NTU Confidential 1

CFO Compensation in Frequency CFO Compensation in Frequency DomainDomain

Presenter: Pin-Hsun LinAdvisor: Prof. Tzi-Dar Chiueh

Date: Aug. 18th 2003

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Outline Outline

• Motivation• Time-delay in a loop

– What are the impacts of delay in a loop? – How the error performance degrades with the

prolonged settling time?– Under what condition the conventional method is

improper? – Loop filter design for a stable system

• With/without consideration of phase error variance• Preliminary remedies

– Frequency domain compensation• Circular convolution, interpolator, rotation

• Conclusion

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Motivation Motivation

• In the 802.11a project the time domain CFO tracking is said to be unstable since there’s a large delay (FFT block)• Find out how the delay affects the burst communication and how to solve the problem caused by the effect efficiently.

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Model of delay in a loopModel of delay in a loop

FFTFFT

CFO Estimato

r

CFO Estimato

r

NCO

NCO

Up to 2 OFDM symbols delay

• Pipeline registers• Latency of signal processing blocks:

―FFT, CFO estimation, TFO estimation, etc.

Some causes of the delay in feedback loop in a communication system include:

ACC

ACC

22

11NCO

NCO

ACC

ACC

If symbol based estimator is used

Example: CFO compensation of OFDM and CP-SC system

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Impacts of delay in a loop: Impacts of delay in a loop:

The optimal natural frequency is decreased [1]

The optimal natural frequency is decreased [1]

The error variance increases [1]

The error variance increases [1]

Delay in a loop increases

Delay in a loop increases

Trade-offThe settling time increases [3] [4].The settling time increases [3] [4].

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Impacts of delay in a loop:Impacts of delay in a loop: the model of loop with delay [1] the model of loop with delay [1]

[2][2]

LO,RLO,T φφ -KDKD

K0/S

K0/S F(s)F(s)

VCO,Rφ

)t(n

∫∫∞

∞-

∞

∞-- dffHfSdffHfS WNPN

WNPN

22

222

|)(|)(|)(1|)(

2

)(

)(

sHs

kksF fp

LOWNPN kPSf

fS ,

2 2

Close loop transfer function

0LPf is the laser line-width

Delay τ

Delay τ

is the LO signal power

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Impacts of delay in a loop:Impacts of delay in a loop: the increased error variance and the the increased error variance and the decreased optimal natural frequency decreased optimal natural frequency

[1][2][1][2]

Bit rate=565Mbps

MHz1=fδ

Optimal loop design

No modification according to the loop delay

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How the error rate performance How the error rate performance degrades with the prolonged settling degrades with the prolonged settling

time?time?

The length of settling time The length of settling time

Accuracy of coarse synchronization

Accuracy of coarse synchronization

Length of training sequence

Length of training sequence

Error rate performance Error rate performance

Delay in a loop Delay in a loop

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Under what condition the Under what condition the conventional method is conventional method is

improper?improper?

If the previous relationship is valid, then under the following conditions the conventional methods are improper:

• In burst communication (not such long time for convergence)• When training symbol is very short like 802.11a

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Loop filter design for a stable system:Loop filter design for a stable system:w/o consideration of phase error w/o consideration of phase error

variance variance [3][3]

0 0.5 1 1.5 2 2.5 3 3.5 40

0.5

1

1.5

2

2.5

3

3.5

4

Kp

Kf

)]12/(,0[

))2/1cos(()2/tan()2/sin(4)(

)2/tan())1sin((2)(

0

M

Mk

Mk

k

f

p

f

Analytical method:

The stable region is enclosed by:

M is the samples of delay

M=0

M=1M=2

(only for 2nd order loop)

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Loop filter design for a stable system:Loop filter design for a stable system:w/o consideration of phase error w/o consideration of phase error

variance variance [4][4]

• Replacing z=exp(u+jv) into the denominator of the loop transfer function.• scan u>0 and v=0~2*pi• The region doesn’t cover by the spirals is the stable region as the right figure shows. 0 0.5 1 1.5 2

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

kp

kf

Numerical method:

M=1, 2nd order loop

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Loop filter design for a stable system:Loop filter design for a stable system:with consideration of phase error with consideration of phase error

variance [5]variance [5]

• Given delay want to find an F(s) that minimizes the phase error variance:

1)()()()(

)(

)(

'

`

sYsMSXsN

sM

sNe

theoremsCauchy

ionapproximatePads

Then F (S) stabilizes the loop iff: NQY

MQXsF

)(

where Q is any stable proper and rational function.

Then find Q by minimizing .2(The solution is complicated so isn’t shown here.)

1.

2.

3.

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Preliminary Remedies Preliminary Remedies

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Compensate the error in Compensate the error in frequency domainfrequency domain

FFTFFTCFO

compensator

CFOcompensat

or

CFO Estimator

CFO Estimator

• The latency of the frequency domain compensator must be smaller than the time domain one.• The additional complexity must be moderate.

Design criterion:

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Frequency domain Frequency domain compensation: compensation:

Circular convolution Circular convolution

• Time domain rotation is equivalent to frequency domain circular convolution.

)n+YHW(E=rn+YHW=r Hd

H ⇒

)n+YHW(AWE

)n+YHW(EEWH

H1-Time domain compensation:

Frequency domain compensation:

H11 WEWN1

=A⇒EW=AW --⇒

A is circulant with 1st row= 1EW -

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Frequency domain Frequency domain compensation: compensation:

Circular convolution (cont’d)Circular convolution (cont’d)

Trunc

ation

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Frequency domain Frequency domain compensation: compensation:

Circular convolution (cont’d)Circular convolution (cont’d)

• The length to be truncated can be determined by:

• The computational complexity can be further optimized by the Chinese remainder theory (CRT) and the latency can be further improved.

• Low latency architecture is under researched.

<σ,|hh|=σ 22truncideal

2 - Required SNR degradation

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Interpolator [6]Interpolator [6]

FFT

FFT

N NP NPinterpolatorinterpolator

N

CFOEstimator

CFOEstimator

Zero padding

Zero padding P P

1st stage 2nd stage

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Interpolator (cont’d)Interpolator (cont’d)

• The constant BER degradation between no CFO and the cubic interpolator may be because not enough information is included to do the compensation.• The sufficient and necessary conditions for the usage of interpolator is needed be investigated.

~0.001

~0.001

CFO normalized to the sub-carrier spacing

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Rotation [7] Rotation [7]

• Rotation is the easiest method with the lowest latency and the worst error performance.

• When CFO is small, the effect of CFO can be considered as a phase rotation.the residual CFO can be compensated by frequency

domain rotation.• The ICI can’t be removed by the rotation.• The resulted SNR degradation is related to how accuracy the

coarse synchronization can achieve.

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Rotation (cont’d)Rotation (cont’d)

0

s2

NE

)R

fΔNπ(

10ln310

2)R

fΔπ(

10ln310D≈

OFDM

SC

BERMlog

SER

2

≤

• Given BER, we can get SER by the following approximation for M-ary modulation :

• Using the SER we can get the corresponding SNR. With the SNR and the following approximation we can get the SNR degradation (SINRnon-ideal-SNRideal in dB).

R is the clock rate

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Conclusion Conclusion

• The impacts of delay in a loop were introduced. • 3 Loop filter design methods for a stabilize a time-

delay system were introduce.• 3 frequency domain compensation methods were

introduced

• Research the relationship between the error rate performance degradation and the prolonged settling time.• Validate the sufficient and necessary conditions for the usage of interpolator.• Merge the circular convolution and the interpolator and find a low latency architecture.

Future work:

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Reference Reference • [1] M. A. Grant, W. C. Michie and M. J. Fletcher, “The performance of optical phase-locked

loops in the presence of nonnegligible loop propagation delay,” IEEE Journal of Lightwave Technology, Vol. 5, No.4, April, 1987, pp. 592-597.

• [2] S. Norimatsu and K. Iwashita, “PLL propagation Delay-time influence on linewidth requirements of optical PSK homodyne detection,” IEEE Journal of Lightwave Technology, Vol. 9, No.10, Oct, 1991, pp. 1367-1375.

• [3] J.W.M. Bergmans, “Effect of loop delay on stability of discrete-time PLL, “Circuits and Systems I: Fundamental Theory and Applications. IEEE Transactions on, Volume: 42 Issue: 4, April 1995, pp. 229 -231

• [4] A. D. Gloria, D. Grosso and M. Olivieri and G. Restani, “A novel stability analysis of a PLL for timing recovery in hard disk drives,” Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on , Volume: 46 Issue: 8 , Aug. 1999 pp. 1026 -1031

• [5] O. Yaniv and D. Raphaeli, “Near-optimal PLL design for decision-feedback carrier and timing Recovery,” IEEE Trans, Commu. Vol. 49, No. 9, Sept 2001, pp. 1669-1678

• [6] M. Luise, M. Marselli and R. Reggiannini, “Low-complexity blind carrier frequency recovery for OFDM signals over frequency-selective radio channels,” Communications, IEEE Transactions on, Vol. 50, No. 7, July 2002 pp. 1182 -1188

• [7] T. Pollet, M. V. Bladel and M. Moeneclaey, “BER sensitivity of OFDM systems to carrier frequency offset and Wiener phase noise,” IEEE Trans, Commu. Vol. 43, No. 2, Feb 1995

• [8] J. R. Barry and J. M. Kahn, “Carrier synchronization for homodyne and heterodyne detection of optical quadriphase-shift keying,” IEEE Journal of Lightwave Technology, Vol. 10, No.12, Dec, 1992.