ch 2 processor
TRANSCRIPT
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Subject : EC 404 Embedded Systems
Chapter-2 : Processors
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Preliminaries
Here we see some general concepts in
computer architecture
including the different styles of computer
architecture the nature of assembly language
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ompu er rc ec ureTaxonomy
von Neumann machine: The memory holds both data and
instructions, and can be read or written when
given an address CPU has several internal registers that
store values used internally. i.e. Program
counter (PC)
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Harvard architecture:
Ithas separate memories for data and program
The program counter points to program memory,
not data memory As a result, it is harder to writeself-modifying programs on Harvard machines
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Advantages of Harvard Arch separation of program and data memories provides
higher performance for digital signal processing
Processing signals in real-time places great strains onthe data
access system in two ways:1) large amounts of data flow through the CPU
2) that data must be processed at precise intervals
Data sets that arrive continuously and periodically are
called streaming data Having two memories with separate ports provides
higher memory bandwidth; not making data andmemory compete for the same port also makes iteasier to move the data at the proper times
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DSPs constitute a large fraction of allmicroprocessors sold today,and most of them are
Harvard architectures.
A single example shows the importance of DSP:
Most of the telephone calls in the world go
through at least two DSPs, one at each end of the
phone call.
Another axis along which we can organize
computer architectures relates to their instructions
and how they are executed
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complex instruction set computers (CISC)machines provided a variety of instructions thatmay perform very complex tasks, such as stringsearching
they also generally used a number of differentinstruction formats of varying lengths
One of the advances in the development of high-performance microprocessors was the concept of
reduced instruction setcomputers (RISC)
These computers tended to provide somewhatfewer and simpler instructions so that they could
be efficiently executed in pipelined processors
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Early RISC designs substantially outperformedCISC designs of the period
As it turns out, we can use RISC techniques toefficiently execute at least a common subset of
CISC instruction sets, so the performance gapbetween RISC-like and CISC-like instruction setshas narrowed somewhat
Beyond the basic RISC/CISC characterization,
we can classify computers by severalcharacteristics of their instruction sets
instruction set of the computer defines theinterface between software modules and theunderlying hardware
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It is the key to analyzing the performance ofprograms. By understanding the types of instructionsthat the CPU provides, we gain insight into alternativeways to implement a particular function
Instructions can have a variety of characteristics:
Fixed versus variable lengthAddressing modes
Numbers of operands
Types of operations supported
The set of registers available for use by programs iscalled the programming model, also known as theprogrammer model
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Assembly Language
An example of ARM assembly language
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It should be remembered that early assemblerswere written
in assembly language to fit in a very small
amount of memory. Those early restrictions have
carried into modern assembly languages by
tradition
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Format of ARM data processing
instructions
ADDGT r0,r3,#5
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Assemblers must also provide some pseudo-opsto help programmers createcomplete assemblylanguage programs
An example of a pseudo-op is one that allows
data values to be loaded into memory locations
These allow constants,for example, to be set into
memory
BIGBLOCK %10
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ARM Ltd The ARM processor core originates within a British
computer company called Acorn. In the mid-1980s theywere looking for replacement for the 6502 processor usedin their BBC computer range
Other companies became interested in this processor,
including Apple who were looking for a processor for theirPDA project. After much discussion this led to Acornsprocessor design team splitting off from Acorn at the end of1990 to become Advanced RISC Machines Ltd, now justARM Ltd.
Thus ARM Ltd now designs the ARM family of RISCprocessor cores, together with a range of other supportingtechnologies.
One important point about ARM is that it does not fabricatesilicon itself, but instead just produces the design - we are
an Intellectual Property (or IP) company. Instead silicon isproduced by companies who license the ARM processor
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Founded in November 1990
Spun out of Acorn Computers
Designs the ARM range of RISCprocessor cores
Licenses ARM core designs tosemiconductor partners who fabricate andsell to their customers.
ARM does not fabricate silicon itself
Also develop technologies to assist withthe design-in of the ARM architecture
Software tools, boards, debug hardware,application software, bus architectures,peripherals etc
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ARM Partnership ModelARMs business model centres around the
principle of partnership. At the centre of this areARMs semiconductor partners who design,manufacture and market ARM-compliant
products. Having so many partner companies producing
silicon executing the same instruction set is avery important part of ARMs strength in themarket place.
However each of our semiconductor partnersbring their own unique strengths to thepartnership - each having their own technologies,applications knowledge, product focus, culture,
geography, and key customers.
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ARM Powered Products
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ARM provides hard and soft views to licencees
RTL and synthesis flows
GDSII layout
Licencees have the right to use hard or soft views of the IP soft views include gate level netlists
hard views are DSMs
OEMs must use hard views
to protect ARM IP
Intellectual Property
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ARM Partnership ModelARMs business model centres around the
principle of partnership. At the centre of this areARMs semiconductor partners who design,manufacture and market ARM-compliant
products. Having so many partner companies producing
silicon executing the same instruction set is avery important part of ARMs strength in themarket place.
However each of our semiconductor partnersbring their own unique strengths to thepartnership - each having their own technologies,applications knowledge, product focus, culture,
geography, and key customers.
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ARM Processor Family
ARM7TDMI
Strong ARM
ARM9
ARM9TDMIARM9E
ARM10E
ARM11
Cortex
XScale
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Example
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ARM processor
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ARM Architecture
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ARM Memory Organization
Different versions of the ARMarchitecture areidentified by different numbers
ARM7 is a von Neumann architecture machine,
while ARM9 uses a Harvard architecture
this difference is invisible to the assembly
language programmer, except for possible
performance differences
heARM architecture supports two basic types ofdata:
The standardARM word is 32 bits long.
The word may be divided into four 8-bit bytes.
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ARM7 allows addresses up to 32 bits long.Anaddress refers to a byte,not a word
So, word 0 in the ARM address space is at
location 0, the word 1 is at 4, the word 2 is at
8,and so on
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General purpose computers have sophisticatedinstruction sets. Some of this sophistication is
required simply to provide the functionality of a
general computer
while other aspects of instruction sets may beprovided to increase performance, reduce code
size, or otherwise improve program
characteristics
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Data operation
In C we consider both arithmetic and logicalinstructions as well as instructions for reading andwriting memory
In the ARM processor, arithmetic and logicaloperations cannot be performed directly onmemory locations
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ARM is a load-store architecture
dataoperands must first be loaded into the CPU and
then stored back to main memory to save the
results
CPSR register is set automatically duringevery arithmetic, logical, or shifting operation
ARM has 16 general-purpose registers, r0
through r15
0 - 1 = -1 : 0x0 - 0x1 = 0xffffffff, with NZCV1000
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Basic ARM programming model
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Arithmetic Instructions
ADD r0,r1,r2
ADD r0,r1,#2
RSB r0, r1,r2
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MUL instruction multiplies two values, but withsome restrictions: 1) No operand may be an
immediate,
2) two source operands must be different
registers
MLA r0,r1,r2,r3 sets r0 to the value r1*r2+r3.
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Logical instructions
exclusive or is called EOR
BIC r0, r1, r2 which sets r0 to r1 and not r2.This instruction uses the second source
operand as a mask Where a bit in the mask
is 1
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Shift/rotate instructions
- LSL and LSR modifiers perform left and right logical shifts, filling
the least- s
significant
- bits of the operand with zeroes
- arithmetic shift left is equivalent to an LSL
-ASR copies the sign bitif the sign is 0, a 0 is copied, while if the
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Comparision & move instruction
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ARM load-store instruction
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The ARM load and store instructions do notdirectly refer to main memory addresses, since a
32-bit address would not fit into an instruction that
included an opcode and operands
Instead,the ARM uses register-indirectaddressing
LDR r0,[r1]
LDR r0,[r1, r2] LDR r0,[r1, #4]
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Register-indirect addressing in the
ARM
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we need to be able to set a register to an arbitrary32-bit value. In the ARM,the standard way to set
a register to an address is by performing
arithmetic on the program counter
By adding or subtracting to the PC a constantequal to the distance between the current
instruction and the desired location, we can
generate the desired address without performing
a load
an ADR pseudo-operation to simplify this step
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Computing an absolute address using the PC
ADR r1,FOO
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C statement : x = (a + b) - c;
Do yourself : y = a (b + c);
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C statement: z = (a
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ARM also supports several forms ofbase-plus-offset addressing
example : LDR r0,[r1,#16] where, r1 is referred
to as the baseand the immediate value the
offset whichmay have
any value up to 4,096. another register may also
be used as the offset
Addressing mode has two other variations : auto-indexing and post-indexing
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Auto indexing: LDR r0,[r1,#16]! first adds 16 to the value of r1, and then uses that
new value as the address
The ! operator causes the base register to be
updated with the computed address so that it can
be used again later
Post-indexing does not perform the offsetcalculation until after the fetch has been
performed
LDR r0,[r1],#16
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The B (branch) instruction is the basic mechanisminARM for changing the flow of control
The address that is the destination of the branch is
often called the branch target
Braches are PC-relative
the branch specifies theoffset from the currentPC value to the branch target
The offset is in words, but because the ARM is byte
addressable,
the offset is multiplied by four (shifted left two bits,actually) to form abyte address
Thus, the instruction B #100 will add 400 to the
current PC value
Flow of Control
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Flow of Control
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C code:
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Implementing C switch statement
The above statement could be coded like an if
statement by first testing testA, then testB, and so
forth. However, it can be more efficiently implemented
by using base-plus-offset addressing and building
what is known as a branch table
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