ch. 5 lecture slides for chenming hu book: modern semiconductor devices for ics

Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-1

Chapter 5 MOS Capacitor

MOS: Metal-Oxide-Semiconductor

SiO2

metal

gate

Si body

Vg

gate

P-body

N+

MOS capacitor MOS transistor

Vg

SiO2

N+

2

This energy-band diagram for Vg = 0 is not the simplest one.

N+po

lysi

licon

SiO

2

P-S

ilico

n bo

dy

Chapter 5 MOS Capacitor

Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Ef , Ec

Ev

Ev

Si Body

Gate

Ec

Ec

Ev

Ef

3

5.1 Flat-band Condition and Flat-band Voltage

E0 : Vacuum levelE0 – Ef : Work functionE0 – Ec : Electron affinitySi/SiO2 energy barrier

sgfbV

SiO2

=0.95 eV

9 eV

Ec, Ef

Ev

Ec

Ev

Ef

3.1 eV q s= Si + (Ec–Ef) qg Si

E0

3.1 eV

Vfb

N+ -poly-Si P-body

4.8 eV

=4.05eV

Ec

Ev

SiO2

The band is flat at the flat band voltage.

q


4

5.2 Surface Accumulation

oxsfbg VVV 3.1eV

Ec ,Ef

Ev E0

Ec

Ef

Ev

M O S

qVg

Vox

qs

Make Vg < Vfb

s is negligible whenthe surface is in

accumulation.

s : surface potential, band bendingVox: voltage across the oxide


5

5.2 Surface Accumulation

fbgox VVV

)( fbgoxacc VVCQ

oxsox CQV /

oxaccox CQV /Gauss’s Law


Vg <Vt

6

ox

ssa

ox

depa

ox

dep

ox

sox C

qN

C

WqN

C

Q

C

QV

2

5.3 Surface Depletion ( )gV > Vfb

Ec, Ef

Ev

Ec

Ef Ev

M O S

qVg

depletion

region

qs

Wdep

qVox

- - --SiO

2

gate

P-Si body

+ + + + + +

- - - - - - - V

- - - - - - - depletion layer charge, Q dep

- - - - - - -


7

5.3 Surface Depletion

ox

ssasfboxsfbg C

qNVVVV

2

This equation can be solved to yield s .


8

5.4 Threshold Condition and Threshold Voltage

Threshold (of inversion):ns = Na , or

(Ec–Ef)surface= (Ef – Ev)bulk , or

A=B, and C = D

i

aBst n

N

q

kTln22

i

a

a

v

i

vbulkvf

gB n

N

q

kT

N

N

q

kT

n

N

q

kTEE

Eq lnlnln|)(

2

Ec,Ef

M O S

Ev

Ef

Ei

Ec

A

B

C = q

Ev

DqVg

= qVt

st


9

Threshold Voltage

ox

BsaBfbgt C

qNVthresholdatVV

222

oxsfbg VφVV

At threshold,

i

aBst n

N

q

kTln22

ox

Bsaox C

qNV

22


10

Threshold Voltage

ox

BssubBfbt C

qNVV

222 + for P-body,

– for N-body (a)

(b)

Tox = 20nm

Vt(V

), N

+ ga

te/P

-bod

y

Vt(

V),

P+ g

ate/

N-b

ody

Body Doping Density (cm-3)

Body Doping Density (cm-3)

Vt(

V),

P+ g

ate/

N-b

ody

Vt(

V),

N+ g

ate/

P-bo

dy

Tox = 20nm


11

5.5 Strong Inversion–Beyond Threshold

Ec,Ef

Ev

Ec

Ef

Ev

M O S

qVg

-

-

- - --

a

Bsdmaxdep qN

WW 22

Vg > Vt

SiO2

gate

P- Si substrate

++++++++++

V

Vg > Vt

- - - - - --- - - - - - - -

Qdep

Qinv


12

Inversion Layer Charge, Qinv (C/cm2)

ox

invt

ox

inv

ox

BsaBfb

ox

inv

ox

depBfbg

C

QV

C

Q

C

qNV

C

Q

C

QVV

2222

)( tgoxinv VVCQ


Vg > Vt Vg > Vt

13

5.5.1 Choice of Vt and Gate Doping Type

Vt is generally set at a small positive value so that, at Vg = 0, the transistor does not have an inversion layer and current does not flow between the two N+ regions

• P-body is normally paired with N+-gate to achieve a small positive threshold voltage.• N-body is normally paired with P+-gate to achieve a small negative threshold voltage.


14

Review : Basic MOS Capacitor Theorys

2B

Vfb Vt

Vg

accumulation depletion inversion

Wdep

Wdmax


s)

1/2

Wdmax = (2s2 qa

VgVt

Vfb


15

Review : Basic MOS Capacitor Theory

0

Vg


Qinv


(a)

(b)


(c)

Qs

0

accumulation regime

depletion regime

inversion regime

total substrate charge, Qs

invdepaccs QQQQ

Qacc

Vg

Vg

Qdep=- qNaWdep

VtVfb

slope = Cox

slope = Cox VtVfb

Vt

Vfb

–qNaWdep

–qNaWdmax

Vg

Qinv

slope = Cox

Vfb

Vt


16

5.6 MOS CV Characteristics

g

s

g

g

dV

dQ

dV

dQC

C-V Meter

MOS Capacitor


17

5.6 MOS CV Characteristics

g

s

g

g

dV

dQ

dV

dQC

Qs

0

Vg

accumulation regime

depletion regime

inversion regime

Qinv

C

Vfb Vt

Cox

accumulation depletion inversionVg

Vt

Vfb

slope = Cox


18

CV Characteristics

depox CCC

111

sa

fbg

ox qN

VV

CC )(211

2

CCox


VgVfb Vt

In the depletion regime:


19

Cox

gate

P-substrate

-

-

-

-

- -- Cdmax

Wdmax

- - - - - - -

AC

DC

+++++ + + + +

Cox

gate

P-substrate

Cox

gate

P-substrate

- - - - - - Cdep Wdep

Cox

gate

P-substrate

-

Wdmax

- - - - - - -N+

DC and AC

Supply of Inversion Charge May be Limited

Accumulation Depletion

Inversion

Inversion

In each case, C = ?


20

Capacitor and Transistor CV (or HF and LF CV)


21

Quasi-Static CV of MOS Capacitor

The quasi-static CV is obtained by the application of a slow linear-ramp voltage (< 0.1V/s) to the gate, while measuring Ig with a very sensitive DC ammeter. C is calculated from Ig = C·dVg/dt. This allows sufficient time for Qinv to respond to the slow-changing Vg .

CCox


VgVfb Vt


22

(1) MOS transistor, 10kHz. (Answer: QS CV).

(2) MOS transistor, 100MHz. (Answer: QS CV).

(3) MOS capacitor, 100MHz. (Answer: HF capacitor CV).

(4) MOS capacitor, 10kHz. (Answer: HF capacitor CV).

(5) MOS capacitor, slow Vg ramp. (Answer: QS CV).

(6) MOS transistor, slow Vg ramp. (Answer: QS CV).

EXAMPLE : CV of MOS Capacitor and Transistor

Does the QS CV or the HF capacitor CV apply?

C

Vg

QS CV

HF capacitor CV

MOS transistor CV,


23

5.7 Oxide Charge–A Modification to Vfb and Vt

oxoxsgoxoxfbfb CQCQVV //0

Ef, Ec

Ev

Ec

E f

Ev

Vfb0

gate oxide body

Ef, Ec

Ev

Ec

E f

Ev

Vfb

gate oxide body

+ + +

Qox

/Cox

(a) (b)


24

Types of oxide charge:

• Fixed oxide charge, Si+

• Mobile oxide charge, due to Na+contamination

• Interface traps, neutral or charged depending on Vg.

• Voltage/temperature stress induced charge and traps--a reliability issue

5.7 Oxide Charge–A Modification to Vfb and Vt


25

EXAMPLE: Interpret this measured Vfb dependence on oxide

thickness. The gate electrode is N+ poly-silicon.

oxoxoxsgfb TQV /Solution:

What does it tell us? Body work function? Doping type? Other?

0

–0.15V

–0.3V

Tox

Vfb

10 nm 20 nm 30 nm


26

from intercept V 15.0 sg

from slope 28 cm/C 107.1 oxQ

-317eV 15.0 cm 10 kTcd eNnNN-type substrate,

E0, vacuum level

Ef, E

c

Ev

Ec

Ef

Ev

g s = g + 0.15V

N+-Si gate Si body


27

5.8 Poly-Silicon Gate Depletion–Effective Increase in Tox

Gauss’s Law polyoxoxdpoly qNW /E

3/

1111

dpolyox

ox

s

dpoly

ox

ox

polyox

WT

WT

CCC

If Wdpoly= 15 Å, what is the effective increase in Tox?

Cox

N-body

Cpoly

++ + + + + + +P+

Wdpoly

E

c

Ef, Ev

Ec

Ef

Ev

qpoly

P+-gate N-substrate

(a) (b)

P+ poly-Si

P+


28

Effect of Poly-Gate Depletion on Qinv

)( tpolygoxinv VVCQ

• How can poly-depletion be minimized?

Wdpoly

Ec

Ef , Ev

Ec

Ef

Ev

qpoly

P+ -gate N-substrate

• Poly-gate depletion degrades MOSFET current and circuit speed.


29

EXAMPLE : Poly-Silicon Gate Depletion

Vox , the voltage across a 2 nm thin oxide, is –1 V. The P+poly-gate doping is Npoly = 8 1019 cm-3 and substrate Nd is 1017cm-3. Find (a) Wdpoly , (b) poly , and (c) Vg .

Solution:

(a)

nm 3.18C106.1cm102

V 1)F/cm(1085.89.3

//

197

14

cm10 319

polyoxoxoxpolyoxoxdpoly qNTVqNW E


30

(b) poly

polysdpoly qN

W2

V 11.02/2 sdpolypolydpoly WqN

(c)

V 01.1V 11.0V 1V 85.0V 95.0

V 95.0V 15.0 V 1.1ln

g

d

cgfb

polyoxstfbg

V

N

N

q

kT

q

EV

VVV

Is the loss of 0.11 V from the 1.01 V significant?

EXAMPLE : Poly-Silicon Gate Depletion


31

5.9 Inversion and Accumulation Charge-Layer Thickness–Quantum Mechanical Effect

Average inversion-layer location below the Si/SiO2 interface is

called the inversion-layer thickness, Tinv .

n(x) is determined by Schrodinger’s eq., Poisson eq., and Fermi function.

-50 -40 -30 -20 -10 0 10 20 30 40 A

Electron Density

Quantummechanical theory

SiO2poly-Sidepletionregion

Å50

Tinv SiGate

Effective Tox

Physical Tox


32

Electrical Oxide Thickness, Toxe

• Tinv is a function of the average electric field in the inversion layer, which is (Vg + Vt)/6Tox (Sec. 6.3.1).• Tinv of holes is larger than that of electrons because of difference in effective mass.•Toxe is the electrical oxide thickness.

3/3/ invdpolyoxoxe TWTT at Vg=Vdd


33

Effective Oxide Thickness and Effective Oxide Capacitance

)( tgoxeinv VVCQ

C Basic CV

with poly-depletion

with poly-depletion and charge-layer thickness

Vg

measured data

Cox

3/3/ invdpolyoxoxe TWTT


34

Equivalent circuit in the depletion and the inversion regimes

Cpoly

Cox

Cdep Cinv

Cox

Cdep

Cpoly

Cox

Cdep, min CinvCinv

Cox

(a) (b) (c) (d)

General case for both depletion and inversion regions.

In the depletion regions

Vg Vt Strong inversion


35

5.10 CCD Imager and CMOS Imager

Deep depletion, Qinv= 0 Exposed to light

5.10.1 CCD Imager

+

---

Ec, E

f

Ev

Ec

Ef

Ev

Ec, E

f

Ev

(a) (b)

-


36

CCD Charge Transfer

P-Si

oxide

V2

- - -- - - -- - - - --- -depletion region

P-Si

oxide- - -- - - --

depletion region

P-Si

oxide- - -- - - -- depletion region

(a)

(b)

(c)

V1 > V2 = V3

V1

V2

V3

V1 V3 V1 V2 V3 V1

V2 > V1 > V3

V2 > V1 = V3

V1V2 V3 V1

V2 V3 V1


37

two-dimensional CCD imager

The reading row is shielded from the light by a metal film. The 2-D charge packets are read row by row.

Signal out

Charge-to-voltage converterReading row,

shielded from light


38

5.10.2 CMOS Imager

CMOS imagers can be integrated with signal processing and control circuitries to further reduce system costs. However, The size constrain of the sensing circuits forces the CMOS imager to use very simple circuits


PN junction charge

collector

switch

Amplifier circuit

Shifter circuit Signal out

V2

V1

V3

39

5.11 Chapter Summary

N-type device: N+-polysilicon gate over P-body

P-type device: P+-polysilicon gate over N-body

)/( oxoxsgfb CQV

polyoxssfb

polyoxsfbg

CQV

VVV

/


40

i

subB n

N

q

kTln

Bst 2 )V 45.0( Bor

ox

stssubstfbt C

qNVV

||2

+ : N-type device, – : P-type device



41

N-type Device(N+-gate over P-substrate)

P-type Device(P+-gate over N-substrate)

What’s the diagram like at Vg > Vt ? at Vg= 0?

Ef

Ef

Vg >Vfb >0

Ef

Ef

Vg <Vfb <0Accumula tion

Ef

Ef

Vg =V fb<0

Ef

Ef

Vg =Vfb >0 Flat-band

EfEf

Vg0> Vfb

EfEf

Vg0<Vfb

Ef

Vg =V t>0

Ef

Ef

Ef

Vg =Vt <0 Threshold

Depletion

Ef

Ef

Vg >Vt>0

Ef

Ef

Vg <Vt

Inversion

N-type D evice(N+-gate over P-substrate)

P -type Device(P+-gate o ver N-sub strate)

Ef

Ef

Vg >Vfb >0

Ef

Ef

Vg <Vfb <0Accumula tion

Ef

Ef

Vg =V fb<0

Ef

Ef

Vg =Vfb >0 Flat-band

EfEf

Vg0> Vfb

EfEf

Vg0<Vfb

Ef

Vg =V t>0

Ef

Ef

Ef

Vg =Vt <0 Threshold

Depletion

Ef

Ef

Vg >Vt>0

Ef

Ef

Vg <Vt

Inversion

N-type D evice(N+-gate over P-substrate)

P -type Device(P+-gate over N-substrate)



42

What is the root cause of the low C in the HF CV branch?


Vg

N-type Device(N+-gate over P-substrate)

P-type Device(P+-gate over N-substrate)

Vg

QS CVTransistor CV

Capacitor (HF) CV


ch. 5 lecture slides for chenming hu book: modern semiconductor devices for ics

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