CH. 9 Design via Root Locus

Figure 9.1a. possible design point vi

a gain adjustment (A)

design point that cannot be met via gain adjustmen

t (B);需補償器設計

9.1 Introduction

Figure 9.1a. possible design point via gain adjustment (A)

design point that cannot be met via gain

adjustment (B);

Figure 9.1 (b) responses from poles at A

and B

9.1 Introduction

補償器種類

Figure 9.2 Compensation

techniques:a. cascade;b. feedback

• 9.2 節 : design of cascade compensation to improve ess

• 9.3 節 : design of cascade compensation to improve 暫態反應

• 9.4 節 : design of cascade compensation to improve both ess and

暫態反應• 9.5 節 : design of feedback compensation

9.2 cascade compensation to improve steady-state error

•改善 ess 補償器 3種 1/S : idea integral compensator 理想積分器

→ ess = 0 亦變 transient response Fig.9.3b (i.e. 變根軌跡圖 )

K1 + K2/S : PI controller ( Proportional-plus-Integral) → ess = 0 可不變 transient response Fig.9.3c

(S+Zc)/(S+Pc) : Pc ＜ Zc Lag Compensator

→ ess ↓ 可不變 transient response

Figure 9.3a. root locus

b. not on the root locus with 1/S compensator added

此設計已無從獲致系統 A

• 補償器 1/S : idea integral compensator → ess = 0

∵ system type 增 1 ess = finite → ess = 0 ( 缺點 active network)

( 缺點 變 transient response)

Figure 9.3 c. on root locus with PI compensator added當 a 甚小 → 0

不變 transient response PI controller 補償

• (S + a)/S : PI controller ( Proportional-plus-Integral)

→ ess = 0 ∵ system type 增 1 可不變 transient response 當 a 甚小 Fig.9.3c ( 缺點 active network)

( 不變 transient response)

補償器 (S+Zc)/(S+Pc) : Pc ＜ Zc Lag Compensator

暫態反應 okay 希望調降穩態誤差

暫態反應 okay 維持 P 點； Zc → Pc 控制器角度貢獻 → 0

Figure 9.4 Closed-loop system for Example 9.1: 設計目標 : 希望 ess = 0 ； 不變 transient response

( 下頁說明控制器選擇 )

before compensation

after PI compensation

•改善 ess 補償器 3種 ( 控制器選擇 )

1/S : idea integral compensator 理想積分器

→ ess = 0 亦變 transient response Fig.9.3b (i.e. 變根軌跡圖 )

K1 + K2/S : PI controller ( Proportional-plus-Integral) → ess = 0 可不變 transient response Fig.9.3c

(S+Zc)/(S+Pc) : Pc ＜ Zc Lag Compensator

→ ess ↓ 可不變 transient response

Figure 9.5Root locus for uncompensated system of Fig. 9.4(a) 3 階系統

Figure 9.6Root locus for compensatedsystem of Figure 9.4(b)

Example 9.1

Figure 9.7 time response PI compensated system response and the uncompensated system

response of Example 9.1

設計目標 : ess = 0 不變 transient response

Figure 9.8PI controller

1/11

1. 未補償系統 ζ= 0.174 → 根軌跡決定系統位置2. ess 降低 10 倍 → 先求未補償系統的 ess

Uncompensated system先畫根軌跡 找出系統現況 2/11

Uncompensated system 找未補償系統的穩態誤差

e(∞) = 1/(1 + Kp) = 0.108 Kp =lims→0 G(s) =164.6/20 = 8.23

3/11

•改善 ess 補償器 3種 ( 控制器選擇控制器選擇 ) 4/11

1/S : idea integral compensator 理想積分器

→ eess ss = 0 = 0 亦變亦變 transient response Fig.9.3b (i.e. 變根軌跡圖 )

K1 + K2/S : PI controller ( Proportional-plus-Integral) → eess ss = 0 = 0 可不變 可不變 transienttransient response Fig.9.3c

(S+Zc)/(S+Pc) : Pc ＜ Zc Lag Compensator

→ eess ss ↓↓ 可不變可不變 transienttransient response

5/11

e(∞) = 1/(1 + Kp) = 0.108

Kp = lims→0 G(s)= 164.6/20 = 8.23

ec(∞) = 0.0108由 Gc(s) 調整

7/11Uncompensated system

Figure 9.12 Compensated system of Figure 9.11 8/11ec(∞) = 0.0108 = 1/(1 + Kpc)

Kpc = lims→0 Gc(s)G(s) = lims→0 Gc(s) Kp

= lims→0 Gc(s) 8.23 = 91.593

lims→0 Gc(s) = Zc/Pc = 11.132

Gc(s) = (s+Zc)/(s+Pc)

→ 取 Pc=0.01 → Zc=0.111

Table 9.1Predicted characteristics of uncompensated and lag-

compensated systems for Example 9.2

9/11

Figure 9.13Step responses of uncompensated and lag-compensated systems for

Example 9.2 10/11

Figure 9.14Step responses of the system for Example 9.2

lag compensator 更趨近原點 → 反應較慢 最終之 ess 不變 11/11

執行 Lag compensation 的相關公式

9.3 Improving Transient Response via Cascade Compensation

•改善 暫態反應 補償器 3種 S : pure differentiator 純微分器

S + Zc : PD controller ( Proportional-plus-Derivative)

(S+Zc)/(S+Pc) : Pc ＞ Zc Lead Compensator 超前補償

器

Figure 9.15 Using PD compensation (S + Zc) 改變暫態反應 %OS 不變 1/3

a. uncompensated; b. compensator zero at –2;c. compensator zero at –3; d. compensator zero at – 4

Figure 9.16 time response 2/3 Uncompensated system and ideal derivative compensation solutions from Table 9.2

Table 9.2Predicted characteristics for the systems of Figure 9.15 3/3

Example 9.3 : S + Zc : PD controller

Figure 9.17Feedback control system 1/7

設計目標 : 補償後系統 %OS = 16% i.e. ζ=0.504 tsc = ts/3

Figure 9.18 Example 9.3 Root locus for uncompensated system 2/7

先求未補償系統位置 %OS = 16% →ζ=0.504

次求未補償系統 ts ts = 4/(ζωn) = 4/1.205 = 3.32

Figure 9.18 Example 9.3 Root locus for uncompensated system 2/7

Figure 9.19 Compensated dominant pole superimposed over the uncompensated root locus for Example 9.3 3/7

希望補償後 dominant poles = -3.613± j6.192 → G∠ c(s)G(s) = 1800 目標設計 Gc(s) = S + Zc PD controller

希望補償後 tsc= 3.32/3 = 1.107

→ (ζωn)c = 3.613 → %OS 不變 →補償後 dominant poles = -3.613± j6.192

Figure 9.20 4/7Evaluating the location of the compensating zero for Example 9.3

希望之角度補償 ∠ S + Zc = 1800 －∠ G(s)

Figure 9.21Root locus for the compensated system of Example 9.3 5/7

Figure 9.22 time response Uncompensated and compensated system step responses ofExample 9.3 6/7

Table 9.3Uncompensated and compensated system characteristics for Example 9.3 7/7

Figure 9.23PD controller S + Zc

Example 9.4 Lead compensator design (S+Zc)/(S+Pc) : Pc ＞ Zc

設計目標 : 補償後系統 %OS = 30% i.e. ζ=0.358

tsc = ts/2

Figure 9.26 uncompensated and compensated dominant poles

∠kG(s) = -1800 目標 →∠ Gc(s) + kG(s)∠ = -1800

∠Gc(s) = ∠(S+Zc)/(S+Pc) = θc

超前控制器設計 → 選擇 Lead compensator 貢獻的角度

Figure 9.25Three of the infinite possible lead compensator solutions Lead compensator 貢獻的角度

(S+Zc)/(S+Pc) : Pc ＞ Zc

∠(S+Zc)/(S+Pc) = θc 正值 超前控制器

目標 →∠ Gc(s)G(s) = 1800

超前控制器設計 → 選擇 Lead compensator 貢獻的角度→ ∠Gc(s) = ∠(S+Zc)/(S+Pc) = θc

Table 9.4 Comparison of lead compensation designs for Example 9.4

Which is the best design?

系統階數 ?是否有 2 個主要極點 ?是否有零點 ? 能否抵消 ?比較規格達成度 確認最佳設計

Figure 9.28Compensated system root locus (which is this design?)

Figure 9.29Uncompensated system and lead compensation responses forExample 9.4

9.4 design of cascade compensation to improve both ess and 暫態反應

• improve both 暫態反應 first

• then improve ess

• Example 9.5 自修

•改善 ess 補償器 3種 1/3 1/S : 積分器 → ess = 0 (S + a)/S : PI 控制器 → ess = 0 (S+Zc)/(S+Pc) : Pc ＜ Zc Lag Compensator → ess ↓ 控制器設計原則 : 選 pole, zero 近原點 , 維持暫態反應不變•改善 暫態反應 補償器 3種 S : 微分器 S + Zc : PD 控制器 (S+Zc)/(S+Pc) : Pc ＞ Zc Lead Compensator

•同時改善 暫態反應 和 ess

PID 控制器 : (S + Zc) (S + a) / S

Lag-Lead 補償器 : [(S+Zc)/(S+Pc)]Lead [(S+Zc)/(S+Pc)]Lag

設計原則 : 先調暫態反應 再調穩態誤差

1. 繪未補償系統根軌跡a. 根軌跡條數 =3 %OS=20% i.e. ζ= 0.456

b. 實軸上根軌跡

c. 漸近線 (3 zeros at ∞ )

•Ex. 9.6 Fig.9.37

• %OS=20% i.e. ζ=0.456

•Tsc=Ts/2 Ts=4/(ζωn)

•essc= ess/10

kGH(s) =

= -16/3

= π/3 ； π ； 5π/3

2/3

1. 繪未補償系統根軌跡

d. Breakaway point 1+kGH(s) = 0 k(s) = -1/ [GH(s)] → dk/ds = 0 → s = -2.43; - 8.24( 不適用 )

e.trial-and-error ∠GH(s) = -1800 find 未補償系統 at s = -1.794± j 3.501 ∣ kGH(s) = 1 ∣ → k = 192.1

2. 先調暫態反應f. 補償後系統位置 Ts=4/(ζωn) = 4/1.794

Tsc=Ts/2 → (ζωn)c = 2(1.794) 補償後系統 at s = -3.588± j 7.003

3/3

4/52. 先調暫態反應

g. Lead 補償器 GcL(s) 設計 補償後系統 at s = -3.588± j 7.003 GcL(s) 角度貢獻 ∠GcLGH(s) = -1800

∠GcL(s) = -1800 - GH(s) ∠ = -1800 – (-164.650) = - 15.350

GcL(s)= (S+Zc)/(S+Pc) Pc ＞ Zc

選 Zc = 6 → Pc = 29.1

∣k GcL(s)GH(s) = 1 → k = 1977∣

3. 後調穩態誤差 essc= ess/10 ess=1/Kv

Kv=lims→0 skGH(s)= 192.1/60 ess=1/Kv=60/192.1 h. Lag 補償器 GcLag(s) 設計 經 Lead 補償後系統 at s = -3.588± j 7.003

Lag 補償器 需維持 system at s = -3.588 ± j 7.003

且降 essc= ess/10 = 60/1921 k GcLag(s) GcLGH(s) Type1 系統 GcLag(s)= (S+Zc)/(S+Pc) Pc ＜ Zc

i.e. Kvc=lims→0 s GcLag(s) kGcLGH(s) = 1921/60 lims→0 GcLag(s) = (Zc/Pc )(1977/291) = 1921/60