ch2- selection of a topology to meet the design requirements

8/22/2019 Ch2- Selection of a Topology to Meet the Design Requirements

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TABLE OF CONTENTS

Page

LIST OF TABLES xi

LIST OF FIGURES xii

LIST OF APPENDICES.. xiv

PREFACE xv

Chapter

1. INTRODUCTION 1

2. SELECTION OF A TOPOLOGY TO MEET THE DESIGN

REQUIREMENTS... 5

2.1. Selection of a suitable topology 5

2.2. Cascaded Buck-Boost PFC Converter 9

2.2.1 Basic Operation of the Buck and Boost Circuits.. 9

2.2.2 Basic Operation of the Cascaded Buck-Boost Converter 15

2.2.3 Steady State analysis of the cascaded buck-boost converter... 16

2.3. Basic Operation of the SEPIC circuit. 17


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Chapter Page

2.3.1 Steady State Analysis of the SEPIC Converter. 18

3. LOSS ANALYSIS. 21

3.1. Loss Analysis in the Cascaded Buck-Boost Converter.. 21

3.1.1 Input Rectifier Bridge.. 21

3.1.2. Conduction Losses of the Buck and Boost Switches. 23

3.1.3. Switching Losses of the Buck and Boost Switches 24

3.1.4. Conduction Losses of the Buck and Boost Diodes 27

3.1.5. Reverse Recovery Switching Losses of the Buck and Boost

Diodes. 28

3.1.6. Capacitor Loss 29

3.1.7. Inductor Loss. 29

3.2. Advantages and Disadvantages of the Cascaded Buck-Boost Circuit.. 30

3.2.1. Advantages. 30

3.2.2. Disadvantages 30

3.3. SEPIC PFC Circuit... 30

3.3.1. Determination of the Switch Duty Cycle.. 31

3.3.2. Conduction Losses of the Input Rectifier Bridge. 32

3.3.3. Conduction Loss of the Switch.. 32

3.3.4. Switching Loss of the Switch 33

3.3.5. Conduction Loss of the Diode... 33


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Chapter Page

3.3.6. Switching Loss of the Diode. 33

3.3.7. Capacitor Loss.. 34

3.3.8. Inductor Loss. 34

3.4. Advantages and Disadvantages of the SEPIC Converter. 34

3.4.1. Advantages. 34

3.4.2. Disadvantages 35

3.5. Comparison of the Two Topologies 35

3.5.1. Efficiency.. 35

3.5.2. Device Stress. 36

3.5.3. Complexity 36

4. CONTROL STRATEGY FOR THE PRECONDITIONER CIRCUIT.. 38

4.1. Background.. 38

4.2. Different Control Strategies 38

4.2.1. Peak Current Control... 38

4.2.2. Average Current Control. 39

4.2.3. Hysteresis Control... 39

4.2.4. Boundary Conduction Mode Control.. 40

4.3. Brief Description of the L6561 chip.. 42

4.4. Transition Mode of the PFC Operation of the Cascaded Buck-Boost

Converter 45


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Chapter Page

4.5. Control Loop Modeling of the L6561 based Converter... 47

4.5.1. Components of the Control Loop. 48

4.6. Derivation of the Transfer Function of each block of the Control Loop.. 48

4.6.1. Power Stage. 48

4.6.2. Transfer Function of the PWM Modulator.. 53

4.6.3. Transfer Function of the Multiplier. 54

4.7. Control Objective 55

4.8. Feedback Compensator Design.. 56

4.8.1. Derivation of the Transfer Function of the Error Amplifier 58

4.9. Summary 61

5. PSPICE SIMULATION OF THE PRECONDITIONER CIRCUIT 62

5.1. Background 62

5.2. Simulation of the Peak Current Control 63

5.3. Simulation of the Zero Current Detect.. 65

5.4. Simulation of the Over voltage Protection. 66

5.5. Modeling the Voltage Error Amplifier.. 67

5.6. Modeling the Converter. 68

5.7. Modeling the Load. 68

5.8. Results 70

6. CONCLUSIONS.. 78


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x

Chapter Page

BIBLIOGRAPHY 81

APPENDICES. 86


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CHAPTER 2

SELECTION OF A TOPOLOGY TO MEET THE DESIGN REQUIREMENTS

2.1. Selection of a suitable topology

The objective of this chapter is to choose a PFC topology that would meet the

design specifications for a high input voltage high output power pre-conditioner circuit.

The design specifications of the pre conditioner circuit are given in Table-1.

Table 1: Design Specifications of the Pre-conditioner Circuit.

Input Voltage 347V-480V

Output Voltage 480V

Output Power 400W

Efficiency 0.95

Losses


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be low, thus minimizing the noise generated at the input and therefore, on the

requirements on the input EMI filter.

3. The switch is source-grounded, therefore it is easy to drive.

Fig. 2.1. Boost Converter Scheme.

The factors which make a boost converter unsuitable for the work considered in

this thesis are outlined first. The boost topology requires the DC output voltage to be

higher than the maximum expected peak line voltage. For a high input voltage range

(347-480V), using a Boost would require the output voltage to have a magnitude of

750V.This would imply higher losses and higher voltage and current rating devices,

which will not be cost-effective. The higher voltage and current rated components also

lead to higher losses. Also, a boost converter designed for the input range considered in


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this work would be heavily oversized compared to any other converter because the

inductor has to be sized for the highest volt-seconds applied throughout the input-line

range [2]. The boost converter has a large energy storage filter capacitor at the output,

resulting in the inrush current problem which can be eliminated by using additional

components, thus increasing the costs [2].

The HID lamps require 230V-240V as their open circuit voltage. The lamp driver

used is the half-bridge resonating driver, so the DC voltage bus should be nearly twice

the open-circuit voltage, so that is around 460-480V. Thus the output voltage is set at

490+/-10%.

With the wide input voltage range considered, the topologies to be considered are

those which give the flexibility of the output voltage to be lesser or greater than the input

voltage. DC-DC converters with step-up/step down characteristics are required in all

applications where the input and the output voltage range overlap. In power factor

correction (PFC) applications, the use of step-up/step-down converters such as the buck-

boost, SEPIC or CUK allows one to set the output DC voltage to an arbitrary

intermediate value. For one given DC operating point, it is well known that the buck or

the boost perform conversion with lower component stresses and energy storage

requirements than the single switch step-up/step-down converters [2].

Paralleling or multi-leveling techniques can be used to share current or voltage

stresses at the expense of more switching components. Neither of these approaches aims

at reducing the current or voltage stresses at the same time.


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The buck-boost topology, fly back, SEPIC topologies have the step-up/step-down

capabilities. Therefore they all are relevant candidates to meet the input-output

specifications of the design mentioned in this work [4, 6, 30, 32].

In the conventional buck-boost, there is the problem of the inversion of the

output voltage. Topologies that offer the flexibility of the output voltage without the

inversion of the polarity would be considered a better option. The plain buck-boost, fly

back, Single Ended Primary Inductance Converter (SEPIC) and CUK converters seem the

possible options then. These converters have greatly increased component stresses,

component sizes and reduced efficiency compared to the boost converter [2, 33, 34]. To

reduce the losses caused by these high voltages, a circuit with buck-boost conversion

characteristics, losses comparable to the boost converter and smaller inductor size is

desired.

Thus, the optimum converter however should have low component stresses, low

energy storage requirements and size and efficiency performance comparable to the boost

or the buck converter.

Taking the above-mentioned issues into consideration, the two topologies that

seem to be ideal for such an application are the Cascaded Buck-Boost topology and the

SEPIC (Single-ended Primary Inductance Converter) topology. Another reason for

choosing these topologies is that not much work had been done on them earlier and it

provided an opportunity for an analysis in detail. In this chapter, the basic operation of

these two topologies is explained followed by a loss analysis in the next chapter.


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2.2 Cascaded Buck-Boost PFC Converter

The cascaded buck-boost topology, shown in Fig. 2.2, will be discussed first. The

basic operation of the buck and boost converters are discussed first followed by the

steady state analysis of the cascaded buck-boost converter.

Fig. 2.2. Cascaded Buck-Boost Converter

2.2.1 Basic Operation of the Buck and Boost Circuits

The cascaded buck-boost topology is a conventional buck converter cascaded with a

boost topology. The basic buck and boost mode operations are discussed first.The buck

converter is shown in Fig. 2.3.

Buck Converter Operation


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Fig. 2.3. Buck Converter

V0 2 Vrms<

As seen in Fig. 2.4, the conversion ratio of the buck converter is given by M (D) =D. This

is represented in Eq.2.1.

V

V

t

T

o

i

on=(2.1)

Where T = total period

ont is the switch on time

DV

V

i

=0 (2.2)

D is the duty cycle of the switch

When the switch is turned ON, the voltage across the inductor is given by

V Ldi

dtV VL i o= =

(2.3)


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When the switch is turned OFF, since the current through the inductor L cannot

change instantaneously, the diode provides the freewheeling path for the current to flow

through the load. During this period the voltage across the inductor is given by

0* Vdt

diLV ll == (2.4)

The current through the inductor during the on time is given by Eq. 2.5.

TDL

VVI il **

)( 0= (2.5)

The discharge portion of the current through the inductor is given by Eq. (2.6).

TDL

VIl *)1(*

0 = (2.6)

Equating Eq. (2.5) and Eq. (2.6), the conversion ratio of the buck converter is given in

Eq. (2.7).

Thus the conversion ratio of the converter is given by Eq.2.7

V

V

t

T

o

i

on=

(2.7)


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The conversion ratio is given in Fig. 2.4.

Fig. 2.4. Conversion Ratio of Buck Converter

Boost Converter Operation

V0 2 Vrms>

When the output voltage is greater than the instantaneous line voltage, the circuit

operates in the boost mode.

The basic boost converter topology is shown in Fig.2.5.

M(D)=D

M(D)

D


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Fig. 2.5. Boost Converter

When the switch is closed, the source voltage sV is applied across the inductor.

The rate of rise of inductor current is dependent on the source voltage and inductance L.

The differential equation describing this condition is:

)(tV

dt

diL s

L

=(2.8)

The current through the inductor during the on-time is given by Eq. (2.8).

L

tVI onsL

*= (2.9)

When the switch is open, the voltage across the inductor is:

V V VL s o= (2.10)

The discharge current through the inductor is given by Eq.2.8.

TDL

VVI sL *)1(*

0

= (2.11)


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The sum of net changes in inductor current expressed by (2.8) and (2.10) should

be zero [32]. That is,

V

LDT

V V

LD T

s s o

+

=( )1 0(2.12)

On simplifying equation (2.9), we get that

VoVs

D=

1(2.13)

The value of D varies such that 0 < D < 1 and it can be seen from Eq. (2.13) that output

voltage is greater than the source voltage, and hence this circuit is called the boost

converter. The conversion ratio of the boost converter is given in Fig. 2.6.

Fig. 2.6. Conversion Ratio of a Boost Converter

The operating condition of the boost converter is shown in Fig. 2.7.

M(D)=1/1-D

M(D)

D


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Fig. 2.7. Boost Mode of Operation

2.2.2. Basic Operation of the Cascaded Buck Boost Converter

The cascaded buck-boost topology is the buck converter cascaded with the boost

converter. This offers the advantage of the elimination of the inversion of the output

voltage which is seen in the conventional buck-boost converter. In this thesis, both the

switches will be controlled simultaneously. Thus depending on the input voltage, the duty

cycle of the switches will be varied to obtain the desired output voltage. Thus if the input

voltage is higher than the output voltage, the duty cycle is adjusted so that the converter

operates like a buck converter and if the input voltage is lower than the output voltage the

duty cycle is varied so that the converter performs the boost function. The variation of the

duty cycle with the input voltage is given in Table-2 and the calculations are shown in

detail in Appendix A.


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Table 2: Variation of Duty Cycle with the Input Voltage

INPUT VOLTAGE DUTY CYCLE

312V 0.606

347V 0.58

480V 0.5

528V 0.476

2.2.3. Steady State analysis of the cascaded buck boost converter

The equivalent circuit when the position is turned on is given in Fig. 2.8

Fig. 2.8. Equivalent Circuit when the switch is ON

The voltage across the inductor when the switch is turned on is given by Eq. (2.13).

)(* tVdtdiLV i

ll == (2.13)

TDL

tVI il **

)(= (2.14)

The equivalent circuit when the switches are in the off position is given in Fig. 2.9


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Fig. 2.9. Equivalent Circuit when the switches are OFF

The voltage across the inductor when the switch is open is given by Eq. (2.15).

0* Vdt

diLV ll == (2.15)

TDL

VIl *)1(*

0 = (2.16)

Thus, the conversion ratio of the converter is given by

D

D

V

V

i =

1

0 (2.17)

2.3. Basic Operation of the SEPIC Circuit

The Single-ended Primary Inductor Converter (SEPIC) topology (Fig. 2.10) offers

the flexibility of the output voltage being higher or lower than the input voltage, thus

making itself as one of the candidates for consideration. Because of the coupling between

the inductors in a SEPIC topology, it has an additional advantage of input current ripple


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reduction Compared to the Fly-back converter, the input current in SEPIC converter is

continuous and thus the SEPIC rectifier needs a smaller volume of input filter SEPIC

features adjustable output voltage and no inrush current problems [4,27,32,33].

Fig. 2.10 SEPIC Converter

2.3.1. Steady State Analysis of the SEPIC Converter

We assume that the values of current and voltage ripple are small with respect to

the DC components [32]. At equilibrium there is no DC voltage across the two

inductances L1 and L2 (neglecting the voltage drop across their parasitic resistances).

Therefore, Cp sees a DC potential of Vin at one side, through L1, and ground on

the other side, through L2. The DC voltage across Cp is given in equation Eq. (2.18).

( ) inmeanCP VV = (2.18)

The period of one switching cycle is represented as T. The duty cycle of the switch is

represented by D and the (1-D) is the time during which the switch is turned off. The


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mean voltage across L1 equals to zero during steady-state conditions and so the voltage

seen by L1 during DT (Ton) is exactly compensated by the voltage seen during (1- D) T

(Toff). This given by the Eq. (2.19).

( ) ( ) ( )dincpdin VVTDVVVVTDDTV +=++= 00 11 (2.19)

where dV is the forward voltage drop of D1 for a direct current of (IL1 + IL2), and

cpV is equal to inV and is given by Eq. (2.20).

( )( ) iin

d AD

D

V

VV=

=

+

1

0 (2.20)

Where Ai is called the amplification factor, where "i" represents the ideal case for

which parasitic resistances are null. Neglecting dV with respect to 0V (as a first

approximation), we see that the ratio of 0V to inV can be greater than or less than 1,

depending on the value of D.

For a SEPIC converter, the peak to peak current ripple in inductors is given in Eq.

(2.21) and Eq. (2.22) [3,21]

( )( ) ( )

1

1

1

*

L

tttvti on= (2.21)

( ) ( ) ( )2

12 *

Ltttvti on= (2.22)

When the transistor is conducting, the peak current going through the transistor is the

sum of the two inductor currents and is shown in the Eq. (2.23).


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( ) ( )tVttLL

i Monpeaktrans *sin**11

21

_

+= (2.23)

The loss analysis of both these topologies is discussed in Chapter 3. Based on the

results of the loss analysis, the topology which is best suited for this application is

selected.

ch2- selection of a topology to meet the design requirements

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