8 8051 Microcontroller

The 8086-based Digital Weighing Machine (DWM) of Chpater-7 was an academic interest in the sense that the design contained all the theories of microprocessor that we studied from Chapter-1 to Chapter-6. The commercial version of the DWM must be designed based on microcontroller (MCU) because such design provides almost a single chip copy protected solution for the product. The MCU has built-in RAM, Code Memory, Data Memory, MPU, Register Bank and partial power of all the commonly used peripheral controllers. Moreover, an MCU contains a security bit, which when enabled, prevents others from accessing the internal program codes. 8.1 (a) Definition of a Microcontroller What is a Microcontroller? It is a Single Chip IC housed in a 40-pin package (Fig-8.1) and is commonly used to build copy-protected products like:

i Digital Taximeter ii Digital Weighing Machine and iii. Prepaid Energy Meter iv. Fuzzy Logic Based Washing Machine

8.1 (b) Built-in Hardware Resources of a Microcontroller A typical MCU of type 89S8252 contains the following hardware resources to support the design of single chip products. The materials of this section could be read in consultation with Fig-8.4. i. Byte Processor to handle 8-bit data with the help of 8-bit accumulator (A-register) ii. Boolean Processor to handle 1-bit data with the help of 1-bit accumulator (C – bit). iii. Special Function Registers (SFRs) to support Data Processing. iv. Register Bank to support Data Processing v. EEPROM-based Code Memory (Flash memory) to hold Program Instructions vi. EEPROM-based Data Memory (Data EEPROM) to hold critical data during Power

Failure. vii. Byte and Bit Addressable RAM space to hold variables viii. Security Bit to prevent access to Inter nal Program Codes and Data. ix. PIO Ports with individually programmable port pins x. Serial Port (SIO Port) to exchange asynchronous data with other controllers xi. Counter Port to count external events xii. Internal Timers for generating various Timing Functions. xiii. Logic to handle External Hardware Interrupts (HWI). xiv. Serial Peripheral Interface Port (SPI Port) to support the exchange of high-speed

synchronous serial data among compatible controllers xv. In System Programming Port (ISP Port) to store program codes and data within the

internal code and data memory without the need of costly ROM programmer. xvi. Bus Interface Unit (BIU) to access external Program and Data Memory.

452

8.1 (c) The Atmel Family of Microcontrollers The Atmel Company of the USA has launched a series of microcontroller chips, which offer very cost effective solutions to many industrial control applications and consumer products. These chips have borrowed the ‘Instruction Set’ and the CPU from the 8051 microcontroller of the Intel Company. The Atmel MCUs are also fully compatible with the Intel 8-Bit peripheral controllers. The following table gives a summary of the commonly used MCUs of the Atmel Company: The 8051 is the generic name and the 89XXXXX are the specific versions of the 8051. Among all these MCUs, the 89S51 is widely used for common purposes. The 89S8252 chips are used for especial purposes like building a Prepaid Energy Meter. All 40-pins devices are pin-to-pin compatible.

Type No

Pins Flash Data EEPROM

RAM PIO Ports

SIO Port

Timer/ Counter

External Interrupt

ISP Port

SPI Port

89C51 40 4K - 128 4x8 Yes 2 2 - - 89S51 40 4K - 128 4x8 Yes 2 2 Yes - 89C52 40 8K - 128 4x8 Yes 2 2 - - 89S52 40 8K - 128 4x8 Yes 2 2 Yes - 89S8252 40 8K 2K 256 4x8 Yes 3 2 Yes Yes 89C2051 20 2K - 128 2x8 Yes 2 2 - -

8.2 (a) Physical Pin Diagram of 89S8252/89S51 Microcontrollers Figure-8.1: Physical Pin Diagram of 89S8252 Figure-8.2: Physical Pin Diagram of 89S51

In Fig-8.1 (a) and 8.1 (b), we find that some of the pins of the MCUs have alternate function and these are shown within the parentheses. For example, Pin-12 could be configured to work either as an IO-pin or to receive an external interrupt request. The desired functions of the pins are determined during the initialization phase of the system design.

67

10

12

141516

18

2122

25

4012345

89

11

13

17

1920

2324

2627282930313233343536373839

P10(CT2)P11(CT2 EX)P12P13P14(SS/)

P15(MOSI)P16(MISO)P17(SCK)RSTP30(RxD)P31(TxD)P32(INT0/)P33(IN1/)P34(CT0)P35(CT1)P36(WR/)P37(RD/)XTAL2XTAL1GND P20(A08)

P21(A09)P22(A10)P23(A11)

P24(A12)P25(A13)P26(A14)P27(A15)

PSEN/ALE(PG/)EA/( Vpp)P07(AD7)P06(AD6)P05(AD5)P04(AD4)

P01(AD1)P00(AD0)

Vcc

89S82521004x

P03(AD3)P02(AD2)

67

10

12

141516

18

2122

25

4012345

89

11

13

17

1920

2324

2627282930313233343536373839

P10P11P12P13P14

P15(MOSI)P16(MISO)P17(SCK)RSTP30(RxD)P31(TxD)P32(INT0/)P33(IN1/)P34(CT0)P35(CT1)P36(WR/)P37(RD/)XTAL2XTAL1GND P20(A08)

P21(A09)P22(A10)P23(A11)

P24(A12)P25(A13)P26(A14)P27(A15)

PSEN/ALE(PG/)EA/( Vpp)P07(AD7)P06(AD6)P05(AD5)P04(AD4)

P01(AD1)P00(AD0)

Vcc

89S511004xy

P03(AD3)P02(AD2)

Chapter - 8

453

8.2 (b) Pin Functions of the 89S51 Microcontroller In the following table, we have briefly described the pin-functions of the commonly used MCU, which is the 89S51 chip. These functions are also valid for all the MCUs under 8051 except the 89C2051 chip. The readers are advised to study data sheets of the relevant MCU.

Pin Signals Signal Names Direction Function P10 – P17 MOSI MISO SCK

Port Pins Master Out Slave In Master In Slave Out Serial Clock

Input and Output Output Input Output

To exchange data with external devices. Each pin can be independently operated either as input or output. These three signals together forms the ‘In System Programming (ISP) Port’, which allows storing code inside the internal code memory of MCU without a ROM Programmer.

RST Reset Input To begin the startup of the MCU from the cold state. P30 – P37 RxD, TxD INT0/, INT1/ CT0/, CT1/ WR/ RD/

Port Pins Receive Data Transmit Data Interrupts Counter/Timer Data Write Signal Data Read Signal

Input and Output Input Output Input Input Output Output

To exchange data with external devices. Each pin can be independently operated either as input or output. To exchange asynchronous serial data in with external devices. To receive interrupt request signals from the external hardware devices. To receive external pulse events for counting purposes. To asserts write and read commands to the external data memory and ports

XTAL2, XTAL1

Crystal In-1 Crystal In-2

Input Input

To connect a frequency determining crystal for the internal oscillator of the MCU.

GND Control Input To sink current of the MCU. P20 – P27 A8 – A15

Data Ports Address Lines

Input and Output Output

To exchange data with external devices. Each pin can be independently operated either as input or output. To assert upper 8-bit address lines while accessing external code memory, data memory and ports.

PSEN/

Program Sense Output Equivalent to read signal while reading program codes form external code memory.

ALE PG/

Address Latch Enable Programming Pulse

Output Input

Asserts High Going Pulse to demultiplex A0 – A7 signal from the composite AD0 – AD7 signal. Also continuously emits 1/6th of crystal frequency while not accessing external memory provided the 0-bit of the AUXR-register is at LH. Low Going Pulse to strobe data inside the code memory.

EA/ Vpp

External Access Voltage Programming Pulse

Input Input

When tied to LL, MCU will ignore internal code memory. When tied to LH, MCU will access code memory from address greater than 1FFFH. If security bit is locked then EA/ has no role. The MCU will access only the internal memory. Application of +12V during writing code into internal code memory using Parallel Mode Commercial ROM Programmer.

P00 – P07 AD0 – AD7

Port Pins Multiples Address And Data Bus

Input and Output Output

To exchange data with external devices. Each pin can be independently operated either as input or output. At the beginning of a bus cycle, A0-A7 signals are emitted to the storage device. And then the lines configures into Data Lines to receive 8-bit data from the storage devices.

Vcc DC Supply Input Supplies Dc Power to the MCU.

Pin Functions of 89S51 Microcontroller

454

8.3 (a) Summary Block Diagram for the Internal Resources of the 89S8252 MCU

Figure-8.3: Summary Hardware Black Diagram for 89S8252 MCU

The block diagram representation of a microcontroller chip exhibits at a glance the available hardware resources present within it. Thus, a designer just looks at the block diagram and quickly decides whether the current MCU can satisfy her design need or not. In Fig-8.2, we have depicted the block diagram for the 89S8252 microcontroller. What’s about the hardware resources of the 89S51 MCU? The answer could be easily found by comparing the physical pin diagram of the 89S51 [Fig-8.1(b)] with the diagram of Fig-8.2. The comparison reveals that the 89S51 MCU contains the following hardware resources:

i. P0, P1, P2 and P3 ii. BIU iii. Serial IO iv. Interrupt Resolver v. 2 Timer/Counters vi. ISP Port The study of data sheets for the 89S51 MCU indicates that the chip contains: vii. 4K Byte Code Memory viii. 128 Byte RAM ix. Security Bit x. Byte Processor xi. Bit Processor xii. Register Bank

1004

8K Flash

256 BytesRAM

Counting/Timing

CT1/CT0/

INT0/INT1/ Interrupt

Resolver

8-Bit CPU

TxDRxD

Serial IO

PIO

P07-P00

P17-P10

P27-P20

P37-P30

P0

P1

P2

P3

Security Bit

8-bit Acc

1-Bit CPU1-bit Acc

ISP Interface

Register Bank

CT2/

2K Data MemSecurity Bit

SPI Interface

BIUA,D, C

Chapter - 8

455

8.3 (b) Expanded Block Diagram for the Internal Resources of 89S8252 MCU

Figure-8.4: Detailed Hardware Black Diagram for 89S8252 MCU

divide by12

11.0

592

MH

z 8-BIt CPU

8-BIT Accumulator (A)

M1 M2

M5

1-BIt CPU

1-BIT Accumulator (C)

M3

M6

In Sys.Prog. Interface

SPIInterface

For 89S8252

M4

M7

SerialCommunication

Timer/Counter

M8

M12Rx, Tx

TC0-2

CodeEEPROM(FLASH)

0000 – 0FFF (89s51)0000 – 1FFF (S8252)

DataEEPROM

0000 - 07FF (S8252) Lower Block ofRAM (00-7F)

SFR (80-FF) Upp RAM (80-FF)

for 89X52 only

Exter. Interrupt

M13INT0-1

M9 M10 M11

M13

M16

M14 M15

M17

Port-0

Port-1

Control Matrix(Sequence Generator)

P00-P07

P10-P17

Addree BusInterface A00-A15

Data Buffer D0-D7

M18

M20

Port-2 Write ControlLogic

Port-3

P20-P27

P30-P37

M19

WR/

M21

Read ControlLogic

RD/PSEN/

SS/, SCKMOSI,MISO

SCKDataOut,DataIn

783a : GM : 1-11-05

Security Bit Security Bit

Expanded Block Diagram for the Internal Resources of 89S8252 MCU

456

8.3 (c) Function-Level View for the Internal Resources of 89S8252 MCU

Figure-8.5: Functional Level View for Internal Resources of 89S8252 MCU

P37

RD/

P36

WR/

P35

C1/

P34

C0/

P33

INT1/

P32

INT0/

P31

TxD

P30

RxD

10

11

12

13

14

15

16

17

Port-3Latches

ProcessingModule-1

D0D1D2D3D4D5D6D7

A0A1A2A3A4A5A6A7

P00P01P02P03P04P05P06P07

Port-0Latches

(8)

A8A9A10A11A12A13A14A15

P20P21P22P23P24P25P26P27

Port-2Latches

(8)

Port-1Latches

P10P11

P17

P12P13P14P15P17

(8)

ProcessingModule-2

0000

1FFF

80P0*

SP

DP0L

DP0HDP1L

81

83

TCON

PCON*

TMOD

TL0

TL1

TH0

TH1

AUXR

P1*

-

SCON*

SBUF

-

P2*

IE*

-

P3*

-IP*

PSW*

-

ACC*

B*

-

82

87

88

89

8A

8B

8C

8D

90

98

91

A8

A0

B0

B8

D0

E0

F0

FF

RegisterSet

InternalRAM

80

7F

2F

20

BitSpace

BK3

BK2

BK1

BK000

08

10

181F

17

0F

07

Internal4K Code EEPROM

PC = 16-Bit A15-A00

MOVX @R1 (R0), A: R1 or R0 = 8-Bit

MOVX @DPTR, A: DPTR = 16-Bit A15-A00

A7-A0A15-A08 by P2

cngmet\ch8\8-6: 784

29

30

PSEN/

ALE

Registers marked by * are Bit Addressable

ISP and SPIInterface

xx52

C8

CDT2Timer-2

DP1H8485

8E

AUXR1 A2WDTRST A6

Internal2K Data

EEPROM

0000

07FF

Security Bit

Security Bit

Chapter - 8

457

The information contained in the diagram of Fig-8.5 may be described in the following ways: 1. Pin-17 can be programmed to carry out one of the following functions: i. Simple bi-directional IO line ii. To emit ‘Data Read Command’ signal to external ‘data memory’ and ‘memory-mapped port’

during the execution of the instruction: MOV X A, @DPTR ; MOVX A, @R1

2. Pin-16 can be programmed to carry out one of the following functions: i. Simple bi-directional IO line ii. To emit ‘Data Write Command’ signal to external ‘data memory’ and ‘memory-mapped port’

during the execution of the instruction: MOV X @DPTR, A ; MOVX @R0, A

3. Pin-11 can be programmed to carry out one of the following functions: i. Simple bi-directional IO line ii. To emit ‘a frame of asynchronous’ serial data during the execution of the instruction: MOV

SBUF, A

4. Pin-12 can be programmed to carry out one of the following functions: i. Simple bi-directional IO line ii. To receive and sense the falling edge of an external signal and then interrupt the MCU.

5. Pin-14 can be programmed to carry out one of the following functions: i. Simple bi-directional IO line ii. To receive and sense the occurrence of the falling edge of an external signal and then count the

number of such occurrences in a unit time.

6. Port Pins P10-P17 can be programmed to carryout one of the following functions: i. Simple bi-directional IO line ii. P14 – P17 lines to work as SPI Port iii. P15 - P17 lines to work as ISP Port

7. Port Pins P00-P07 can be programmed to carryout one of the following functions: i. Simple bi-directional IO line

ii. As low order address lines (A0 – A7) while accessing the external code memory, data memory and memory-mapped port. The P00 – P07 lines automatically turns into A0-A7 address lines while the MCU executes the instructions MOVX A, @DPTR to access external storage devices.

iii. As data lines (D0 – D7) while accessing the external code memory, data memory and memory-mapped port. The P00 – P07 lines automatically turns into D0 – D7 address lines while the MCU executes the instructions MOVX A, @DPTR to access external storage devices.

8. Port Pins P20-P27 can be programmed to carryout one of the following functions: i. Simple bi-directional IO line

ii. As high order address lines (A8 – A15) while accessing the external code memory, data memory and memory-mapped port. The P20 – P27 lines automatically turns into A8-A15 address lines while the MCU executes the instructions MOVX @DPTR, A to access external storage devices. While, the MCU is not executing the external memory reference instructions, the P2 keeps emitting the port data previously written into it.

9. The PC (Program Counter Register) emits the 16-bit address of the external code memory when the MCU fetches program instructions.

10. The DPTR (16-bit Data Pointer Register composed of DPH, DPL) emits 16-bit address of the external data memory and memory-mapped port during data read/write operation with these them.

11. The R0 or R1 register emits lower (A0-A7) 8-bit address of an external data memory location during the execution of the instruction: MOVX A, @R0. The upper 8-bit address (A8-A15) of the memory location is assumed to be equal to the content of Port-2.

Functional-Level View for the Internal Resources of 89S8252 MCU

458

8.3 (d) SFR Register and RAM Space Map of an 8051-based Design

Figure-8.6: Internal RAM and Register Map for a typical 89S8252-based Design

00 Bank-007

0F08

10

20

17

FlagTable

3F40

761

Bank-1

Bank-2181F Bank-3

27

2F

000107081018

1F171F

2027282F3037

787F30 DP0

DPF

CC Code for Digit of DP0CC Code for Digit of DP1CC Code for Digit of DP2CC Code for Digit of DP3

CC Code for Digit of DPF

4F DPF

DP0Unpacked Hex of format: 0X

Unpacked Hex of format: 0X50

57

Packed Hex of format: XX

DPEDPF

DP0DP1

Packed Hex of format: XX586B6C6D6E6F70

7F

CRP (Curs Pos)/ PRP (Print Pos)

SP

NPD (Digits Printd left of CursCTP (Cursor Type)

Key Sccan Code

384048505860

7068

3F474F575F676F77

0203040506

797A7B7C7D7E

Internal RAM Internal SFRs of the MCU

80

FF

818283

P0

TCON

SPDP0LDP1H

DP1L, DP1HPCON

84, 85

TH0

NOT ACCESSIBLE

8D

TMOD

TH1

89

8788

TL1TL08A

8B8C

8F

P190

NOT ACCESSIBLE91 - 97

SCON98SBUF99

F1

NOT ACCESSIBLE

F0

E1E0

B

NOT ACCESSIBLE

ACC

EF

NOT ACCESSIBLE

D1

DF

PSWD0

NOT ACCESSIBLE9A

9FA0

P3

NOT ACCESSIBLEA1

A7A8 IE

WDTRSTA9

AFB0

P2

NOT ACCESSIBLEB1

B7B8 IP

NOT ACCESSIBLE

B9

CF

8087

8887

9097

989F

A8

A0

B7

A7

AF

- -

B0

B8BF

F0F7

E0

D0

E7

D7

R0R7R0R7R0R7R0R7

Scratch pad Memory Space

T2CONT2MODRCAP2LRCAP2HTL2TH2

C8C9CACBCCCD

8952

onl

y8E AUXR

AUXR1AE

FF

80Upper RAM

Accessed indirectly by R0 or R1

T1

T2

T3

T4

T5

T6

T7

T8

T9

Chapter - 8

459

Special Function Register (SFR):

Register Name Address Reset Content Bit Addressable P0 (Port – 0) 80H 1111 1111 Yes SP (Stack Pointer) 81H 0000 0111 - DPOL (Lower Byte of Data Pointer 0) 82H 0000 0000 - DP0H (Higher Byte of Data pointer 0) 83H 0000 0000 - DP1L (Lower Byte of Data Pointer 1) 84H 0000 0000 - DP1H (Higher Byte of Data Pointer 1) 85H 0000 0000 - SPDR (SPI Port Data Register) 86H XXXX XXXX ? PCON (Power Control) 87H 0XXX0000 - TCON (Timer Control) 88H 0000 0000 Yes TMOD (Timer Mode) 89H 0000 0000 - TL0 (Timer 0 Lower Byte) 8AH 0000 0000 - TL1 (Timer 1 Lower Byte) 8BH 0000 0000 - TH0 (Timer 0 Higher Byte) 8CH 0000 0000 - TH1 (Timer 1 Higher Byte) 8DH 0000 0000 - P1 (Port-1) 90H 1111 1111 Yes WMCON (Watchdog and memory Control) 96H 0000 0010 ? SCON (Serial Control) 98H 0000 0000 Yes SBUF (Serial Buffer) 99H XXXX XXXX - P2 (Port – 2) A0H 1111 1111 Yes IE (Interrupt Enable) A8H 0X00 0000 Yes SPSR (SPI Port Status Register) AAH 00XX XXXX ? P3 (Port – 3) B0H 1111 1111 Yes IP (Interrupt Priority) B8H XX00 0000 Yes T2CON (Timer 2 Control) C8H 0000 0000 Yes T2MOD (Timer 2 Mode Control) C9H XXXX XX00 ? RECAP2L (Lower Byte of RCAP2) CAH 0000 0000 - RECAP2H (Higher Byte of RECAP2) CBH 0000 0000 - TL2 (Timer 2 Lower Byte) CCH 0000 0000 ? TH2 (Timer 2 Higher Byte) CDH 0000 0000 ? PSW (Processor Status Word) D0H 0000 0000 Yes SPCR (SPI Port Control register) D5H 0000 01XX ? ACC (Accumulator A) E0H 00000 0000 Yes B (Register B) F0H 0000 0000 Yes

Register Bank (Table T1) : There are four RAM banks (Bank0 – Bank3) at the lower part of the RAM. At one time, the MCU can work with only one bank. The working bank is determined with the help of RS0, RS1 bit of the PSW register. Each bank contains eight RAM locations, which are designated as R0 – R7 (Regiter-0 to Register-7). Only the registers R0 and R1 could be employed to work as a pointer register. Bit Addressable RAM Locations (Table T2) : The 8051 has 16 (20H – 2FH) RAM locations, which are bit addressable. Bit addressable means that there are addresses for each bit of the RAM location. Thus, a single bit could be made 0 or 1 without affecting the values of other bits of the RAM location. The addresses of the bits are shown in the diagram as 00H, 01H, .., 7FH. The bit addressable locations find their usage in creating flags or ‘bit map table’.

SFR Register and RAM Space Map of an 8051-based Design

460

There is a RAM location with address 00H and there is a bit location with address 00H also. These two storage locations are distinguished by instructions. For example:

MOV 00H, #75H : 75 00 75 ; 75H (8-bit) is written into RAM location with address 00H. MOV 00H, C : 92 00 ; content of Carry-bit (0 or 1) is written at 1st bit of RAM location 20H.

Stack Space: Stack (Table T8): This is an internal RAM space into which the MCU saves return address during interrupt and subroutine calls. The author has chosen the RAM space 70H – 7FH for stack space. The content of the sp-register points to the address of a stack location, which is known as StackTop. According to 8051 architectures, the StackTop is always a filled up location. The stack grows towards increasing memory locations. The lower byte of the return address is saved first on the stack and then the upper byte of the return address. The mechanism of the storage of the return address onto the stack is explained with the help of the Fig-8.7.

Figure-8.7: Stack Operation during Subroutine Call

Upper RAM Space (80H – FFH) (Table T9): This RAM space is not available for the microcontrollers 89C51, 89S51 and 89C2051. This is available in the xx52 series of the Atmel microcontrollers. In Fig-8.6, we find that the address space of the SFRs (Special Function Registers) is the same as that of the upper RAM space (URS). The URS is accessed indirectly by putting the 8-bit address of the target location into the R0 or R1 register. The addressing method determines whether it is the URS or the SFR, which is being accessed. The following instructions would clarify the access methods into URS and the SFR.

MOV R0, #80H MOV A, @R0 ; Indirect Addressing Mode

; 8-bit content of RAM location 80H of the URS is copied into A-register

MOV A, 80H ; Direct Addressing Mode ; 8-bit content of the P0-register is copied into A-register.

RAM Space (30H – 3FH)(Table T2): The author recommends that the indicated space should be reserved to hold CA-codes for the possible 16-nos display devices to be driven by the MCU in a typical system like a Digital Weighing Machine (Fig-8.34). The display devices would be continuously refreshed with the contents of this RAM space.

RAM Space (50H – 57H) (Table T4): This space may be kept aside to hold the 8-byte (packed Hex or Packed BCD) data to be outputted on the 7-Segment display device (7SD) attached with the MCU. A BCD2CC (BCD code to CC code Converter) could be called upon to convert the 8-byte BCD data into 16-byte CC-code.

RAM Space (40H – 4FH) (Table T3): This 16-byte RAM location could be reserved to contain the unpacked-BCD (Hex) data for the 8-byte BCD data of T4. The RAM space could also be used to create lookup table for converting BCD data into CC-coded data.

RAM Space (58H – 6DH) (Table T6): A programmer may use this space as a rough (scratch pad memory) area or as temporary storage locations during computations.

70

7F

StackTop xx

Stack before Subroutine Call

70

7F

StackTop

xx

Stack after Subroutine CallMainline Program:

L1: C100 - NOPL2: C101 – LCALL C300HL3: C104 -

Subroutine:SL1: C300 – NOPSL2: C301 - RET

Return Address

04C1

761

7172

Chapter - 8

461

8.4 (a) Port-Mode Operation of 8051 Microcontroller

Figure-8.8: Port Mode Operational Diagram for the 8051 Microcontroller

P10

P1

P17

8PIO

RST

0V

R15k

+5C1100uF+

K1

P30

P3

P37

PIO 8

VccGND

+50V

P00

P0

P07

P20

P2

P27

8

8

PIO

PIO

PSEN/ NCALEEA/ +5V

XT1 XT2

Y1 = 12.00 MHz

8051Port

+5

8x5kSecurity Bit

Code Memory(8k Flash)

0000H – 1FFFH

256 Byte RAM00H – 7FH - FFH

Data Memory(4k EEPROM)

0000H – 07FFFH

Register Set

1/6th of Y1

TTL of Y1

GND

22pF 22pF

699xy

P0 80HP00P01P02P03P04P05P06P07

80H81H82H83H84H85H

87H86H

P1 90HP10P11P12P13P14P15P16P17

90H91H92H93H94H95H

97H96H

P20P21P22P23P24P25P26P27

A0HA1HA2H

A5HA6HA7H

P2

A4HA3H

A0H

89S8252 MCU

0000

07FF

DataEEPROM

0000

0FFF

Code Flash

00

FF

RAM

7F80

FF

RegisterSet

80

P30P31P32P33P34P35P36P37

B0HB1HB2H

B5HB6HB7H

P3

B4HB3H

B0H

Port-Mode Operation of 8051 Microcontroller

462

In Port-Mode operation., the 8051 offer the following hardware services: A: The IO lines of P0, P1, P2 and P3 can be individually configured to work as either input or

output. However, the eight port-pins of P0 must be terminated to +5V by eight 5k resistors. This is due to the reason that the internal port-driving MOSFETS of Port-0 are open drain devices.

B: By default (after power up reset), the port pins are automatically configured as output. However, to operate the port-pins as inputs, a LH (Logic High) should be written into the corresponding port-pin by executing the instruction: SETB PX.X. The execution of the instruction MOV P1, #0FFH will configure all the P1-pins as input. However, after writing LH into a port-pin, it can still be used as output pin.

C: A TTL level frequency equal to the crystal frequency is available at XT1-pin of the MCU. D: The ALE-pin emits clock pulses equal to the 1/6th of the crystal frequency. This clock

pulses could be used as a general-purpose clock. Internal Structures of P0, P1, P2 and P3 of 8051 Microcontroller:

Figure-8.9: Internal Structure of P0, P1, P2, and P3 for the 8051 Microcontroller Exception: In port mode operation, all the ports of the 8051 have identical internal hardware structure as is shown in Fig-8.9 except that the Port-0 (P0) does not contain the internal transistor T1. This means that the P0 is an open drain circuit and external pull up resistors must be used before it is operated as an IO port. Open drain circuits can directly drive relays and lamps. Writing LH or LL on Port Pins: The circuit of Fig-8.9 indicates that the desired logic value (say LH) is written onto the Q-bit of the internal FF1. Q/-bit assumes LL and the T2 is OFF. T1 works as a pull up resistor (except P0) and the P1.X-pin assumes LH state. The following instructions perform data write operations on the port pins through internal FF1.

i. MOV PX, #XX ; LH or LL are written to all the 8 port-pins. ii. SETB PX.X ; LH or LL is written onto only one port-pin. iii. MOV PX.X, C ; the value of C-bit (LH or LL) is written to port-pin.

Q

Q/

A

T1

FF1

T2

B

C

D

D

CK

G1

Vcc

0V

Port Latch Read Command

Latch Output Data

Port Pin Read Command

Port Pin Data

Port Latch WriteCommand

Internal Data Bus P1.0

340a

G4

0V

Q1

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463

Reading Data Bit from an Input Port Pin: Before we operate a port as an input, we must write LH at Q-bit of the internal FF1 to ensure that T2 is OFF and T1 is ON. Now, external data values either LH or LL will be inputted at the PX.X-pin. The data bit will enter to the MCU via gate G1. The following instructions are used to read data from the input port-pins.

i. MOV A, PX ; to read data bits from all the 8 port-pins of P0. ii. MOV C, PX.X ; to read data bit from only one port-pin, PX.X

Reading Data Bit from an Output Port Pin: Assume that a port is configured to work as output and we will always be interested to write data on it rather that reading data from it. But there may be an occasion to read the value of the port-pin and then taking a decision depending on the value of the port-pin. As long as we are sure that the port-pin has retained the previously written value then the instructions: MOV A, PX.X; MOV C, PX.X will correctly read the bit values of the port pins. But, the difficulties arise when the output pin drives the base of a transistor Q1 as is depicted in Fig-8.9.

In Fig-8.9, let us assume that the transistor Q1 is not connected with the PX.X. Now, the value (LH or LL) what is written on Q-bit is immediately transferred on the port-pin PX.X. Under this condition, reading either the Q-bit or the PX.X (port-pin) will always provide the correct value.

Now, let us assume that the transistor Q1 is connected at PX.X-pin and write LH at Q-bit to turn ON the transistor. The result is that the Q1 in ON but we have LH at the Q-bit but LL (0.7V= BE voltage of Q1) at the PX.X-pin. The PX.X-pin has failed to retain the previously written LH value due to its load Q1. However, the actual value is present at the Q-bit of the FF1. Therefore, to know the actual value of PX.X-pin, we have to perform a read operation on the Q-bit of the FF1 (known as read latch). The following instructions perform ‘read-modify-write’ operations on the latch. These instructions read the Q-bit of the internal FF1, possibly change it and then write back on the Q-bit of the latch. When the destination is a port or a port-bit, these instructions read the latch rather than the port-pin. This is equivalent of changing the bit values of the output port-pins.

Sno. Instruction Operations i. ANL P1, A 8 Q-bits of FF1 is read and then logically ANDed with the contents of A-

register. The result is then written ino the 8 Q-bits of the FF1. The values are ultimately transmitted to physical pins.

ii. ORL P1, A Same as above but this time it is logically ORed. iii. XRL PP3, A Same as above but this time it is logically exclusive ORed. iv. JBC P2.1, L1 The Q2-bit of internal latch is read and then breaching is made at label

depending on the bit value. v. CPL P3.0 The Q3-bit of internal latch is read. It is then inverted and then is written

into the Q3-bit. The bit value ultimately goes to P3.0-pin. vi. INC P2 The Q-bits of latch is read and then added with 01H. The result is written

back to latch. The value ultimately goes to the physical port-pins. vi. DEC P2 Same as above but this time it is a subtraction of 01H. vii. DJNZ P3, L2 The latch is read and the value is decremented by 01H. The result is

written back to latch so that it can propagate to physical port-pins. Branching is made at label L2 depending on the result.

viii. MOV PX.X, C The value of Carry bit is written into latch from where it goes to PX.X-pin. ix. CLR PX.X LL is written into latch from where it goes to physical PX.X-pin. x. SET B PX.X LH is written into latch from where it goes to physical port-pin PX.X.

Figure-8.10: Summary Table of Read-Modify-Write Instructions of 8051 Microcontroller

Port-Mode Operation of 8051 Microcontroller

464

8.4 (b) Mixed-Port Operation of 8051

Figure-8.11: Mixed-Port Operational Diagram for the 89S8252 MCU

In Mixed-Port operation, the 8051 offer the following hardware services: A: Parallel IO Operation i. P00 – P07 ii. P11 – P13 ii. P20 - P27 iii. P36 – P37 B: Serial IO Operation i. P30-pin is configured to work as RxD-pin (Receive Serial Data) by software initialization ii. P31-pin is configured to work as TxD-pin (Transmit Serial Data) by software initialization C: Counter Functions

i. P34-pin is configured to work as Counter-0 (to receive external pulses) by software initialization.

ii. P35-pin is configured to work as Counter-1 by software initialization. iii. P10-pin is configured to work as Counter-2 by software initialization.

D: Interrupt Request Pin i. P32-pin is configured to work as Interrupt Request Line-0 by software initialization. ii. P33-pin is configured to work as Interrupt Request Line-1 by software initialization. E: Synchronous Serial Peripheral Interface

i. P14-pin is configured to work as external slave select (to select another 89S8252 MCU) pin by software initialization.

ii. P15-pin is configured to work as MOSI-pin (Master Out slave In = Sending Serial Data to another MCU).

iii. P16-pin is configured to work as MISO-pin (Master In Slave Out = Receive Serial Data from another MCU).

iv. P17-pin is configured to work as SCK-pin (Serial Clock) for clocking out/ clocking in data.

C2/C2

8PIO

+5C1

100uF K1

PIO 2

VccGND

+50V

P00P0

P07

P20

P2

P27

8

8

PIO

PIO

PSEN/ NCALEEA/ +5V

XT1 XT2

Y1 = 11.0592 MHz

8051MixedPort

+5

8x5kSecurity Bit

Code Memory(8k Flash)

0000H – 1FFFH

256 Byte RAM00H – 7FH - FFH

Data Memory(4k EEPROM)

0000H – 07FFFH

Register Set

1/6th of Y1

TTL of Y1

P11P12P13

SS/MOSIMISOSCK

0VR15k

+

4SPIP14P15P16P17

RxDTxD

P30P31

2SIO

2IRQ INT0/INT1/

P32P33

C0/C1/

P34P35

2Counter

P36P37

RST

P10P1

P3

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465

8.4 (c) Bus-Mode Operation of 8051 Microcontroller ``

Figure-8.12: Bus Mode Operational Diagram for the 8051 MCU In Bus-Mode operation, the following hardware services are offered by the 8051 MCU: A: Limited PIO, Serial IO, Counter, Interrupts and SPI services. B: The Internal and External Code Memory are available under the following constraints: i. When EA-pin is tied to 0V:

The MCU does not see the internal code memory. The MCU can excess 64Kbyte of external code memory.

ii. When EA-in is tied to +5V: The MCU will find internal code memory for the addresses 0000H – 1FFFH. The MCU will access external code memory for the address 2000H – FFFFH.

C: The MCU can excess external 64Kbyte data memory regardless of the logic-level of the EA-pin.

D: In Bus-Mode operation, the MCU operates as follows: i. P00-P07 pins automatically configured as multiplexed AD0 – AD7 pins. ii. P20 – P27 pins automatically configured as A8 – A15 pins. iii. P36-pin automatically operates as WR/-pin for the data memory. iv. P37-pin automatically operates as RD/-pin for data memory. v. PSEN/-pin automatically operates as ‘Read Signal’ for the code memory. vi. ALE-pin could be used to demultiplex the A0-A7 lines from the composite AD0-AD7 lines.

E: In Bus-Mode operation, the Security Feature of the MCU is not available.

C2/C2

8PIO

+5C1

100uF K1

VccGND

+50V

A15P2

A8

AD7

P0AD0

8

8

AD7-AD0

A15-A8

PSEN/

ALE

EA/0V

XT1 XT2

Y1 = 11.0592 MHz

8051BusMode: GM: 05-2008

Security Bit

Code Memory(8k Flash)

0000H – 1FFFH

256 Byte RAM00H – 7FH - FFH

Data Memory(4k EEPROM)

0000H – 07FFFH

Register Set

TTL of Y1

P11P12P13

SS/MOSIMISOSCK

0VR15k

+

4SPIP14P15P16P17

RxDTxD

P30P31

2SIO

2IRQ INT0/INT1/

P32P33

C0/C1/

P34P35

2Counter

RST

P10P1

P3

P00

P07

CK

D Q A7 – A0

D7-D0

A8

A15

8

A15-A8

OE/

A7 – A0

A15-A8

D7 – D08

RD/(P37)WR/(P36)

RD/WR/

ROM RAM

D7-D0

Mixed-Port Operation of 8051 Microcontroller

466

8.5 Instruction Set Summary of 8051 The 8051 instruction set is divided into four functional groups: i. Data Transfer ii. Boolean manipulation iii. Arithmetic

iv. Logic v. Control Transfer

A: Data Transfer Data Transfer Instructions

Instructions Description Number of Bytes

Oscillator Frequency

MOV A, Rn Register (R0 – R7) content into Accumulator 1 12 MOV A, direct Internal RAM location (00H – FFH) content into Accumulator

Register 2 12

MOV A, @Ri Content of Ram location pointed by R0 or R1 into Accumulator 1 12 MOV A, #data8 8-Bit immediate data into Accumulator 2 12 MOV Rn, A Content of A-register into Register (r0 – R7) 1 12 MOV Rn, direct Content of RAM location into Register (R0 – R70 2 24 MOV Rn, #data8 8-bit immediate data into register (R0 – R7) 2 12 MOV direct, A Content of A-register into internal Ram location 2 12 MOV direct, Rn Register (R0 – R7) content into internal RAM location 2 24 MOV direct, direct Content of one Ram location into another RAM location 3 24 MOV direct, @Ri Content of one RAM location pointed by R0 or R1 into another

RAM location 2 24

MOV direct, #data8 8-bit immediate data into a RAM location 3 24 MOV @Ri, A Content of A-register into a RAM location pointed by R0 or R1 1 12 MOV @Ri, direct Content of a RAM location into another RAM location pointed by

R0 or R1 2 24

MOV @Ri, #data8 8-bit immediate data into a RAM location pointed by R0 or r1 2 12 MOV DPTR, #data16 16-bit immediate data into Data Pointer Register 3 24 MOVC A, @A+DPTR Content of an external memory location pointed by the content of

A-register and the DPTR-register comes into A-register. 1 24

MOVC A, @A+PC Content of an external memory location pointed by the content of A-register and the PC-register comes into A-register.

1 24

MOVX A, @Ri Content of external memory RAM location whose A0-A7 bits are pointed by R0 or R1 comes into A-register. The A8-A15 bits are asserted by P2-port. Therefore, P2 must be initialized properly.

1 24

MOVX A, @DPTR Content of external Ram location whose 16-bit address is asserted by DPTR-register comes into A-register.

1 24

MOVX @DPTR, A Content of A-register is transferred to an external RAM location whose 16-bit address is asserted by DPTR-register.

1 24

PUSH direct Content of an internal RAM location is stored into stack memory 3 24 POP direct 8-bit content from the stacktop location is retrieved into a internal

RAM location. 3 24

XCH A, Rn Content of Register (R0 – r7) is exchanged with A-register. 1 12 XCH A, direct Content of RAM location is exchanged with A-register 2 12 XCH A, @Ri Content of RAM location pointed by R0 or R1 is exchanged with A 1 12 XCHD A, @Ri Exchange of lower order digit of a RAM location pointed by R0 or

R1 with the lower digit of A-register. 1 12

B: Boolean Manipulation CLR C Clear the carry-bit of PSW-register 1 12 CLR bit Clear the value of the bit flag designated by the bit address (00H –

7FH) 2 12

SETB C Put LH to the carry bit 1 12 SETB bit Put LH into the bit flag designated by the address 00H – 7FH 2 12 CPL C Complement the bit value of the carry bit 1 12

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467

CPL bit Complement the bit value of the bit flag having the bit address 00H – 7FH

2 12

ANL C, bit Logical AND operation between C-bit and the bit with an 8-bit address

2 24

ANL C, /bit Logical AND operation between C-bit and the complement of bit with an 8-bit address

2 24

ORL C, bit Logical OR operation between C-bit and the bit with an 8-bit address

2 24

ORL C, /bit Logical OR operation between C-bit and the complement of bit with an 8-bit address

2 24

MOV C, bit Move 1-bit data into C-bit from a bit location with an 8-bit address 2 12 MOV bit, C Move 1-bit data into a bit location with an 8-bit address from C-bit 2 12 JC L2 Jump to location L2 if Carry bit of PSW is found set. 2 24 JNC L2 Jump to label L2 if Carry bit of PSW is not found set. The label L2

is located either 128 byte backward or +127 byte forward relative to the first byte of the following instruction.

2 24

JB bit, L3 Jump to label L3 if the value of the direct bit (with an 8-bit address) is found set.

3 24

JNB bit, LX Jump to label LX if the value of the direct bit (with an 8-bit address) is found set.

3 24

JBC bit, LY Jump to label LY if the value of the direct bit (with an 8-bit address) is found set and clear the bit value..

3 24

C: Arithmetic Operations

ADD A, Rn Add with A-register, the content of Rn-register (n = 0 – 7) 1 12 ADD A, direct Add with A-register, the content of an internal RAM location

whose 8-bit address is directly given in the instruction 2 12

ADD A, @Ri Add with A-register, the content of an internal RAM location whose 8-bit address is being pointed by the R0 or R1 register.

1 12

ADD A, #data8 Add with A-register, an 8-bit data which has been directly given in the instruction.

2 12

ADDC A, Rn Add with A-register, the C-bit of the previous operation and the content of Rn (n = 0 – 7) register.

1 12

ADDC A, direct Add with A-register, the C-bit of the previous operation and the content of an internal RAM location whose 8-bit address is directly given in the instruction..

2 12

ADDC A, @Ri Add with A-register, the C-bit of the previous operation and the content of an internal RAM location whose 8-bit address is being pointed by R0 or R1 register.

1 12

ADDC A, #data8 Add with A-register, the C-bit of the previous operation and an 8-bit data directly given in the instruction.

2 12

SUBB A, Rn Subtract from A-register, the C-bit of the previous operation and the content of Rn (n = 0 – 7) register.

1 12

SUBB A, direct Subtract from A-register, the C-bit of the previous operation and the content of an internal RAM location whose 8-bit address is directly given in the instruction..

2 12

SUBB A, @Ri Subtract from A-register, the C-bit of the previous operation and the content of an internal RAM location whose 8-bit address is being pointed by R0 or R1 register.

1 12

SUBB A, #data8 Subtract from A-register, the C-bit of the previous operation and an 8-bit data directly given in the instruction.

2 12

INC A Add 01H with the content of A-register 1 12 INC Rn Add 01H with the content of Rn register (n = 0 – 7). 1 12 INC direct Add 01H with the content of an internal RAM location whose 8-bit

address is directly given in the instruction. 2 12

Instruction Set Summary of 8051 Microcontroller

468

INC @Ri Add 01H with the content of internal RAM location whose 8-bit address Is being pointed by R0 or R1 register.

1 12

DEC A Subtract 01H from the content of A-register 1 12 DEC Rn Subtract 01H from the content of the Rn (n = 0 – 7) register. 1 12 DEC direct Subtract 01H from an internal RAM location whose 8-bit address

is directly given in the instruction. 2 12

DEC @Ri Subtract 01H from an internal RAM location whose 8-bit address is being pointed by R0 or R1 register.

1 12

INC DPTR Add 01H with the 16-bit content of the Data Pointer Register. 1 24 MUL AB Multiply together the unsigned contents of the A and B registers.

The lower byte of the result is in the A-register and the upper-byte is in the B-register.

1 48

DIV AB Divide the unsigned 8-bit content of A-register by the 8-bit unsigned content of B-register. After division, the A-register receives the quotient and the B-register receives the remainder.

1 48

DA A Carry out decimal adjustment on the content of A-register to get correct BCD result after the addition of two BCD numbers.

1 12

D: Logical Operations

ANL A, Rn Logical AND operation between 8-bit data of A-register and the 8-bit data of Rn (n = 0 – 7) register.

1 12

ANL A, direct Logical AND operation between 8-bit data of A-register and the 8-bit data of an internal RAM location whose 8-bit address is directly given in the instruction.

2 12

ANL A, @Ri Logical AND operation between 8-bit data of A-register and the 8-bit data of an internal RAM location whose 8-bit address is being pointed by R0 or R1 register.

1 12

ANL A, #data Logical AND of immediate 8-bit data with the 8-bit of A-register 2 12 ANL direct, A Logical AND of direct RAM location with the content of A-

register. The result will be in the direct RAM location. 2 12

ANL direct, #data Logical AND of immediate 8-bit data with the content of direct RAM location. The result will be in the direct RAM location.

3 24

ORL A, Rn Logical OR of a GPR (R0 – R7) with 8-bit content of A-register. 1 12 ORL A, direct Logical OR of the 8-bit content of direct RAM location with A-reg. 2 12 ORL A, @Ri Logical OR of a RAM location pointed by R0 or R1 with A-register. 1 12 ORL A, #data Logical OR of an immediate 8-bit data with the content of A-reg. 2 12 ORL direct, A Logical OR of the content of A-register with the content of direct

RAM location. The result will be in the direct RAM location. 2 12

ORL direct, #data Logical OR of an 8-bit immediate data with the 8-bit content of direct RAM location. The result will be in the direct RAM location.

3 24

XRL A, Rn Logical exclusive OR of a GPR (R0 – R7) with 8-bit content of A-register.

1 12

XRL A, direct Logical exclusive OR of the 8-bit content of direct RAM location with A-register.

2 12

XRL A, @Ri Logical exclusive OR of a RAM location pointed by R0 or R1 with A-register.

1 12

XRL A, #data Logical exclusive OR of an immediate 8-bit data with the content of A-register.

2 12

XRL direct, A Logical exclusive OR of the content of A-register with the content of direct RAM location. The result will be in the direct RAM location.

2 12

XRL direct, #data Logical exclusive OR of an 8-bit immediate data with the 8-bit content of direct RAM location. The result will be in the direct RAM location.

3 24

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469

CLR A Put Os to all bits of A-register 1 12 CPL A Invert all the bits of A-register 1 12 RL A Rotate every bit of A-register to the left by one position. MSB will

be put at A0 position. 1 12

RLC A Rotate every bit of A-register to the left by one position. MSB will be put in C-bit and the C-bit will be put in A0 position.

1 12

RR A Rotate every bit of A-register to the right by one position. LSB will be put at A7 position.

1 12

RRC A Rotate every bit of A-register to the right by one position. LSB will be put in C-bit and the C-bit will be put in A7 position.

1 12

SWAP A The lower 4-bit of A-register will be exchanged with its upper 4-bit 1 12 E: Program Branching

ACALL adr11 Absolute subroutine call. 2 24 LCALL adr16 Long subroutine call. The SUR is located at the 16-bit address that

follows the opcdoe LCALL. 3 24

RET Return to Mainline Program from after finishing a subroutine. 1 24 RETI Return to Mainline program after finishing an Interrupt

Subroutine. 1 24

AJMP adr11 Absolute jump with 2k boundary 2 24 LJMP adr16 Long jump. Target program is location at the 16-bit address that

follows the opcdoe LJMP. 3 24

SJMP rel Short jump 2 24 JMP @A+DPTR Go to location whose 16-bit address is to computed by adding the

8-bit content of A-register with the 16-bit content of DPTR. 1 24

JZ rel Jump to target location if the content of A-register appears to be zero.

2 24

JNZ rel Go to the target location if the content of A-register is not zero. 2 24 CJNE A, direct, rel Compare the content of A-register with the content of direct RAM

location and then go to target location if they are not equal. 3 24

CJNE A, #data, rel Compare the content of A-register with 8-bit immediate data given in the instruction and then go to the target location if they are not equal.

3 24

CJNE Rn, #data, rel Compare the content of a GPR (R0 – R7) with 8-bit immediate data given in the instruction and then go to the target location if they are not equal.

3 24

CJNE @Ri, #data, rel Compare the 8-bit content of the RAM location pointed by R0 or R1 with the 8-bit immediate data given in the instruction and then go the target location if they are not equal.

3 24

DJNZ Rn, rel Decrement the content of a GPF (R0 – R7) and then go the target location if its content is not zero.

3 24

DJNZ direct, rel Decrement the content of the direct RAM location and then go to the target location if its content is not zero.

3 24

NOP No operation. The PC is incremented by one. 1 12 .

Instruction Set Summary of 8051 Microcontroller

470

Instruction Template

Instruction Hex Code Number of Bytes Opcode Operands

00 1 NOP 01 2 AJMP code addr 02 3 LJMP Code addr 03 1 RR A 04 1 INC A 05 2 INC Data addr 06 1 INC @R0 07 1 INC @R1 08 1 INC R0 09 1 INC R1 0A 1 INC R2 0B 1 INC R3 0C 1 INC R4 0D 1 INC R5 0E 1 INC R6 0F 1 INC R7 10 3 JBC Bit addr, code addr 11 2 ACALL Code addr 12 3 LCALL Code addr 13 1 RRC A 14 1 DEC A 15 2 DEC Data addr 16 1 DEC @R0 17 1 DEC @R1 18 1 DEC R0 19 1 DEC R1 1A 1 DEC R2 1B 1 DEC R3 1C 1 DEC R4 1D 1 DEC R5 1E 1 DEC R6 1F 1 DEC R7 20 3 JB Bit addr, code addr 21 2 AJMP Code addr 22 1 RET 23 1 RL A 24 2 ADD A, #data 25 2 ADD A, data addr 26 1 ADD A, @R0 27 1 ADD A, @R1 28 1 ADD A, R0 29 1 ADD A, R1 2A 1 ADD A, R2 2B 1 ADD A, R3 2C 1 ADD A, R4 2D 1 ADD A, R5 2E 1 ADD A, R6 2F 1 ADD A, R7 30 3 JNB Bit addr, code addr 31 2 ACALL Code addr

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471

Instruction Hex Code Number

of Bytes Opcode Operands 32 1 REI 33 1 RLC A 34 2 ADDC A, #data 35 2 ADDC A, data addr 36 1 ADDC A, @R0 37 1 ADDC A, @R1 38 1 ADDC A, R0 39 1 ADDC A, R1 3A 1 ADDC A, R2 3B 1 ADDC A, R3 3C 1 ADDC A, R4 3D 1 ADDC A, R5 3E 1 ADDC A, R6 3F 1 ADDC A, R7 40 2 JC Code addr 41 2 AJMP Code addr 42 2 ORL Data addr, A 43 3 ORL Data addr, #data 44 2 ORL A, #data 45 2 ORL A, data addr 46 1 ORL A, @R0 47 1 ORL A, @R1 48 1 ORL A, R0 49 1 ORL A, R1 4A 1 ORL A, R2 4B 1 ORL A, R3 4C 1 ORL A R4 4D 1 ORL A, R5 4E 1 ORL A, R6 4F 1 ORL A, R7 50 2 JNC Code addr 51 2 ACALL Code addr 52 2 ANL Data addr, A 53 3 ANL Dataaddr, #data 54 2 ANL A, #data 55 2 ANL A, data addr 56 1 ANL A, @R0 57 1 ANL A, @R1 58 1 ANL A, R0 59 1 ANL A, R1 5A 1 ANL A, R2 5B 1 ANL A, R3 5C 1 ANL A, R4 5D 1 ANL A, R5 5E 1 ANL A, R6 5F 1 ANL A< R7 60 2 JZ CODE ADDR 61 2 AJMP Code addr 62 2 XRL Data addr, A 63 3 XRL Data addr, #data 64 2 XRL A, #data 65 2 XRL A, data addr

Instruction Set summary of 8051 Microcontroller

472

66 1 XRL A, @R0 67 1 XRL A, @R1 68 1 XRL A, R0 69 1 XRL A, R1 6A 1 XRL A, R2 6B 1 XRL A, R3

Instruction Hex Code

Number of Bytes Opcode Operands

6C 1 XRL A, R4 6D 1 XRL A, R5 6E 1 XRL A, R6 6F 1 XRL A, R7 70 2 JNZ Code addr 71 2 ACALL Code addr 72 2 ORL C, bit addr 73 1 JMP @A+DPTR 74 2 MOV A, #data 75 3 MOV Data addr, #data 76 2 MOV @R0, #data 77 2 MOV @R1, #data 78 2 MOV R0, #data 79 2 MOV R1, #dara 7A 2 MOV R2, #data 7B 2 MOV R3, #data 7C 2 MOV R4, #data 7D 2 MOV R5, #data 7E 2 MOV R6, #dta 7F 2 MOV R7, #data 80 2 SJMP Code addr 81 2 AJMP Code addr 82 2 ANL C, bit addr 83 1 MOVC A, @A+PC 84 1 DIV AB 85 3 MOV Data addr, data addr 86 2 MOV Data addr, @R0 87 2 MOV Data addr, @R1 88 2 MOV Data addr, R0 89 2 MOV Data addr, R1 8A 2 MOV Data addr, R2 8B 2 MOV Data addr, R3 8C 2 MOV Data addr, R4 8D 2 MOV Data addr, R5 8E 2 MOV Data addr, R6 8F 2 MOV Data addr, R7 90 3 MOV @DPTR, A 91 2 ACALL Code addr 92 2 MOV Bit addr, C 93 1 MOVC A, @A+DPTR 94 2 SUBB A, #data 95 2 SUBB A, data addr 96 1 SUBB A, @R0 97 1 SUBB A, @R1 98 1 SUBB A, R0

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99 1 SUBB A, R1 9A 1 SUBB A, R2 9B 1 SUBB A, R3 9C 1 SUBB A, R4 9D 1 SUBB A, R5 9E 1 SUBB A, R6 9F 1 SUBB A, R7 A0 2 ORL C, /bit addr A1 2 AJMP Code addr A2 2 MOV C, bit addr A3 1 INC DPTR A4 1 MUL AB A5 - - - A6 2 MOV @R0, data addr A7 2 MOV @R1, dataaddr

Instruction

Hex

Code

Number of Bytes Opcode Operands

A8 2 MOV R0, data addr A9 2 MOV R1, data addr AA 2 MOV R2, data addr AB 2 MOV R3, data ddr AC 2 MOV R4, data addr AD 2 MOV R5, data addr AE 2 MOV R6, data ddr AF 2 MOV R7, data addr B0 2 ANL C, /bit addr B1 2 ACALL Code addr B2 2 CPL Bit addr B3 1 CPL C B4 3 CJNE A, #data, code addr B5 3 CJNE A, data addr, code adr B6 3 CJNE` @R0, #data, code addr B7 3 CNE @R1, #data, code addr B8 3 CJNE R0, #data, code addr B9 3 CJNE R1, #data, code addr BA 3 CJNE R2, #data, codeaddr BB 3 CJNE R3, #data, code addr BC 3 CJNE R4, #data, code addr BD 3 CJNE R5, #data, code addr BE 3 CJNE R6, #data, code addr BF 3 CJNE R7, #data, code addr C0 2 PUSH Data addr C1 2 AJMP Code addr C2 2 CLR Bit addr C3 1 CLR C C4 1 SWAP A C5 2 XCH A, data addr C6 1 XCH A, @R0 C7 1 XCH A, @R1 C8 1 XCH A, R0 C9 1 XCH A, R1 CA 1 XCH A, R2 CB 1 XCH A, R3 CC 1 XCH A, R4

Instruction Set Summary of 8051 Microcontroller

474

CD 1 XCH A, R5 CE 1 XCH A, R6 CF 1 XCH A, R7 D0 2 POP Data addr D1 2 ACALL Code addr D2 2 SETB Bit addr D3 1 SETB C D4 1 DA A D5 3 DJNE Data addr, code addr D6 1 XCHD A, @R0 D7 1 XCHD A, @R1 D8 2 DJNE R0, code addr D9 2 DJNE R1, code addr DA 2 DJNE R2, code addr DB 2 DJNE R3, code addr DC 2 DJNE R4, code addr DD 2 DJNE R5, code addr DE 2 DJNE R6, code addr DF 2 DJNE R7, code addr E0 1 MOV A, @DPTR E1 2 AJMP Code addr E2 1 MOVX A, @R0 E3 1 MOVX A, @R1

Instruction Hex

Code Number of Bytes Opcode Operands

E4 CLR 1 A E5 2 MOV A, data addr E6 1 MOV A, @R0 E7 1 MOV A, @R1 E8 1 MOV A, R0 E9 1 MOV A, R1 EA 1 MOV A, R2 EB 1 MOV A, R3 EC 1 MOV A, R4 ED 1 MOV A, R5 EE 1 MOV A, R6 EF 1 MOV A, R7 F0 1 MOVX @DPTR, A F1 2 ACALL Code addr F2 1 MOVX @R0, A F3 1 MOVX @R1, A F4 1 CPL A F5 2 MOV Data addr, A F6 1 MOV @R0, A F7 1 MOV @R1, A F8 1 MOV R0, A F9 1 MOV R1, A FA 1 MOV R2, A FB 1 MOV R3, A FC 1 MOV R4, A FD 1 MOV R5, A FE 1 MOV R6, A FF 1 MOV R7, A

Chapter - 8

475

8.6 (a) Asynchronous Serial Communication Port Operation of 8051 The 8051 have built-in circuitry, which can be configured to exchange ‘asynchronous data frame’ with a remote computer or another 8051-based controller. The concepts of serial IO discussed in Chapter-4 will be equally applicable here. The connection diagram between the serial port of 8051 and the 9-pin serial port (COM1) of the IBMPC is shown below in Fig-8.10. The circuit is taken from the Technical Reference Manual of MicroTalk-8051, which is an 8051 Microcontroller Learning System developed by the author.

Structures and Connection Diagram of the Serial Port Section of 8051 with IBMPC

Figure-8.13: Connection Diagram between Serial Port Section of 8051 MCU with IBMPC

Detailed Internal Structure of Serial Port of 8051 Microcontroller

Figure-8.14: Internal Structure of Serial Port Section of 8051 Microcontroller

TxD

Rx Buffer RxD

Port-3 : B0H

Address: 99H

Address: 99H

Tx Buffer

P30P31P32P33P34P35P36P37

P30

P31

10

11

121314151617

Serial Section of 8051 Microcontroller

RXTTL

TXTTL

753xy : GM : 03-07

Rx Full InterruptTx Empty Interrupt

TI

RI

ESEA

IRQ: 0023H

b0b4b7IE*

SCON*b0b1b7 REN

b4

TxD

Rx Buffer RxD

Port-3 : B0H

Address: 99H

Address: 99H

Tx Buffer

P30P31P32P33P34P35P36P37

P30

P31

10

11

121314151617

U2: 8051 Microcontroller U24 : MAX232 J12: Holes

TTL <--> RS232

12 R1OUT

11 T1IN

R1IN 13

14T1OUT

J6-10RXTTL

J6-12TXTTL

J6-13TXRS

J6-11RXRS

1

2

3

4

5

6

7

8

9

COM1 Port of IBMPC

Pins

1

3

2

4

5

6

7

8

9

CD/

DTR/

DSR/

RTS/

CTS/

+5V

TXRS

RXRS

0V15 COM

753x : GM : 03-07

MicroTalk-8051 IBMPC

Rx FullInterrupt

Tx EmptyInterrupt

IRQ: 0023H

Asynchronous Serial Communication Port Operation of 8051

476

Working Principle: The Rx-buffer works as an asynchronous serial receiver whenever the switch REN is brought to close condition by putting LH at bit-4 of the SCON register. The Rx-buffer receives the incoming frame over Pin-10 of the MCU. The Rx-buffer strips out the start, parity and the stop bits from the received frame and then sets the RI (Receiver Full Indicator) bit of the SCON register. If the interrupt enable switches ES and EA are already closed, then the MCU will be automatically interrupted. Similarly, the Tx-buffer is an asynchronous serial transmitter. The Tx-buffer automatically starts transmitting a frame whenever an 8-bit data (an ASCII character or a Binary byte) is written into it. The frame is transmitted over Pin-11 of the MCU. At the end of the transmission of the current data byte, the Tx-buffer sets the TI (Transmitter Empty Indicator) bit of the SCON register. If the interrupt enable switches ES and EA are already closed, then the MCU will be automatically interrupted. The Rx- and the Tx-buffer are assigned the same address (99H). This is perfectly correct in the sense that the Rx-buffer is a read-only register and the Tx-buffer is a write-only register. The software name for both of them is SBUF (Serial Buffer). We may notice that the MCU jumps at the same ISUR address (002CH) whether the interrupt comes from the Rx-buffer or the Tx-buffer. The MCU resolves this ambiguity by polling the RI and TI bits at the beginning of the ISURSER. The sample codes are:

ORG 0023H ISURSER: NOP

L1: JB RI, RECEIVE L2: ; this an interrupt due to Tx-buffer emptiness. MOV SBUF, ‘A’ ;character A is written for xmit. ………………………………………………………………………….. RECEIVE: MOV A, SBUF ; data is read from Tx-buffer ………………………………………………………………………………………………………………..

When the MCU is vectored to ISURSER, the RI and the TI bits of the SCON register are automatically reset and the MCU is ready to handle the next interrupt. However, the user may serve the serial registers by polling method and in that case, the RI and TI bit have to be reset by software at the beginning of the ISURSER.

Registers involved with Serial Port Operation

Table-12 Registers Name Mode Address Rx Buffer (SBUFF=Serial Buffer) Read Only 99H Tx Buffer (SBUFF) Write Only 99H SCON (Serial Control) Read/Write 98H IE (Interrupt Enable) Read/Write A8H IP (interrupt Priority) Read/Write B8H PCON (Power Control) Read/Write 87H TMOD (Timer Mode) Read/Write 89H TCON (Timer Control) Read/Write 88H TH1 (High Byte of Timer-1) Read/Write 8DH TL1 (Low Byte of Timer-1) Read/Write 8BH

Chapter - 8

477

Baud Rate Determination: The standard baud rates supported by 8051 are indicated in Table-8.1, which can be generated using Timer-1 of the 8051. In this application, the TC-1 is configured for ‘timer’ operation and in the auto-reload mode. The Timer-1 interrupt must be disabled. The baud rate is given by:

Bd = ((2SMOD)/32) X ((Crystal Frequency)/(12*(0100H – TH1)))

Table-8.1 Timer-1 Baud Rate Crystal

Frequency SMOD

C-T/ MODE Reload Value (IH1) 19200 11.059MHz 1 0 2 FDH 9600 11.059MHz 0 0 2 FDH 4800 11.059MHz 0 0 2 FAH 2400 11.059MHz 0 0 2 F4H 1200 11.059MHz 0 0 2 E8H

The Assembly Codes for 4800 Bd, Frame Length 10: L1: MOV SCON, #50H ; 8-bit UART, 8-bit data, 1-Stop Bit, No parity, receiver enable MOV PCON, 00H ; SMOD is set to ‘0 (zero)’ for Bd=4800 MOV TH1, #0FAH ; Auto reload value for Bd = 4800 MOV TMOD, #20H ; Timer/Counter-1 is set to operate as Timer in Mode-2 MOV IE, #00H ; All interrupts are disabled

MOV TCON, #40H ; Timer-1 is enabled to ‘run’

8.6 (b) External Hardware Interrupt Operation of 8051

Figure-8.15: External Hardware Interrupt Operation of INT0-pin

Working Principles: a. Assume that the SWA is at position ‘1’, which could be done by writing LH at IT0-bit of the

TCON register. b. When a High-to-Low going signal appears at Pin-12, the IE0-bit of TCON register is set to

LH. c. Assume that the switches SWB and SWC are closed. These switches could be opened and

closed as required by manipulating the relevant bit of the IE register. d. The MCU would be automatically interrupted. e. The MCU would suspend the mainline program and would jump to the ‘Interrupt Service

Routine’ due to INTO (ISURINT0) at the address: 0003H. This is known as ‘Vectored Interrupt’.

f. If the switches SWB and SWA are opened, then the user can still detect the occurrence of the arrival of an interrupting signal at Pin-12 by reading the IE0-bit and then the user can deliver the interrupt services. This is known as ‘Polling Interrupt’.

12 INT0/ (P32) IE0SWA

0

1IT0=0,1

SWB SWC

EA=1 EX0=1

IRQ : 0003H

IT0

IE0

IT1

IE1TCON (88H) EX0

EA IE (A8H)

1100

cngmet\ch8n\8-9n+5VInernalPullup(5k)

InterruptingDevice (K1)

Asynchronous Serial Communication Port Operation of 8051

478

8.6 (c) Timing Functions of 8051

Figure-8.16: Mode-0 Operation of Timer-1 to Generate 8.912mS Time Quanta

The 8051 have two (89S8252 has three) 16-bit identical TC (Timer-Counter) registers. Each of them is composed of two 8-bit registers as per following break up:

i. TC0 : THO ; Timer-0 Higher 8-bit : TL0 ; Timer-0 Lower 8-bit ii. TC1 : TH1 ; Timer-0 Higher 8-bit : TL1 ; Timer-0 Lower 8-bit

The TC is said to be operating in Timer mode, when its driving pulses are obtained from the internal oscillator of the MCU. It is said to be working as Counter when the driving pulses are coming from external source. In Fig-8.16, the TC1 is operating in Timer-1 mode operation. When the switch is placed in Position-B, it will be working as Counter-1. The software name of the TC1 is always TH1 and TL1 whether it is working as Timer or Counter.

The circuit of Fig-8.16 has been initialized to work as Timer-1 in Mode-0. In this mode, the Timer-1 works as divide-by-13 counter. After receiving 213 pulses (at the elapse of 8192 µS), the Timer-1 rolls over and the TF1-bit assumes LH-state. The MCU can continuously poll the TF1-bit to see that 8192 µS has elapsed or it may be interrupted if interrupt logic are enabled. There are many other interesting mode of operations for TC1, which could be invoked to generate desired timing functions like generating 1mS or even 1µS time interval. The timer can also be used to measure the width of an unknown pulse like the phase difference between the voltage and current and thus estimating the power factor. 8.6 (d) Counter-0 Operation of 8051

Figure-8.17: Structure of Counter-0 of8051in Mode-2 (8-Bit Auto Reload) Operation

OSC 1/12 f1= 1000 KHzY1

C0-T0/=1

SW2SW1

18

19

XT2

XT112 MHz

TF0

534b

C0 (P34)14

TL0(8-bit)

TH0(8-bit)

Address:8AH

Address:8CH

IRQ: 000BH

Auto Reload

SW3

A

B

TR0 TCON(88H)*TF

0

CT0 TMOD(89H)

SW4

IE (A8H)*ET0

EA

b2

b0

OSC 1/12 f1=1MHzY1

C1-T1/=0SW2

SW1 TL1(5-bit)

TH1(8-bit)

18

19

XT2

XT112 MHz

13-BitMode-0

TF1

534c

8DH8BH

14 P34

A

B

Chapter - 8

479

The above circuit works as Counter-0 when SW1 is brought to Position-B by putting LH at TMOD2-bit. The same circuit is termed to be operating as Timer-0 when SW1 is at Position-A. The closing mechanism of the switches SW2, SW3, SW4 is clearly indicated in the circuit. The TL0 is an 8-bit up counter. It keeps counting up the external pulses that arrive at its C0-pin until all bits are 1s. When next pulse comes, the counter rolls over from all 1s to all 0s and this roll over condition is reflected by having LH at TCON5-bit (symbolic name is TF0). During roll over, the TL0 is automatically loaded with the content of the TH0-register. The value of TH0 sets the preloaded count of TL0. The TL0 keeps adding the external pulses with the preloaded value. At certain time, the Counter-0 rolls over. As a result, the TF0-bit is set, which in turn interrupts the MCU should the switches SW3 and SW4 are in closed condition. 8.7 (a) 8051-DS12C887 Based Real Time Clock System

Figure-8.18: Schematic Diagram of an 89S51-12C887 Based Real Time Clock 8.7.A1 RTC Clock Chip DS12C877 It is a 24-pin packaged IC, which has been used in the IBMPC. The chip is compatible with both the Motorola and Intel bus system. The chip contains a lithium energy source (battery), which allows it maintaining a running clock for 10 years. A built-in crystal oscillator provides the basic timings for the clock. The clock chip provides many functions, which have been detailed in its data sheet. In this application, we have operated the chip as a simple 12-hr clock where the time is advanced by 1-sec. The registers of the chip are seen by the microcontroller as memory locations and at the addresses shown below:

RST

0V

R15k

+5C1100uF+

K1

VccGND

+50V

P17P1

P10

P0

88 - 1

PSEN/NC

ALE

EA/+5V

XT1 XT2

Y1 = 12.00 MHz

Rtclk : GM : 09-2008

+5

RN1:8x560RSecurity Bit

Code Memory(8k Flash)

0000H – 1FFFH

256 Byte RAM00H – 7FH

Register Set

1/6th of Y1

TTL of Y1

p,…,a

AD7

AD03938

3637

353433

U2 : DS12C887

32

AD0

AD7

45

11

6789

10

A15(P28) 28 CS/13ALE(AS)

RD/(P37)WR/(P36)

RD/(DS)WR/(R-W/)

30

1716

+5V

1715

AD6AD5AD4AD3AD2AD1

14

RESETIRQ/

1819 NC

2 – 3,16 NC20-22 NC

SQW NC

+5V0V

cc0

1224

2329

31

4020

cc5

8P35-P30 14 - 10

HRS MIN SEC

P30 P359

U1: 89S51

NC P36-P3715 - 16

1918

NC P20 – P2721 - 27

CC7SDD

1

20k

MOT-INTEL/ 0V

DP0 DP5DP1 DP2 DP3 DP4

Timing Functions of 8051 Microcontroller

480

Register Name Address Functions 1. Seconds Register 0000h Contains Seconds of the Time 2. Seconds Alarm 0001h 3. Minutes Register 00002h Contains Minutes of the Time 4. Minutes Alarm 0003h 5. Hours Register 0004h Contains Hours of the Time 6. Hours Alarm 0005h 7. Day of the Week 0006h 8. Day of the Month 0007h 9. Month 0008h 10. Year 0009h 11. Register A 0000Ah 1-sec elapse indication, clock start 12. Register B 000Bh Format of Time: 12-hr or 24-Hr 13. Register C 000Ch 14. Register D 000Dh 15. Protected RAM 000Eh – 0031h 16. Century 0032h 17. Protected RAM 0033h – 007Fh 8.6.A2 Clock Time The MCU continuously monitors the A7-bit for LL of Register-A to see that 1-sec time has elapsed. The MCU reads the current BCD time from the RTC and puts them into the BCDTIME data structure (Section – 8.6.A) of the MCU. The BCDTIME is converted into CCTIME and then is displayed at DP0 – DP5 positions of the CC7SDD. The CC7SDD display unit is of multiplexed type and is being refreshed continuously by the MCU itself in the middle of reading the current time from the RTC. The pull up resistor RN1 of Port-1 can be adjusted to get an acceptable level of light intensity for the display devices DP0 – DP5. 8.6.A3 +5V Power Supply for the Clock System The following circuit of Fig-8.19 may be employed to obtain +5V DC supply for the Clock System of Fig-8.18. This type of +5V Dc power source is usually employed in the AD5755 based Digital Energy Meter and similar applications. MOV1 (the varistor) and L1 together prevent the line transient noise from appearing at the +5V point. The circuit works on the principles of half wave rectification by catching the negative half cycle of the line frequency. The user must use a 220v/220V (100VA) isolation transformer while developing and testing the circuit in order to avoid lethal electric shock.

Figure-8.19: Direct 220VAC Based +5V DC Power Supply for the Clock System

L1Ferrite Bread

N

L

MOV1681

R1330R, 1W

C10.47uF, 280V

Z115V

D1

C20.1uF

C3470uF, 25V+ +

C40.1uF

C5100uF16V

1 3

2

7805 +5V

COM (0V)

Rtclk : GM : 09 - 2008

Chapter - 8

481

8.6.A4 Data Structure for the Clock System

Figure-8.20: Internal RAM Based Data Structure for Real Time Clock System

At the elapse of every 1-sec time, the MCU updates the BCDTIME of Fig-8.20. The MCU converts the BCDTIME into CCTIME (Time in Common Cathode Format) using subroutine BCD2CC. The CCTIME is transferred to display device via Port-1 with the help of subroutine CCX7SDD. The Port-3 of MCU scans the CC-pins of the display devices.

8.6.A5 Control Program for the RTC (Pseudo Codes) START: NOP

ML1: Initialize Stack and PSW

ML1A: Initialize CC-table in internal RAM

ML1B: Initialize the RTC - oscillator ON by sending 20H into A-register - Time format : BCD and 12-hr (78H → B-register)

ML1C: Set initial time - (xx) into HRS reg - (yy) into MIN reg - (ZZ) into SEC reg

ML2: Read A-register If (A7 = LL) Goto ML3 ; 1-sec time has elapsed Refresh Display by executing codes at label ML4B (TIME_R)

ML3: NOP

ML4: Update BCDTIME

ML4A: Convert BCDTIME into CCTIME

ML4B: Transfer CCTIME into CC7SDD

ML5: Goto ML2

8.6.A6 Assembly Codes for the Control Program (…\pspkit\rtclk.asm) ORG 0000H DB 02H DB 00H DB 10H

ORG 0010H ML1: MOV SP, #70H ; Stack Pointer init MOV PSW, #00H ; Bank init ML1A: MOV 40H, #3FH ; 0 ; Cc-table init MOV 41H, #06H ; 1 MOV 42H, #5BH ; 2 MOV 43H, #4FH ; 3 MOV 44H, #66H ; 4

IRAM BCD

BCDTIME

IRAM

54

52

53

5 : GM : 10-08

MIN

HRS

SEC

BCD2CC

CC

3A3B

DP0

3C3D3E3F

SEC

MIN

HRS

CCX7SDD

HRS MIN SECDP5…...

CC7SDD

CCTIME

8051-DS12C887 Based Real Time Clock System

482

MOV 45H, #6DH ; 5 MOV 46H, #7DH ; 6 MOV 47H, #07H ; 7 MOV 48H, #7FH ; 8 MOV 49H, #6FH ; 9 CC-code table at upper RAM of MCU

ML1B: MOV A, #20H ; RTC init MOV DPTR, #000AH ; Register-A MOVX @DPTR, A

MOV A, #78H ; 12 Hr Clock MOV DPTR, #000BH ; Regsiter-B MOVX @DPTR, A

ML1C: MOV A, #11H ; Current Time Set into RTC 11:56:03 MOV DPTR, #0004H ; HRS Regsiter MOVX @DPTR, A MOV 54H, A ; BCDTIME data table

MOV A, #56H ; Current Time - MIN MOV DPTR, #0002H ; MIN ZRegister MOVX @DPTR, A MOV 53H, A

MOV A, #03H ; Current Time SEC MOV DPTR, #0000H ; SEC Regsiter MOVX @DPTR, A MOV 52H, A

ML2: MOV DPTR, #000AH ; Reading Register-A JNB 0E7H, ML3 ; 1-sec has eleapsed LJMP TIME_R ; CCTIME to CC7SDD

ML3: NOP ML4: ; update BCD Time of Data Structure ; TIME_UPDATE: MOV A, 52H ADD A, #01H DA A CJNE A, #60H, ADJ1 MOV 52H, #00H MOV A, 53H ADD A, #01H DA A CJNE A, #60H, ADJ2 MOV 53H, #00H MOV A, 54H ADD A, #01H DA A CJNE A, #24H, ADJ3 MOV 54H, #00H LJMP TIME_REFRESH ADJ1: MOV 52H, A LJMP TIME_REFRESH ADJ2: MOV 53H, A LJMP TIME_REFRESH ADJ3: MOV 54H, A

ML4A: ;TIME_REFRESH: convert BCDTIME into CCTIME using cc-code Table of ML1A: MOV R0, #54H ; R0 points at BCDTIME Table MOV R1, #3FH ; R1 points at CCTIME Table MOV R2, #03H ; Number of BCD bytes to convert

Chapter - 8

483

LSR1: MOV A, @R0 ; A=00 ; getting 1st BCD SWAP A ANL A, #0FH ; A =00 ; to get cc code ADD A, #40H ; A= 80 MOV 03H, R1 ; R1=R3=3F ; temporary saved MOV R1, A ; R1 = 40 MOV A, @R1 ; A = C0 MOV R1, 03H ; R1 = R3 = 3F MOV @R1, A ; (3F) = C0H MOV A, @R0 ; A = 00 ANL A, #0FH ADD A, #40H ; A = 40 MOV 03H, R1 ; R1=R3=3F MOV R1, A ; R1 = 40 MOV A, @R1 ; A = C0 MOV R1, 03H ; R1=R3 = 3F DEC R1 ; R1=3E MOV @R1, A ; (3EH) = C0 DJNZ R2, LFW LJMP FRWX LFW: DEC R0 DEC R1 LJMP LSR1

FRWX: MOV A, 3EH ; placing points ORL A, #80H MOV 3EH, A MOV A, 3CH ORL A, #80H MOV 3CH, A

ML4B: ; CCTIME to CC7SDD ; TIME_R: ; CCX7S: MOV P0, 3FH MOV P3, #0FEH ; DP0 1111 1110 LCALL TDELAY MOV P0, 3EH MOV P3, #0FDH ; DP1 1111 1101 LCALL TDELAY MOV P0, 3DH MOV P3, #0FBH ; DP2 1111 1011 LCALL TDELAY MOV P0, 3CH MOV P3, #0F7H ; DP3 1111 0111 LCALL TDELAY MOV P0, 3BH MOV P3, #0EFH ; DP4 1110 1111 LCALL TDELAY MOV P0, 3AH MOV P3, #0DFH ; DP5 1101 1111 LCALL TDELAY ML5: LJMP ML2

TDELAY: MOV R6, #20H HERE2: MOV R7, #20H HERE1: DJNZ R7, HERE1 DJNZ R6, HERE2 RET END

8051-DS12C887 Based Real Time Clock System

484

8.7 (b) 8051-Based Single Chip Digital Weighing Machine (DWM) 8.7.B1 Introduction In Chapter-7, we studied the design of an 8086-based Digital Weighing Machine in order to experience the real applications of the ‘functional properties’ of a microprocessor in the implementation of various processing algorithms. In this chapter, we intend to develop a realistic DWM based on 8051 architecture to arrive at a cost-effective and copy protected. The diagram of Fig-8.21 depicts the initial idea in the form of block diagram of the target DWM.

Figure-8.21: 8051-based Copy Protected Digital Weighing Machine The readers should recognize the challenges that they must defeat to realize the block diagram of Fig-8.21 into a working machine. The challenges are due to the following characteristic features of the DWM: i. There is no dedicated 8279 controller to handle the keyboard and the display, ii. The MCU of Fig-8.21 must drive a multiplex type display unit, which must be

continuously refreshed to avoid flickering. iii. The acquisition of Weight and necessary conversion must be accomplished in the

middle of refreshing the display. iv. The product rate must be acquired on Interrupt. Therefore, the discrete components

based keyboard must be able to interrupt the MCU. v. The Control Program should be able to compute the cost using all the routines

developed in Chapter-7 and show the Weight, Rate and Cost on the 7-segment display. It is recommended that the readers should use a suitable ‘8051-based Microcontroller Learning System’ to test the functionalities of various hardware and software involved in this job. Finally, all the parts could be hooked up together to see that the ‘Multiplexed DWM’ works! 8.7.B2 Load Cell and Amplifier Circuit They are exactly the circuits discussed in Chapter-7. 8.7.B3 ADC Circuit It is exactly the circuit of Chapter-7 but the ADC’s output lines will now be connected with the Port-1 pins of the 8051 microcontroller

P17-P10

P07 - P00

P23-P20

P27 - P24

P32 - P30

Load Cell Amplifier ADC Microcontroller 4 to16 MUX

PWR BUF

PWR BUF

PWR BUFDisplay

DP0-DP7

DisplayDP8 - DP15

Keyboard

Weight

ROMRAM

GM:648a: 06-04:10-05

Chapter - 8

485

8.7.B4 Discrete Components Based Keyboard The ‘Discrete Components Based Keyboard’ of Fig-8.22 is really a ‘Smart Keyboard’. It can generate Scan Code for a pressed down key and at the same time generating an interrupt signal for the MCU. The author does not claim the ‘design idea’ of this keyboard but claims the credit for presenting the circuit in a way it is done here. The source of the circuit is MDA-8086 Reference Manual, which has not put any restriction on the use of this circuit.

Figure-8.22: Discrete Components Based Keyboard

Working Principles: The heart of the keyboard circuit is the component U1, which is a ‘Priority Encoder’ chip. This is the chip, in conjunction with the transistors TR1 and TR2 generate the scan codes for the pressed down keys of the keypad. TR1 and TR2 provide the column lines for the keyboard matrix. The keyboard works in a very interesting way.

When all the keys are at open conditions, the row lines are isolated from the column lines and the inputs to the U2 are 00000000B. According to the truth table of the U1 (4532), when the inputs are at 0s, the output E0=LH and GS=0. It is assumed that prior to the operation of the keyboard, asserting LL at P34-pin by executing the instruction CLR P34 has reset it. When any one key of the keypad is pressed down, the Q/-pin of U3 immediately goes to LL. The Q/-pin can be connected to interrupt the MCU for notifying that a key has been pressed down in the keypad.

Say, the key-8 is pressed down. The column line provided by TR2 is shorted with the D7 line of the U27. The voltage at D7 of U27 becomes: 5V – VEBTR2 (0.7V) = 4.3V, which is Logic-H. Because, the TR2 is ON, its collector voltage is very close to +5V (LH), which constitutes Bit-3 of the scan code. With the bit pattern as 10000000 at the inputs of U1, the output of U1 would be 111 (Q2Q3Q1). The EO-pin assumes LL and the GS-pin assumes LH. The activity of the EO signal triggers the 33mS-oneshot U2. The 33mS pulse width is intentionally chosen to allow the complete extinction of the debounching pulses of the mechanical key. The inverted output of U2 clocks the GS-bit into the latch, U3 after 33mS time delay. This results in putting LL at Q/-pin of U3. Thus, the scan code for the key-8 stands as: 0111, which is connected to the MCU through P27 – P24 lines.

0V

R23.3k

R43.3k

+5VR13.3k

R33.3k

TR1 TR2

D0D1D2D3D4D5D6D7

EI+5V

EO 5 B

0V 34

+5V

10

C5: 1uFR5 : 33k

Q/

Q

1

6

+ U274121

GS 2 D

CK3

Q/

Q

6

5U3: 7474

R/1

14

15

9

10111213

0201

0304

5

U14532

Q0Q1Q2

76

Reset Enable

544a

01234567

89

RateBKS

33mS

IRQ

0V8x3.3kRN1

P34

INT0/ (P32)

P27P26P25P24

NC

8051-Based Single Chip Digital Weighing Machine

486

8.7.B5 Schematic of the Display Unit

Figure-8.23: Schematic of the CA7SDD Multiplexed Display System

Qdp0 delivers currents for all the CA-type segments of display device DP0. Similarly, Qdp1 supplies currents for the segments of DP1 and so on. Qa – Qp pull the cathodes of the segments to ground potentials. Transistors Qa – Qp are available in a single package as 2803, which is capable of supplying currents at 50V. Similarly, Qdp0 – Qp15 are to be replaced by 2803s.

To see character ‘2’ at DP0 position, let us make y0/-pin active (Qdp0 is OFF) by sending 0000B to the input of 4-to-16 multiplxer. Let us assert appropriate bit pattern on Port-0 so that the cathode terminals of segments a, b, d, e, g are shorted to 0V.

y0/

y15/

+12

Rdp01k

a

b

c pde

f

g

DP0

Qa

Qg

Qb

Qc

Qd

0V

Qe

Qf

Qp

idp0

Qdp0

a

b

c pde

f

g

DP15

idp15

0V

0V

+12

Rdp151k

Qd15

P23P22P21P20 A

BCD

P07

P06

P05

P04

P03

P02

P01

P00

6:GM:10-2008

Chapter - 8

487

8.7.B6 Cost Computation Data Structure for DWM

Figure-8.24: Cost Computation data Structure for the 8051-based DWM of Fig-8.21 Weight Acquisition, Storage, Conversion and Display: The multiplexed uBCD (Unpacked BCD) weight data generated by the ADC of Fig-8.21 is acquired via Port-1, converted to BCD and is saved in BCDWT table of Fig-8.24. It is then converted to CC-code using subroutine BCD2CC and is saved in CCRT table from where it goes to display through subroutine CCXCA7SDD and Port-0. The BCD weight is converted into BINary weight using subroutine BCD2BIN and is saved in table BINWT for subsequent use by the BMULT (Binary Multiplication Subroutine). Rate Acquisition, Storage, Conversion and Display: The product rate (Tk/kg) would be acquired through interrupt. The scan code of a pressed down key is immediately converted to CC-code and is presented on the display. At the end of pressing down all the four keys representing four-digit rate, the scan codes are converted into BCD and are saved in table BCDRATE of Fig-8.24. The BCD rate is converted into BINary rate using subroutine BCD2BIN and is kept in table BINRT for subsequent use by the BMULT subroutine. Cost Computation, Conversion, Storage and Display: The Binary Weight (BINWT) and the Binary Rate (BINRT) are multiplied together using subroutine BMULT to get Binary Cost, which is kept in table BINCOST. The Binary Cost is converted into BCD cost using subroutine BIN2BCD. The BCD cost is then converted into CC-coded Cost using subroutine BCD2CC. The CC-coded cost is finally transferred to display unit using subroutine CCXCA7SDD and Port-0. The readers are referred to Section-8.8 for problems and Solutions to interesting question relating to the design of the 8051-based ‘Multiplexed DWM’.

BCDRATE 5657

IRAM

7 : GM: 10-2008

5554

HB

BCDWT53

LB

LB

HB

HB

MB

BCDCOST MBLB

525150

BCD2BIN

BCD2BIN

IRAM (Scratch)59

5B

BINRT58

5A

HBLB

LBMB

BINWT

BMULT

IRAM (Scratch)

5C

HB

5D5E5F

LB

NBNB BINCOST BIN2BCD

BCD2CC CCXCA7SDDCCRATE

BCDCOST

Display DevicesDPF

BCD2CC CCWT

DPC

DP6

DPDDPE

DP7

DP0

DP8DP9DPA

CCXCA7SDD

BCD2CC CCCOST CCXCA7SDD

DP4

DP1

DP5

DP2DP3

DPB

Rate Display23.75

Weight Display

17.450

Cost Display

414.43

Tk

Kg

Tk

IRAM

CCWT

CCRT

3C

3F3E3D

36373839

HB

LB

HB

LB

CCCOST

31323334

HB

LB30

35IRAM

IRAM

DP0 – DP5

DPC - DPF

DP6 - DPA

8051-Based Single Chip Digital Weighing Machine

488

8.8 Problems and Solutions 1 What is the difference between Byte Processor and Boolean Processor?

2 Indicate the differences between SFR and GPR registers of the 8051. SFR: The named registers in the space 80H – FFh are designated as Special Function Registers GPR: The 32 [4x (R0 – R7) ] registers that are present in the RAM space of the 8051.

3 Indicate the type number of the MCU that has internal EEPROM-based data memory.

4 The Pin-13 of Fig-8.2 is labeled with the signal name: P33(INT1/). What does the signal name mean? Ans: After power up, the Pin-13 will work as general IO line. By software initialization, the same pin can be configured to deliver alternate function that is ‘Receiving External Hardware Interrupt Signal-1’.

5 Indicate the role of the EA/-pin in the process of accessing Internal/External Data and code memory.

6 Indicate the port pins that support alternate functions for Asynchronous Serial Communication.

7 Indicate the difference between byte addressable and bit addressable internal RAM locations of 8051.

8 Which registers out of R0 – R7 could be used as pointer registers?

9 In Port Mode operation, the Port-0 must be operated with a pull up resistor. Why?

11 What is the difference between ‘Reading the Latch’ and ‘Reading a Port-pin’?

12 Draw Mixed-Port operational diagram for the 8051 microcontroller.

13 Copy the following table in your answer script and then fill up the gaps.

8051 Signals PSEN/ RD/ WR/ EA/

Operation Address Asserted By

0 -------

---- LL Reading from External Code Memory PC (range: 0000 – FFFF)

0 1 1 LH ----------------------------------------------- PC (range: ……………….) 1 1 1 LH ----------------------------------------------- PC (range: ……………….) 1 1 0 X ----------------------------------------------- DPTR (range: …………..) 1 0 1 X …………………………………………. R0 (range: ……………….)

14 Write 8051 assembly codes for the following operations: i. move data from RAM location 40H into RAM location 90H. Ans: MOV R0, #90H MOV @R0, 40H ii. move content of P2.2-bit into location P1.0. Ans: MOV C, P2.2 MOV P1.0, C iii. 37H x 45H Ans: MOV A, #37H MOV B, #45H MUL AB

iv. A + B 45H Ans: ADD A, B v. If A0 = LH then branch to label LX. Address of A0-bit is E0H. Ans: JB 0E0H, LX vi. Save 23H in the location pointed by SP-register. Ans: MOV R0, SP MOV @R0, #23H vii. DPH and DPL are loaded with the contents of the R1 and R0 registers of Bank-1. Now load A-

register with the content of memory location pointed by DPTR. Ans: MOV DPH, R1 MOV DPL, R0

Chapter - 8

489

MOVX A, @DPTR viii. Use R0 and R1 as pointers and then move 5-byte data from the space (30H – 34H) into the space

(40H – 44H). Ans: MOV R0, #2FH MOV R1, #3FH MOV R2, #05H AGN: INC R0 INC R1 MOV A, @R0 MOV @R1, A DJNZ R2, AGN ix. [1+2 {3+4 (5+6)}] Ans: MOV A, #05H ADD A, #06H

MOV B, #04H MUL AB ; result in BA ADD A, #03H INC B

ADD A, A INC B

ADD A, #-01H INC B

x. for (x=5; x !=0; - - x) y = y+1; Ans: MOV R2, #05H GN1: ADD y, #01H DJNZ R2, AGN1

15 Answer to the following questions as requested:

i. Write ASM code for the following pseudo code: ((45H)) + ((95H)) → C600H

Ans: MOV A, 45H MOV R0, #95H ADD A, @R0 MOV DPTR, #0C600H MOVX @DPTR, A

ii. Write ASM code to put LH onto A6-bit of A-register. iii. Ans: SETB 0E6H iii. Write ASM code for the following operations:

A B 45H 67H 91H Ans: MOV B, A MOV 45H, A MOV 67H, 45H MOV R1, #91H MOV @R1, 67H

iv. Write ASM codes to exchange information between P2.0 and P3.0. v. Ans: MOV C, P2.0

MOV P3.0, C v. Given: A= 23H, (98H) = 45H, R0 = 98H. What will be the value of B-register after the

execution of the following instructions?

Problems and Solutions

490

ADD A, #0DBH ADD A, #02H ADDC A, @R0 MOV B, A

vi. Given that: A= 12H, DPTR = C400H, (C412H) = 34H. What will be content of A-register after the execution of the following instruction?

MOVC A, @A+DPTR vii. Write ASM codes for the subroutine BCD2UP to convert the BCD numbers of the following

table into upBCD numbers of the form 0X and save them in the table indicated.

viii. Write ASM codes to perform the following operations:

1234H x 0AH + 09H → R7, R6 ix. Write codes to perform the following operations:

1234 + 5678 → R7, R6 x. Write 8051 codes for the following loop structure. x = 2; while (x !=0) y = y + 3;

16 Refer to the diagram of Fig-8.15 of the text and answer to the following questions: i. Write down the conditions that must be fulfilled so that the MCU is automatically interrupted at

the falling edge of the interrupt signal. ii. Write 8051 ASM codes so that the MCU can serve the ISURINT0 by pulling the IE0-bit of the

TCON-register. iii. Which bit of the IE-register will prevent the MCU from being interrupted by an interrupt signal

arriving on its INT1/-pin?

17 Refer to Section-8.6 (d) for the working principles of Counter-0 of the 8051. Based on this description, write 8051 ASM codes so that the MCU is interrupted for every 17 pulses arriving at its Co-pin.

18 Read the data sheet of the Real Time Clock chip DS12C887 and then answer to the following questions: i. Explain the meaning of: The RTC uses multiplexed bus for pin efficiency. ii. Draw RAM space map and shows its division for Clock Registers, Control Registers and GPR. iii. Explain the purpose of the Protection Circuitry that is present in the RTC chip. iv. Write down the functions that are provided by the RTC. a. Time-of-day Clock

b. Alarm c. One Hundred Year Calendar d. Programmable Interrupt e. Square Wave Generator f. 15 Clock and Control Registers g. 113 bytes nonvolatile static RAM

v. Write down the Intel version of the following pins of the RTC. a. AS (Address Strobe)

534bxBCD Table upBCD Table

98

76

54

BCD2UP

0908

07

0605

0458

59

5A

IRAM ERAMBCD uBCD

C590

C591

C592C593

C594

C595

Chapter - 8

491

b. R-W/ (Read/ Write) c. DS (data Strobe)

vi. Why do we need to connect an external pull up resistor (5k) at the IRQ/-pin? vii. At what level of Vcc, the internal lithium energy source supplies power to the RTC? Ans: < 3V viii. Explain the relation of Vcc, the lithium energy source and the accessibility of RTC.

Ans: a. The RTC retains all the internal data for 10 years even at the absence of external power.

b. When Vcc > 4.25V, the RTC becomes accessible after 200mS, provided that the internal oscillator is running.

c. When Vcc falls below 4.25V, the chip select (CS/) pin is internally forced to an inactive level regardless of the value of CS/-pin at its input. The DS12C887 is, therefore write protected.

ix. Draw a diagram to indicate the operational condition of the RTC for which the IRQ/-pin becomes active.

19 Given below a data structure relating to Product Rate Acquisition, Storage, Conversion and Display. The

8279 controllers drive the display devices. Read it carefully and then answer to the questions that follow:

i. The following program codes can be used to acquire the scan codes for the digits 2 4 7 5 that

have been pressed down in the keyboard. Draw flow chart for these codes. START: NOP L1: MOV SP, #70H ; initialize SP, Bank. Counter, pointer for TSC and 8279 MOV PSW, #00H MOV R7, #04H MOV R0, #57H MOV DPTR, #CR MOV A, #Cbyte1 MOVX @DPTR, A MOV A, #Cbyte2 MOVX @DPTR, A L2: MOVX A, @DPTR JNB A0, L2 ; closed key not found L3: MOV A, #Cbyte3 ; command to move scode from KFIFO to DR

IRQIRQF

AIE (Alarm Interrupt Enable) set by User

AF (Alarm Interrupt Flag) set by Event

PIE (Periodic Interrupt Enable) set by USer

PF ( Periodic Interrupt Flag) set by Event

UIE (Update Ended Interrupt Enable) set by User

UF (Update Ended Interrupt) set by Event

Rtclk : GM : 09 - 2008

534b:22-07-08:GM

0

1 2 3

5 64

7 8 9

RSRE

IRAM SC

SC2

Rate : 24.75

2 4 7 5

58

595A

5B

TSC

SC5

SC7

SC4

IRAM CC

CC230

3132

33 CC5

CC7

CC4

DRAM CC

CC200

0102

03 CC5

CC7

CC4

TCCA TCCB

CCXDRAMSC2CC

DP0 DP3

2 4. 7 5

CC7SDDKBD

Problems and Solutions

492

MOVX @DPTR, A L4: MOV DPTR, #DR ; read scan code and save in TCCA MOVX A, @DPTR INC R0 MOV @R0, A L5: DJNZ R7, L2 ; still more digits to read from keyboard L6: LJMP L6

ii. Assume that a LUT table like 07XX can be used to convert the scan codes of Table-TSC into corresponding CC codes of Table-TCCA. The 07XX refers to ROM locations, which contains the CC-code for the scan codes designated as XX in the address 07XX. Now, write 8051 ASM codes to convert the codes of TSC into CC codes and save them in TCCA.

iii. Write 8051 ASM codes to transfer the codes of Table-TCCA into the Table-TCCB. iv. Assume that Cbyte4=63H allows reading the content of DRAM3. Now write 8051 ASM codes to

place decimal point at DP1 position of the CC7SDD device.

20 Read the following diagram carefully and then answer to the questions that follow: Not that the 8279 controllers drive the keyboard and the display unit.

(a) Draw flow chart to check that a key has been pressed down on the keyboard and if the pressed

down key is the only and only E-key then show _ _ . _ _ at the on the CC7SDD unit. (b) Assume that the display device already shows 2475. Now, write 8051 ASM codes to place

decimal point at DPD position so that the display appears as: 24.75 (c) Explain the role of the software switches SW1 and SW2 in guiding the MCU for executing the

command key E (for Data Entry Command) and printing the data digits 0 – 9. (d) The following mixed-codes read n-packets of Scan Codes from the keypad for the n-number of

digits. Read these codes and then draw the RAM table that holds the scan codes. L1: MOV R2, #05H #C400H → DPTR L1: if (pressed down key not found) Goto L1 L2: Read Scan Code and save into A-register L3: MOVX @DPTR, A L4: DJNZ R2, L6 L5: End L6: INC DPTR Goto L1 (e) Write 8051 ASM codes to transfer the contents of table TCCA into table of TCCB.

21 Draw data structure, pseudo code, flow chart and 8051 ASM codes to add two hexadecimal numbers and show the result at DPC- DPF positions of the display unit of MicroTalk-8051 trainer. Assume that the numbers are located into ERAM locations C700H and C701H.

22 Draw Top-down Design tree for an 8051-based Digital Weighing Machine.

23 Draw a Conceptual Hardware Block Diagram for an 8051-based Digital Weighing Machine.

534bx:22-07-08:GM

0

1 2 3

5 64

7 8 9

RSRE

IRAM SC

SC2

Rate : 24.75

2 4 7 5

58

595A

5B

TSC

SC5

SC7

SC4

IRAM CC

CC230

3132

33 CC5

CC7

CC4

DRAM CC

CC200

0102

03 CC5

CC7

CC4

TCCA TCCB

CCXDRAMSC2CC

DPC DPF

2 4. 7 5

CC7SDDKBD

Command Execution : Show _ _ . _ _ on the Rate Filed for the E (Rate Entry) Command

E

DPC -------- DPF

- - . - -

SW1

SW2

Chapter - 8

493

24 Write down the names and purposes of various Hardware, Software and File names that are required to build a microcontroller-based system.

25 Given below a frame of an Intel-Hex formatted file. Break it into its various fields and explain their

meanings.

:05C1950090A500F0225E

26 Manually convert the following text file into an Intel-Hex formatted file.

C500 - 74 00 90 C2 23 27 Explain with example, the difference between a BINary file and a TEXT file. Keeping in mind that an

Intel-Hex formatted file is a TEXT file, then write the storage bit pattern for the following frame:

:02C630001200F8 28 Read the following Block Diagram for the MicroTalk-8051 based Digital weighing Machine and then

answer to the questions that follow:

(a) Draw electrical equivalent circuit for the load cell and then briefly explain its working principle.

Load Cell

0 - 20kg

20mV

AMPL

x100 2V Ain

ADC Weight

Strobe

101

4433

KBC

1/28279 : U19

CS/

BB

Keyboard

MPU

8051 : U2

Data

BB

2/28279 : U19

DPC

Cost(Tk)

Rate(Tk)

Wt(Kg)

646f:GM:06-04-08

Row

Col

IRQ

Pan

Q0Q1Q2Q3

DS4DS3DS2DS1

INT0/

B

3

47 8 9

65421 3

RS0 RE

DP6 DPA

DPC DPF

DP5DP0

P1(90H)

P10

P17

2000H – 2100H

0000H -C000H -

ROM RAM

BB

test.asmMIDE-51ASM51

MIDE-51.buildASM51

test.lst

test.hex

51TXCOM1(GM)

IBMPC

MicroTalk-8051(GM)RAM

TOP51EPW512 TOP51test.bin

MCU

TOP51BTA (GM) test.txt

Code EEPROM only

PSPKIT (GM)

1501:GM:08 - 08

Code EEPROMData EEPROM

MCU

COM1

Problems and Solutions

494

(b) Draw schematic diagram for the discrete components based Instrumentation Amplifier. Deduce expression for the gain of an instrumentation amplifier.

(c) Draw Bus-structure diagram for the ADC4433 and then briefly describe its working principle. (d) Draw signal conversion timing diagram for the ADC4433. (e) Write 8051 ASM codes to poll the DS-bits and then acquire upBCD data for the upper two-digits

of the weight. Pack them together to make BCD and save into R6 register.

29 Refer to the diagram of Fig-8.21 for the design of an 8051-based Digital Weighing machine. Draw schematic diagram for its various modules as requested.

i. The DWM will be a copy-protected product. It will not use any external code memory. The crystal clock frequency is 12MHz. A 10uF-5K network will provide the RST-signal for the MCU. Draw schematic diagram (without the pin numbers) for the MCU subsystem.

ii. Draw schematic diagram for the 4-to-10 multiplexer using 2x74LS138 decoders. iii. Consider that the power buffers (PWR BUF) for the CA7SD devices are of open collector NPN

transistors. Draw schematic diagram showing all the circuit elements for the segment-a of the device DP0. Your schematic should start from y0/-pin of 4-to-16 multiplexer and is terminated at P00-pin of the MCU.

iv. Write 8051 codes to display the characters 2 3 on the devices DP0 and DP1. v. Draw a schematic diagram (no need to show the pin numbers) for the keyboard.

30 Refer to Fig- 8.11 for the internal structure of the built-in serial port of the 8051 microcontroller. Read it carefully and then answer to the following questions:

(a) Write down the names of the parameters that must be set during initialization so that the MCU can reliably exchange serial data with IBMPC.

(b) Write down the functions of the various bits of the SCON and IE registers for the serial port operation of the 8051 MCU.

(c) Assume that the serial port has been initialized. Now, write 8051 codes to read the content of the Rx Buffer by polling the RI-bit.

(d) The diagram shows that the MCU goes to the same ISR location (0023H) whether the interrupting signal is coming from the Rx Buffer or the Tx Buffer. Write the 8051 codes by which this conflicting situation is practically resolved.

(e) The 11.0592MHz is a good frequency for generating desired baud rate without any error. But, while considering the divide-by-12 circuit within the oscillator part of the MCU, the 11.0592MHz crystal becomes a hindrance to get a solid frequency of 1MHz, which we can easily obtain by using 12MHz crystal. 1MHz frequency may be considered as a base frequency to generate accurate timing functions for some other purposes in the system. Calculate the error that will yield in the baud rate if using 12MHz. given that:

Bd = ((20)/32) X ((Crystal Frequency)/(12*(0100H – FAH)))

31 Refer to Fig-8.24 and answer to the following questions: (a) Draw Flow Chart to describe the logic for the design of the overall Control Program of the DWM.

Consider that the ‘Product Rate’ is acquirable by ISRINT0. (b) Write Control Structure for converting 4-digit BCD number into equivalent BINary number by

Counting Method (slow method). (c) Derive Horner Expression for converting n-digit BCD number into equivalent BINary number

(fast method). (d) Write 8051 assembly codes using Horner Rule to convert the upper two-byte data of table

BCCDWT into data of table BINWT. Given that the subroutine EVAHB evaluates the expression: IPBIN x 0AH + dx.

(e) Write 8051 ASM codes using Horner Rule to convert the data of table BINCOST into the data of BCDCOST. Given that the subroutine EVAHD evaluates the expression: IPBCD x 02 + bx.

32 Explain the theory of performing Data Read/Write Operations with Internal Data EEPROM of 89S8252.

Chapter - 8

495

89S8252 MCU ADE7756 EMC

SCKDOUTDIN

SCK(P17)MISO(P16)MOSI(P15)

876

181920

RST/5P14(SS/) 1 +5V32

AVddAVdd

REFIN/REFOUT 9+

C147uF

C20.1

8AGND10DGND

Y13.58MHz

CLKOUT

CLKIN

16

15

V2PV2N

76 Vol Channel

V1PV1N

45 Curr Channel

0V CS/17SAG/IRQ/ZXCFNC

867 : GM : 03-05

Looking at Fig-8.4, we find that the AT89S8252 MCU contains 2K Data EEPROM along with security bit. The DATA EEPROM occupies the space: 0000H – 07FFH. A user may store ‘System Confidential Data’ inside the data EEPROM and then set the security bit. Once the security bit is set, there is no way left to access the content of the data EEPROM using the ‘Conventional Programmer’ or the ‘ISP Port’. This feature of the 89S8252 allows it for building ‘Prepaid Energy Meter’ and the similar products.

There are three ways of writing data inside the data EEPROM and these are:

1. Using conventional ROM Programmer putting the MCU OFF-line (not running). 2. Using Program Instructions of the MCU itself keeping the MCU ON-line (running). 3. Using ISP Port of the MCU keeping the chip OFF-line.

Data Structure:

Figure-5.18: Data Structure for the Process of Writing into EEPROM of 89S8252 MCU

Working Principles: Let us open the program c:\ckit\p522a.asm and we find that the writing process into the EEPROM of the 89S8252 MCU involves the following steps:

1. The data 12H, 34H and 56H are written into RAM locations 08H – 0AH for matter of convenience. However, the data could be directly written into the EEPROM.

2. The rules for performing data read/write operations into the EEPROM of the MCU are clearly stated into the data sheets of the MCU. We follow the data sheets and copy the contents of RAM locations 08H-0AH into EEPROM locations 00EAH-00ECH.

3. The 3-byte data are read back from the EEPROM and are saved into RAM locations EAH-ECH. 4. The content of the locations EAH-ECH are displayed on the LCD to visualize that the data have

been correctly written/retrieved into/from of the EEPROM of the MCU.

33 Explain the theory of SPI Port Programming and Operation of 89S8252 MCU The four port pins (P1.4-P1.7) of the 89S8252 microcontroller could be configured to operate as a ‘High Speed Synchronous Serial Peripheral Interface Port (SPI Port)’ to exchange data with compatible devices ike: i. Another 89S8252 ii. AT25040 Serial EEPROM iii. ADE7756 Energy Measurement Chip (EMC)

34 Explain ISP Port Programming Procedures of 89S51 MCU

08

09

0A

12H

34H

56H

Immediate Data RAM Locations EEPROM Locations

00EA

00EB

00EC

RAM Locations

EA

EB

EC

LCD

Write:12,34,56

Read: 12,34,56

1201:GM:03-06

Problems and Solutions

496

A: The ISP Concept: The S-series (AT89S51, AT89S52, AT89S8252, AT90S2313, AT9085S15) microcontrollers of Atmel contains EEPROM for the storage of program codes and data. To change code/data within the EEPROM of the MCU, it is removed from the holding instrument and then a parallel programming mode ROM programmer is used to fuse the code/data inside the EEPROM. Removal of the MCU from the holding instrument and put it back is a time consuming procedure. For example, the current flat fare for the initial 2-km distance traveled by a CNG-Cab is Tk 12.00. Now, the authority has changed it to Tk13.00. To update the data, the MCU should be removed from the Taximeter, fuse the new data and put it back.

In order to make a quick update of the code/data, the S-series microcontrollers of the Atmel contain a ‘Serial Programming Interface’ circuit, which allows Erasing, Reading, Writing and Locking MCU without removing it from the instrument. This validates the name ‘In System Programming’.

The ISP programming is a serial mode programming. The trick is the inclusion of a 3-pin ‘Serial Programming Interface’. The author of this book has implemented the ISP programming algorithm based on LPT-IBMPC-C environment. The hardware schematic is depicted in below. The driving software has been listed below.

The 89S51 chip automatically configures its P1.5, P1.6 and P1.7 port pins as ‘ISP Programming Interface’ whenever its RST-pin is pulled to Logic-H state. The ISP-port definitions are as follows: Port -Pin Signal Name Function P1.5 (6) MOSI : Master Out Slave In Data enters serially into MCU in synchronism with SCK P1.6 (7) MISO : Master In Slave Out Data leaves serially from MCU in synchronism with SCK P1.7 (8) SCK : Serial Clock Clock to drive data into MCU and out of MCU. B: The Hardware Setup and Operation using LPT Port of IBMPC

14

25

24

23

22

`

15

16

17

18

19

20

21`

1

2

3

4

5

6

7

8

9

10

11

12

13

9

LPTCR (037Ah)

CR0 RST

U1: 40 Pin ZIF (89S51)

LPTSR (0379h)

SR4

LPTDR (0378h)

DB7

CR2

COM

LPT Port

MOSI (P15)MISO (P16)SCK (P16)

678

Data In

Data Out

Clock In

GND20Vcc40+5V

XT2

XT1

18

19

Y111.0592MHz

P1010V

D1

+

1001x: GM : 02-05

Chapter - 8

497

C: Serial Programming Instruction Set of 89S51 Microcontroller

Instruction Format Instruction Byte1 Byte2 Byte3 Byte4

Operation

Prog. Enable

1010 1100 0101 0011 xxxx xxxx xxxx xxxx 0110 1001 (on MISO)

Enables Serial Program When RST is at LH

Chip Erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase Code Memory Read (Byte) 1010 1100 xxxx A11-A8 A7 - A0 D7 – D0 (on MISO) Data read byte by byte Write (Byte) 1010 1100 1110 A11-A8 A7 – A0 D7 – D0 (MOSI) Data write byte by byte Lock Bits 1010 1100 1110 00B1B2 xxxx xxxx xxxx xxxx Write lock bits

In this section, we shall discuss the ‘Serial Programming Mode Instruction Set’ to allow the readers developing the ‘Driving Software’ for their own.

Programming Enable Operation 1. Pull the RST–pin of the MCU to LH by sending LL to CR0. Assert Logic-L on CR2-pin. 2. Manipulate Byte-1 (Byte-2) in such a way so that the data can be transferred over the DB7 pin bit-by-

bit. The MS-bit would transmit first. 3. Place the MS-bit of Byte-1 on DB7-pin. Assert a pulse (LH-wait-LL) on CR2-pin. At the rising edge of

this signal, the MS-bit enters into the MCU. At the same time, a data bit also enters to the IBMPC over the SR4-pin, which is not considerable at this time.

4. In a way similar to Step-2, 3 send byte-2 to the MCU. Ignore data that arrives to PC via SR4. 5. In a way similar to Step-2. 3 send byte-3 (00H) to the MCU. Ignore data that arrives to PC. 6. Send byte-4 (00H) to MCU. This time, we must not ignore the data that arrives to the PC over the SR4-

pin. After making LH on the CR2-pin, immediately catch the return bit from the SR4-pin and save it in a buffer. And then assert Logic-L to CR2-pin.

7. At the end of catching all the 8-bits from the SR4-pin, merge them together to see that the data byte received from the MCU is 69H.

8. To read data from a particular location of the MCU, the user must send a data byte 00H during byte-4 command. As the byte-4 enters into MCU bit-by-bit, the data from the requested memory locations also enters bit-by-bit to the PC over the SR4-pin. The user must merge the bits to obtain the data byte.

D: C-based Routine to Drive the ISP Port of 89S51

#include <stdio.h> #include <conio.h> #define LPTDR 0x0378 #define LPTCR 0X037A #define LPTSR 0x0379 unsigned long hexmcusadr, hexmcueadr; unsigned char mcusadr[5] = {15,15,15,15,15}; unsigned char mcueadr[5] = {15,15,15,15,15}; unsigned char ch1, ch2, ch3, i=0; union buff { unsigned long size; unsigned char ch [4]; } y; unsigned char destfile[30]; unsigned char sourcefile[30]; unsigned char send2S51(unsigned char); unsigned char x, ch, byte;

Problems and Solutions

498

unsigned char rcvdbyte; unsigned char rcvdbit[9];// = {0x90, 0x80, 0x90, 0x80, 0x90, 0x80, 0x90, 0x80}; void buildbyte (void); //10101010=AA void wr28951(void); void rdf8951(void); void erase8951(void); void lock8951(void); void chklock(void); void main() { clrscr(); // programming enable outport(0x037A,0x01); // reset is done delay(100); //getch(); outportb(0x037A, 0x00); printf("Press any Key to Start......!\n"); getch(); byte = 0xAC; // programming enable send2S51(byte); byte = 0x53; send2S51(byte); byte = 0x00; send2S51(byte); byte = 0x00; send2S51(byte); buildbyte(); printf("%x \n", x); //getch(); if(x != 0x69) { printf("\nSlave MCU is not Accessible.......!\n"); printf("Press any Key to Exit........!\n"); getch(); exit(1); } printf("The MCU is Found.....!\n"); printf("You wish to Read from 89S51......?");

if(getche() == ('Y'|'y')) { putchar('\n'); goto L1; }

printf("\nYou wish to Write into 89S51.....?");

if(getche() == ('Y'|'y')) { putchar('\n'); goto L2; } printf("\nYou wish to Lock the 89S51.....?");

Chapter - 8

499

if(getche() == ('Y'|'y'))

{ putchar('\n'); goto LX; }

printf("\nYou wish to Erase the 89s51......?");

if(getche() == ('Y'|'y')) { putchar('\n'); goto L3; } printf("\nYou wish to Execute the Downloaded Program.....?");

if(getche()==('Y'|'y')) { putchar('\n'); printf("\nRunning the Downloaed Program........!"); outportb(LPTCR, 0x01); delay(50); getch(); exit(0); } exit(0); LX: lock8951(); printf("\n locking is done......!\n"); printf("\nPress any key to return to DOS........!"); getch(); exit(0); L1: rdf8951(); printf("\nReading is Done Successfully.......!\n"); printf("\The Binary Data is saved in the File: "); //d:\\pspkit\\51.bin"); puts(destfile); printf("\nPress any Key to Return to DOS...!"); getch(); exit(0); L2: wr28951(); printf("\nWriting is Done Successfully.......!\n"); printf("\nPress any Key to Return to DOS.....!\n"); getch(); exit(0); L3: erase8951(); printf("\nErasing is Complete........!"); printf("\nPress any Kry to Return to DOS.........!"); getch(); exit(0); } unsigned char send2S51(unsigned char byte) {

Problems and Solutions

500

unsigned int i;//=0x08; unsigned int j=0x00; for (i=0; i<8; i++) { outportb(LPTDR, byte); //BYTE=AC=10101100 //delay(1); outportb(LPTCR, 0x04); //assert rising edge of SCLK //delay(1); rcvdbit[j] = inportb(LPTSR); // yes this line must be here outportb(LPTCR, 0x00); //rcvdbit[j] = inportb(LPTSR); // not here byte = byte<<0x01; j++; } return(0); } void buildbyte(void) { //printf("\nHellow.Building Byte.!\n"); //getch(); rcvdbit[0]=(rcvdbit[0]<<0x03)&0x80; // 10010000 = 10000000*/ //printf("%x ", rcvdbit[0]); //getch(); rcvdbit[1]=(rcvdbit[1]<<0x02)&0x40; // 0 rcvdbit[2]=(rcvdbit[2]<<0x01)&0x20; rcvdbit[3]=(rcvdbit[3])&0x10; rcvdbit[4]=(rcvdbit[4]>>0x01)&0x08; //printf("%x ", rcvdbit[4]); //getch(); rcvdbit[5]=(rcvdbit[5]>>0x02)&0x04; rcvdbit[6]=(rcvdbit[6]>>0x03)&0x02; rcvdbit[7]=(rcvdbit[7]>>0x04)&0x01; rcvdbit[0] = (rcvdbit[0]|rcvdbit[1])|(rcvdbit[2]|rcvdbit[3]) ; rcvdbit[0] = rcvdbit[0]|(rcvdbit[4]|rcvdbit[5])|(rcvdbit[6]|rcvdbit[7]); x = rcvdbit[0]; } void rdf8951(void) { FILE *fp; unsigned char databufr[4096]; unsigned int r; char destfile[30]; union adr { unsigned int address; unsigned char array[2]; } count;

Chapter - 8

501

LJ: printf("Enter MCU Starting Address in 4-Digit Hex: "); gets(mcusadr); // 41 42 43 44 : A B C D 31 32 33 34 : 1 2 3 4 strupr(mcusadr); // making all characters uppercase printf("\nEnter MCU End Address in 4-Digit Hex: "); gets(mcueadr); // 41 42 43 44 : A B C D 31 32 33 34 : 1 2 3 4 strupr(mcueadr); // making upper case

for (i=0; i<4; i++)

{ if ((mcusadr[i]>>04)==04) mcusadr[i] = (mcusadr[i] + 0x09); // 41 is being made 4A ... else ; } ch1 = (mcusadr[0]<<0x04)|(mcusadr[1]&0x0F); ch2 = (mcusadr[2]<<0x04)|(mcusadr[3]&0x0F); y.ch[3] = 0x00; y.ch[2] = 0x00; y.ch[1] = ch1; y.ch[0] = ch2; hexmcusadr = y.size; count.address = hexmcusadr; printf("\n%x ", hexmcusadr); for (i=0; i<4; i++) { if ((mcueadr[i]>>04)==04) mcueadr[i] = (mcueadr[i] + 0x09); else ; } ch1 = (mcueadr[0]<<0x04)|(mcueadr[1]&0x0F); ch2 = (mcueadr[2]<<0x04)|(mcueadr[3]&0x0F); y.ch[3] = 0x00; y.ch[2] = 0x00; y.ch[1] = ch1; y.ch[0] = ch2; hexmcueadr = y.size; printf("\n%x\n", hexmcueadr); printf("\nEnter Path and File Name into Which Data to be Saved...!\n"); gets(destfile); printf("Please Wait.....!"); fp=fopen(destfile, "wb"); //(d:\\MASM510\\51.bin", "wb"); if(fp==0x00) { printf("File Can't be Created/Opened........!\n"); getch(); exit(2); } //printf("%x ", count.array[0]); //getch();

Problems and Solutions

502

for (r=0; r<(hexmcueadr+1); r++) { // reading from 89S51 byte = 0x20; send2S51(byte); delay(20); byte = count.array[1]; // address upper byte send2S51(byte); delay(20); byte=count.array[0];//albyte = 0x00; // address lower byte send2S51(byte);//count.array[0]); delay(20); byte=0x00; //data byte send2S51(byte); delay(20); buildbyte(); databufr[r]=x; //printf("%x ", x); // getch(); (count.address)++; delay(20); } for (r=0; r<4096; r++) putc(databufr[r], fp); fclose(fp); outportb(LPTCR, 0x01); } void wr28951(void) { FILE *ifp; unsigned char databuf[4096]; unsigned int r; union adr { unsigned int address; unsigned char array[2]; } count; LJ1: count.address=0x0000; printf("Enter ROM Starting Address in 4-Digit Hex: "); gets(mcusadr); // 41 42 43 44 : A B C D 31 32 33 34 : 1 2 3 4 if (mcusadr[4] !=0x00) { clrscr(); goto L2; } strupr(mcusadr); // making all characters uppercase L2: printf("\nEnter ROM End Address in 4-Digit Hex: ");

gets(mcueadr); // 41 42 43 44 : A B C D 31 32 33 34 : 1 2 3 4

Chapter - 8

503

if (mcueadr[4] !=0x00)

{ clrscr(); goto L2; } strupr(mcusadr); // making upper case for (i=0; i<4; i++) { if ((mcusadr[i]>>04)==04) mcusadr[i] = (mcusadr[i] + 0x09); // 41 is being made 4A ... else ; } ch1 = (mcusadr[0]<<0x04)|(mcusadr[1]&0x0F); ch2 = (mcusadr[2]<<0x04)|(mcusadr[3]&0x0F); y.ch[3] = 0x00; y.ch[2] = 0x00; y.ch[1] = ch1; y.ch[0] = ch2; hexmcusadr = y.size; printf("\n%x ", hexmcusadr); for (i=0; i<4; i++) { if ((mcueadr[i]>>04)==04) mcueadr[i] = (mcueadr[i] + 0x09); else ; } ch1 = (mcueadr[0]<<0x04)|(mcueadr[1]&0x0F); ch2 = (mcueadr[2]<<0x04)|(mcueadr[3]&0x0F); y.ch[3] = 0x00; y.ch[2] = 0x00; y.ch[1] = ch1; y.ch[0] = ch2; hexmcueadr = y.size; printf("\n%x ", hexmcueadr); printf("\nEnetr Path and File Name from Which Data to be Written...!\n"); gets(sourcefile); ifp=fopen(sourcefile, "r+"); //("D:\\EPROM\\testp10.bin", "r+"); if(ifp==0x00) { printf("File Can't be Opened........!\n"); getch(); exit(2); } printf("\nPlease Wait.......!"); for(r=0; r<(hexmcueadr+1); r++) { ch = getc(ifp); databuf[r] = ch; }

Problems and Solutions

504

//printf("%x ", databuf[0]); //getch(); for (r=0x00; r<(hexmcueadr+1); r++) { // writing into 89S51 byte = 0x40; send2S51(byte); byte=count.array[1]; // address upper byte send2S51(byte); byte=count.array[0];//albyte = 0x00; // address lower byte send2S51(byte); //data byte send2S51(databuf[r]); delay(1); // check if the last byte has been successgully written (count.address)++; } fclose(ifp); outportb(LPTCR, 0X01); // the MCU is in RUN Mode } void erase8951(void) { byte = 0xAC; send2S51(byte); byte=0x80; // address upper byte send2S51(byte); byte=0x00;//albyte = 0x00; // address lower byte send2S51(byte); //data byte byte=0x00; send2S51(byte); delay(200); outportb(LPTCR, 0X01); // the MCU is run } void lock8951(void) { byte = 0xAC; send2S51(byte); byte=0xE0; // address upper byte send2S51(byte); byte=0x00;//albyte = 0x00; // address lower byte send2S51(byte); //data byte byte=0x00; send2S51(byte); delay (200); byte = 0xAC; send2S51(byte);

Chapter - 8

505

byte=0xE1; // address upper byte send2S51(byte); byte=0x00;//albyte = 0x00; // address lower byte send2S51(byte); //data byte byte=0x00; send2S51(byte); delay(200); byte = 0xAC; send2S51(byte); byte=0xE2; // address upper byte send2S51(byte); byte=0x00;//albyte = 0x00; // address lower byte send2S51(byte); //data byte byte=0x00; send2S51(byte); delay(200); byte = 0xAC; send2S51(byte); byte=0xE3; // address upper byte send2S51(byte); byte=0x00;//albyte = 0x00; // address lower byte send2S51(byte); //data byte byte=0x00; send2S51(byte); delay(200); outportb(LPTCR, 0X01); // the MCU is run } void chklock(void) { byte = 0x24; send2S51(byte); byte=0x00; // address upper byte send2S51(byte); byte=0x00;//albyte = 0x00; // address lower byte send2S51(byte); //data byte byte=0x00; send2S51(byte); delay (200); buildbyte(); }

Problems and Solutions

506

KRST/K60 F1

1 2

R61k

K12 31 2

D7

D0

U2A

74LS123

1415

123

13

4

CEXT

REXT

/CEX

T

ABCLR

Q

Q+5V

U3A74LS74

2

3

5

6

41

D

CLK

Q

QPRCL

VCC

Q3BC337

2

3

1

VCC

K62 F31 2

K51 E-EXA1 2

K52 F-FRW1 2

0V

k41 B-BKW1 2

Q3BC327

3

2

1

CS0/

D3

D6

K50 D-DOP1 2

K71 F51 2

R41k

C3 1uF

R11k

K10 11 2

U4 74LS244

2468

11131517

119

181614129753

1A11A21A31A42A12A22A32A4

1G2G

1Y11Y21Y31Y42Y12Y22Y32Y4

K40 A-AUT1 2

K21 51 2

R82k2

K70 F41 2

R21k

D5

K01 8-AR11 2

D1

Q2BC327

3

2

1

K00 01 2

K30 71 2

K20 41 2

+5V

D2

+5V

K32 91 2

K72 F61 2 VCC

Q1BC327

3

2

1

K02 01 2

U1

4532

101112131234

5

976

15

14

D0D1D2D3D4D5D6D7

EIN

Q0Q1Q2

EO

GS

R31k

R51k

K61 F21 2

K42 C-CHG1 2

R9 33k

K31 81 2

0V

R7 2k2

StatusK22 61 2

D4K11 2

1 2

C

RN18x1k

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