E5163

UNIT 3

MOS TRANSISTOR FABRICATION

OUTCOMES

By the end of the lecture, student should be able to :

• Explain the NMOS transistor fabrication process

sequence based on wafer cross-section diagram.

• State the number of masks needed for NMOS.

• State the number of masks needed P-well CMOS

transistor.

• Draw the physical structure of other CMOS transistors

: N-well, Twin-tub and Silicon on Insulator (SOI).

NMOS TRANSISTOR FABRICATION

PROSES SEQUENCE

• This set of steps proceeds through a simple, single-

layer metal MOS fabrication process (far simpler than

what is used today but illustrating the main mask

points).

• It’s start with a clean P-type silicon wafer (highly

polished on the top side) since we will be fabricating

an NMOS transistor.

NMOS TRANSISTOR FABRICATION

PROSES SEQUENCE

P-Type Silicon

Silicon Dioxide

Photoresist

Photomask

UV light

Figure 1: Start of fabrication (Mask 1: Diffusion Mask)

• Figure 1 showing the P-type silicon

wafer after a thick SiO2 layer has been

grown on the wafer.

• After that , a layer of photoresist has

been spread across the wafer surface.

• Also shown in Figure 1 is a

photomask above the silicon wafer,

blocking light from hitting the

photoresist.

• Photoresist can be either _______ or

________.

• In the case of a _______ photoresist,

the regions struck by light are

removed during development. For a

_______ photoresist, the regions not

struck by light are removed.

NMOS TRANSISTOR FABRICATION

PROSES SEQUENCE

Figure 2: Illustration of photoresist and patterning

• Figure 2 illustrates an example of the

role of the photomask in defining the

device structure.

• Development process leads to the

complete removal of the exposed

portions of the film (for positive

photoresists) or of the non-exposed

portions of the film (for negative

photoresists).

• Figure 2 also shows Hydrofluoric acid

(HF) used as etchant for etching the

SiO2 but will not etch silicon.

P-Type Silicon

Silicon Dioxide

Photoresist

Hydrofluoric Acid

NMOS TRANSISTOR FABRICATION

PROSES SEQUENCE

Figure 3: Thick oxide etched and gate oxide grown.

• In Figure 3, the etching

operation illustrated in Figure 2

has been completed and a very

thin layer of SiO2 grown.

• This is called the "gate oxide", a

very thin oxide relative to the

oxide grown earlier.

• That thin oxide film also adds to

the thicker oxide film but, since

they are both SiO2, this is not

shown.

Gate oxide

NMOS TRANSISTOR FABRICATION

PROSES SEQUENCE

Polysilicon

Figure 4: Polysilicon layer deposited. (Mask 2:

Gate Mask)

• In Figure 4, an additional layer has been

"grown," the polysilicon layer, covering the

entire wafer.

• Next, a photoresist film has been spread

onto the wafer.

• A photomask is again used. In this case, we

want the regions not struck by light are

removed. Therefore, _________ photoresist

is used.

• Development process used to remove

unnecessary photoresist.

• Using suitable ectant, all of the polysilicon

except for that in the center of the gate oxide

will be removed during the etching step that

follows development of the photoresist.

NMOS TRANSISTOR FABRICATION

PROSES SEQUENCE

Figure 5: Doping of the source and drain regions.

• The remaining polysilicon acts as a

conductor, namely the gate connection of the

MOSFET.

• In Doping process (ion implantation

technique is used), donor atoms are being

injected into the silicon to create the source

and drain regions. Where the donor atoms

strike the thick oxide, they are absorbed

within the oxide layer.

• Similarly, where the donor atoms strike the

polysilicon, they are absorbed by the

polysilicon layer (doping the polysilicon

heavily N-type).

• The source and drain regions are now

heavily doped N++ (the "++" indicating that

source/drain donor densities - typically 1018

cm-3 - are well above those found in the

substrate).

Ion beam (donor atons)

N++ Source N++ Drain

NMOS TRANSISTOR FABRICATION

PROSES SEQUENCE

Figure 5: Doping of the source and drain regions.

• Figure 6a illustrates the structure

after applying annealing process

to repair the silicon damaged

during the ion implantation step.

• The donors diffuse during this

process and now extend

somewhat under the gate,

ensuring proper operation of the

overall device.

N++ Source N++ Drain

Polysilicon gate contact

NMOS TRANSISTOR FABRICATION

PROSES SEQUENCE

Figure 6: Making metal contacts. (Mask 3: Contact

Mask)

• In Figure 6, additional silicon dioxide has

been deposited (not grown as before)

over the entire silicon wafer.

• A photoresist film has been spread.

• Using photomask, UV light is exposed

through a mask.

• Using development process,

unnecessary photoresist is removed.

• In etching process (plasma/dry etching

techniques), region that exposed to UV

light is removed allowing contact holes

to be created.

NMOS TRANSISTOR FABRICATION

PROSES SEQUENCE

Figure 7: Patterning of metal for connections:

(Mask 4: Metal Mask).

• Figure 7 shows the next and last mask

operation for this simple NMOS

fabrication process.

• An aluminum layer has been deposited

over the entire wafer

• The photoresist has been spread onto

the wafer.

• The photoresist is being exposed

through the metal mask (photomask) to

define the metal patterns.

• Through development and etching

process, unnecessary aluminium is

removed.

Aluminum

metal

NMOS TRANSISTOR FABRICATION

PROSES SEQUENCE

Figure 8: Silicon nitride protective layer

• The final step Figures 8, is to cover the

entire wafer with a silicon nitride

protective layer (preventing entry of

atoms such as sodium into the

structure). Since this covers the entire

wafer (including aluminum "pads" for

connecting the IC to the package pins), a

final mask (not shown here) must be

used to "clean" the nitride off the

bonding pads.

MASKS IN P-WELL CMOS TRANSISTOR

(CMOS INVERTER)

MASKS IN P-WELL CMOS TRANSISTOR

(CMOS INVERTER)

P-WELL MASK

MASKS IN P-WELL CMOS TRANSISTOR

(CMOS INVERTER)

ACTIVE MASK

MASKS IN P-WELL CMOS TRANSISTOR

(CMOS INVERTER)

POLY MASK

MASKS IN P-WELL CMOS TRANSISTOR

(CMOS INVERTER)

P+ MASK

MASKS IN P-WELL CMOS TRANSISTOR

(CMOS INVERTER)

N+ MASK

MASKS IN P-WELL CMOS TRANSISTOR

(CMOS INVERTER)

CONTACT MASK

MASKS IN P-WELL CMOS TRANSISTOR

(CMOS INVERTER)

METAL MASK

CMOS TRANSISTOR USING P-WELL

• The substrate is n-type.

• The NMOS transistor is built in a p-type well

within the n-substrate.

• The PMOS transistor is built directly on the

n-substrate.

CMOS TRANSISTOR USING N-WELL

• The substrate is p-type.

• The PMOS transistor is built in a n-type well

within the p-substrate.

• The NMOS transistor is built directly on the

p-substrate.

CMOS TRANSISTOR USING TWIN-TUB

• Both an n-well and a p-well are

manufactured on a lightly doped n-

substrate.

CMOS TRANSISTOR USING SOI

(silicon on insulator)

• SOI allows the creation of independent,

completely isolated nMOS and pMOS

transistors virtually side-by-side on an

insulating substrate.

OUTCOMES

By the end of the lecture, student should be able to :

1. Explain the two problems that exist in CMOS

transistor operation:

• Latch up

• Parasitic capacitance

2. Discuss the origin and their effect on circuit operation.

3. Compare the 4 technologies in terms of circuit

performance due to latch up and parasitic

capacitance.

LATCH UP

• Definition:

Latch up pertains to a failure mechanism where a

parasitic silicon controlled rectifier (SCR) is

inadvertently created within a circuit, causing a high

amount of current to continuously flow through it once

it is accidentally triggered or turned on. Depending on

the circuits involved, the amount of current flow

produced by this mechanism can be large enough to

result in permanent destruction of the device due to

electrical overstress (EOS).

LATCH UP

Effect:

1. CMOS transistor not functioning

properly.

2. If the transistor gain and

resistance increase continuously,

latch-up current can permanently

damage or destroying junctions.

Therefore, the transistor can’t be

use.

LATCH UP

Prevention:

1. Latch up-resistant design where a layer

of insulating oxide (called a trench)

surrounds both the NMOS and the

PMOS transistors. This breaks the

parasitic SCR structure between these

transistors.

LATCH UP

Prevention:

2. Reduce the well and substrate resistances

will producing lower voltage drops:

• Higher substrate doping level.

• Low resistance contact to GND

• Guard rings around p-well or n-well.

LATCH UP

Prevention:

3. Move n well and n+ farther apart.

LATCH UP

Prevention:

4. Latch up Protection Technology circuit.

When a latch up is detected, the LPT circuit

shuts down the chip and holds it powered-

down for a preset time.

PARASITIC CAPACITANCE

• Definition:

parasitic capacitance is an unavoidable and usually

unwanted capacitance that exists between the parts of

an electronic component or circuit simply because of

their proximity to each other.

All actual circuit elements such as inductors, diodes,

and transistors have internal capacitance, which can

cause their behavior to depart from that of 'ideal'

circuit elements.

PARASITIC CAPACITANCE

Types of capacitance:

• Junction capacitance

– CBDSW, CBDJ and

CBSSW, CBSJ

• Overlap capacitance

– CGSOV and CGDOV

• Gate capacitance –

CGS , CGD and CGB

DIFFERENCES BETWEEN 4 TECHNOLOGIES

CMOS

TECHOLOGYADVANTAGES DISADVANTAGES

CMOS P WELL

• Using low cost

equipment.

• Easy to fabricate.

• Latch up problem arise.

• Parasitic capacitance

higher due to no insulator.

CMOS N WELL

• Using low cost

equipment.

• Easy to fabricate.

• Latch up problem arise.

• Parasitic capacitance

higher due to no insulator.

CMOS TWIN

TUB

• Reliability higher due to

lower in parasitic

capacitance.

• Complex in fabrication due

to 2 well to be built.

SOI

• No latch up

• Smaller parasitic

capacitance

• Using high cost equipment.