chap 2.4 - instruction representation jen-chang liu, spring 2006 adapted from cs61c
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TRANSCRIPT
Chap 2.4 - Instruction Representation
Jen-Chang Liu, Spring 2006
Adapted from
http://www-inst.eecs.berkeley.edu/~cs61c/
Review° Instructions:
Arithmetic: add, addi, sub
Memory access: lw, sw
Branch: beq, bne, j
comparison: slt, slti, sltu, sltiu
Review of Lab#2: memory access
.globl main .datastr: .asciiz "abcdABCD"
.textmain: … la $s1, str # $s1=str[0] lb $t2, 0($s1) addi $s1, $s1, 1 # $s1=str[1] lb $t2, 0($s1)
abcdABCD
strstr[1]
li $t0, 1 # i=1lb $t2, $t0($s1) # str[i] Wrong!
Hierarchy of Programming Languages
Low-level
High-level
Java
C
Assembly
Degree ofabstraction operand operation
objects method
variables arithmetic op.functions
registers instruction set
machine binary operation coderegisters
Q: How do we represent instructions
in machine?
Overview° Instructions as Numbers
°R-Format
° I-Format
°Branch instruction: addressing mode
°J-Format
Instructions as Numbers (1/2)°Currently all data we work with is in words (32-bit blocks):
• Each register is a word.•lw and sw both access memory one word at a time.
°So how do we represent instructions?• Remember: Computer only understands 1s and 0s, so “add $t0,$0,$0” is meaningless.
• MIPS wants simplicity: since data is in words, make instructions be words...
Instructions as Numbers (2/2)°One word is 32 bits, so divide instruction word into “fields”.
°Each field tells computer something about instruction.
°We could define different fields for each instruction, but MIPS is based on simplicity, so define 3 basic types of instruction formats:
• R-format
• I-format
• J-format
6 5 5 5 65
6 5 5 16
opcode
6 26
Instruction Formats°J-format: used for j and jal
° I-format: used for instructions with immediates ( 含常數的指令 )•lw and sw (since the offset counts as an immediate)
• the branches (beq and bne)
• (but not the shift instructions; later)
°R-format: used for all other instructions• Registers as operands
Overview° Instructions as Numbers
°R-Format
° I-Format
°Branch instruction: addressing mode
°J-Format
以暫存器為運算單位的指令
R-Format Instructions (1/5)°Define “fields” of the following number of bits each:
6 5 5 5 65
opcode rs rt rd functshamt
°For simplicity, each field has a name:
° Important: Each field is viewed as a 5- or 6-bit unsigned integer, not as part of a 32-bit integer.
• Consequence: 5-bit fields can represent any number 0-31, while 6-bit fields can represent any number 0-63.
Low-orderbits
high-orderbits
每個 field 看做單獨的數字
R-Format Instructions (2/5)
°What do these field integer values tell us?•opcode: partially specifies what instruction it is (Note: This number is equal to 0 for all R-Format instructions.)•funct: combined with opcode, this number exactly specifies the instruction
• Question: Why aren’t opcode and funct a single 12-bit field?
• Answer: We’ll answer this later.
opcode rs rt rd functshamt
R-Format Instructions (3/5)°More fields:
•rs (Source Register): generally used to specify register containing first operand•rt (Target Register): generally used to specify register containing second operand (note that name is misleading)•rd (Destination Register): generally used to specify register which will receive result of computation
opcode rs rt rd functshamt
R-Format Example°MIPS Instruction:
add $t0,$t1,$t2 =>
add $8,$9,$10
0 9 10 8 32?
000000 01001 01010 01000 100000?
binary representation:
decimal representation:opcode rs rt rd functshamt
100123456789
101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263
100123456789
101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263
100123456789
101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263
0123456789
10111213141516171819202122232425262728293031
0123456789
10111213141516171819202122232425262728293031
0123456789
10111213141516171819202122232425262728293031
16000102030405060708090a0b0c0d0e0 f101112131415161718191a1b1c1d1e1 f202122232425262728292a2b2c2d2e2 f303132333435363738393a3b3c3d3e3 f
op(31:26)
jjalbeqbneblezbgtzaddiaddiusltisltiuandiorixoriluiz = 0z = 1z = 2z = 3
lblhlwllwlbulhulwr
sbshswlsw
swr
lwc0lwc1lwc2lwc3
swc0swc1swc2swc3
rs(25:21)mfcz
cfcz
mtcz
ctcz
copzcopz
(16:16)bcztbczt
tlbrtlbwi
tlbwrtlbp
rte
rt (20:16)
bltzbgez
bltzalbgezal
cvt.s.fcvt.d.f
cvt.w.f
c.f.fc.un.fc.eq.fc.ueq.fc.olt.fc.ult.fc.ole.fc.ule.fc.st.fc.ngle.fc.seq.fc.ngl.fc.lt.fc.nge.fc.le.fc.ngt.f
funct(5:0)add.fsub.fmul.fdiv.f
abs.fmov.fneg.f
funct(5:0)sll
srlsra
srlvsravjrjalr
syscallbreak
mfhimthimflomtlo
multmultudivdivu
addaddusubsubuandorxornor
sltsltu
if z = l,f = d
if z = l,f = s
if z = 0
01
funct(4:0)
See p. A-54
R-Format Instructions (4/5)°Notes about register fields:
• Exactly 5 bits => 0~31 => indicate the register number
°Final field:•shamt: This field contains the amount a shift instruction will shift by. Shifting a 32-bit word by more than 31 is useless, so this field is only 5 bits (so it can represent the numbers 0-31).
• This field is set to 0 in all but the shift instructions.
opcode rs rt rd functshamt
R-Format Example (cont.)°MIPS Instruction:
add $t0,$t1,$t2 => add $8,$9,$10
0 9 10 8 320
000000 01001 01010 01000 10000000000
binary representation:
Called a Machine Language Instruction
decimal representation:
Hex: 0 1 2 a 4 0 2 0
opcode rs rt rd functshamt
Overview° Instructions as Numbers
°R-Format
° I-Format
°Branch instruction: addressing mode
°J-Format
以常數為運算單位的指令
I-Format Instructions (1/5)
°What about instructions with immediates?
• Ideally, MIPS would have only one instruction format (for simplicity): unfortunately, we need to compromise
• 5-bit field only represents numbers up to the value 31: immediates may be much larger than this
°Define new instruction format that is partially consistent with R-format !
Opcode 6 rs 5 rt 5 rd 5 funct 6shamt 5
R-format:
c.f. add $t0, $t1, $t2 addi $t0, $t1, 2
I-Format Instructions (2/5)° I-format:
6 5 5 16
opcode rs rt immediate
°Again, each field has a name:
Compared with R-format:
Opcode 6 rs 5 rt 5 rd 5 funct 6shamt 5
I-Format Instructions (3/5)°What do these fields mean?
•opcode: same as before except that, since there’s no funct field, opcode uniquely specifies an I-format instruction
• This also answers question of why R-format has two 6-bit fields to identify instruction instead of a single 12-bit field: in order to be consistent with other formats.
Opcode 6 rs 5 rt 5 Immediate 16 bits
Opcode 6 rs 5 rt 5 rd 5 funct 6shamt 5
I
R
I-Format Instructions (4/5)
°More fields:•rs: specifies the only register operand (if there is one)•rt: specifies register which will receive result of computation (this is why it’s called the target register “rt”)
opcode rs rt immediate
addi $t0, $t1, 1
I-Format Instructions (5/5)°The Immediate Field:
• 16 bits can be used to represent immediate up to 216 different values•addi, slti, sltiu: the immediate is sign-extended to 32 bits in real hardware operation
• lw, sw: immediate = offset- lw $t0, 0($a0)
opcode rs rt Immediate 16 bits
I-Format Example
°MIPS Instruction: addi $s5,$s6,-50
=> addi $21,$22,-50
8 22 21 -50
001000 10110 10101 1111111111001110
decimal representation:
binary representation:
Hex: 2 2 d 5 f f c e
opcode rs rt immediate
100123456789
101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263
100123456789
101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263
100123456789
101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263
0123456789
10111213141516171819202122232425262728293031
0123456789
10111213141516171819202122232425262728293031
0123456789
10111213141516171819202122232425262728293031
16000102030405060708090a0b0c0d0e0 f101112131415161718191a1b1c1d1e1 f202122232425262728292a2b2c2d2e2 f303132333435363738393a3b3c3d3e3 f
op(31:26)
jjalbeqbneblezbgtzaddiaddiusltisltiuandiorixoriluiz = 0z = 1z = 2z = 3
lblhlwllwlbulhulwr
sbshswlsw
swr
lwc0lwc1lwc2lwc3
swc0swc1swc2swc3
rs(25:21)mfcz
cfcz
mtcz
ctcz
copzcopz
(16:16)bcztbczt
tlbrtlbwi
tlbwrtlbp
rte
rt (20:16)
bltzbgez
bltzalbgezal
cvt.s.fcvt.d.f
cvt.w.f
c.f.fc.un.fc.eq.fc.ueq.fc.olt.fc.ult.fc.ole.fc.ule.fc.st.fc.ngle.fc.seq.fc.ngl.fc.lt.fc.nge.fc.le.fc.ngt.f
funct(5:0)add.fsub.fmul.fdiv.f
abs.fmov.fneg.f
funct(5:0)sll
srlsra
srlvsravjrjalr
syscallbreak
mfhimthimflomtlo
multmultudivdivu
addaddusubsubuandorxornor
sltsltu
if z = l,f = d
if z = l,f = s
if z = 0
01
funct(4:0)
I-Format Problems (1/3)
°Problem 1: • What if immediates are too big to fit in the immediate field (16 bits only)?
- We need a way to deal with a 32-bit immediate in any I-format instruction.
• How to do this?addi $t0,$t0, 0x2BAB2DCD
16 bits16 bits
I-Format Problems (2/3)
°Solution to Problem 1:• Handle it in software (assembler)
• Don’t change the current instructions: instead, add a new instruction to help out
°New instruction:lui register, immediate
• stands for Load Upper Immediate
• takes 16-bit immediate and puts these bits in the upper half (high order half) of the specified register
• sets lower half to 0s 16 16reg.
I-Format Problems (3/3)°Solution to Problem 1 (continued):
• So how does lui help us?
• Example:addi $t0,$t0, 0x2BAB2DCD
becomes:
lui $a0, 0x2BABori $a0, $a0,
0x2DCD add $t0,$t0,$a0
Why not : li $a0, 0x2BAB2DCD
How to be an assembler?
°Assembly code:
.data .textmain: bne $t0, $t1, End lui $t3, 0x2BAB ori $t3, $t3, 0x2DCD add $s0, $s1, $t3End:
step 1
°Choose which formats they are?
°Write down the formats and how many bits for each field
Opcode 6 rs 5 rt 5 rd 5 funct 6shamt 5
R-format
Opcode 6 rs 5 rt 5 Immediate 16
I-format
step 2
°Write down the encoding of registers
100123456789
101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263
100123456789
101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263
100123456789
101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263
0123456789
10111213141516171819202122232425262728293031
0123456789
10111213141516171819202122232425262728293031
0123456789
10111213141516171819202122232425262728293031
16000102030405060708090a0b0c0d0e0 f101112131415161718191a1b1c1d1e1 f202122232425262728292a2b2c2d2e2 f303132333435363738393a3b3c3d3e3 f
op(31:26)
jjalbeqbneblezbgtzaddiaddiusltisltiuandiorixoriluiz = 0z = 1z = 2z = 3
lblhlwllwlbulhulwr
sbshswlsw
swr
lwc0lwc1lwc2lwc3
swc0swc1swc2swc3
rs(25:21)mfcz
cfcz
mtcz
ctcz
copzcopz
(16:16)bcztbczt
tlbrtlbwi
tlbwrtlbp
rte
rt (20:16)
bltzbgez
bltzalbgezal
cvt.s.fcvt.d.f
cvt.w.f
c.f.fc.un.fc.eq.fc.ueq.fc.olt.fc.ult.fc.ole.fc.ule.fc.st.fc.ngle.fc.seq.fc.ngl.fc.lt.fc.nge.fc.le.fc.ngt.f
funct(5:0)add.fsub.fmul.fdiv.f
abs.fmov.fneg.f
funct(5:0)sll
srlsra
srlvsravjrjalr
syscallbreak
mfhimthimflomtlo
multmultudivdivu
addaddusubsubuandorxornor
sltsltu
if z = l,f = d
if z = l,f = s
if z = 0
01
funct(4:0)
Step 3: decide opcode
step 4
°Fill the other fields
Peer Instruction
Which instruction has same representation as 35ten?
1. add $0, $0, $0
2. subu $s0,$s0,$s0
3. lw $0, 0($0)
4. addi $0, $0, 35
5. subu $0, $0, $0
6. Trick question! Instructions are not numbers
Registers numbers and names: 0: $0, .. 8: $t0, 9:$t1, ..15: $t7, 16: $s0, 17: $s1, .. 23: $s7
Opcodes and function fields (if necessary)
add: opcode = 0, funct = 32subu: opcode = 0, funct = 35addi: opcode = 8lw: opcode = 35
opcode rs rt offset
rd functshamtopcode rs rt
opcode rs rt immediate
rd functshamtopcode rs rt
rd functshamtopcode rs rt
Overview° Instructions as Numbers
°R-Format
° I-Format
°Branch instruction: addressing mode
°J-Format
Branches: PC-Relative Addressing (1/5)°Use I-Format
opcode rs rt immediate
°opcode specifies beq , bne
°rs and rt specify registers to compare
°What can immediate specify?•Immediate is only 16 bits
• Label is 32-bit address in memory
• So immediate cannot specify entire address to branch to.(16 bits 定址空間有限)
Ex. beq $t0, $t0, Label
Branches: PC-Relative Addressing (2/5)
°How do we usually use branches?• Answer: if-else, while, for
• Loops are generally small: typically up to 50 instructions ( 迴圈程式段落通常不大 )
• Function calls and unconditional jumps are done using jump instructions (j and jal), not the branches.
°Conclusion: a single branch will generally change the PC by a very small amount.
Branches: PC-Relative Addressing (3/5)°Solution: PC-Relative Addressing
°16-bit immediate = offset
°Now we can branch +/- 215 bytes from the PC, which should be enough to cover any loop.
…PC
Target address: PC + offset
offset
Branches: PC-Relative Addressing (4/5)
°Note: Instructions are words, so they’re word aligned
• So the number of bytes to add to the PC will always be a multiple of 4.( 指令碼的位址都是四的倍數 )
• So specify the immediate in words.
°Now, we can branch +/- 215 words from the PC (or +/- 217 bytes), so we can handle loops 4 times as large.
Branches: PC-Relative Addressing (5/5)°Final Calculation:
• If we don’t take the branch:
PC = PC + 4
• If we do take the branch:
PC = (PC + 4) + (immediate * 4)
• Observations- Immediate field specifies the number of
words to jump, which is simply the number of instructions to jump.
- Immediate field can be positive or negative.
- Due to hardware, add immediate to (PC+4), not to PC; will be clearer why later in course
beq(bne) rs, rt, Label
Branch Example (1/3)
°MIPS Code:Loop: beq $9,$0,End
add $8,$8,$10addi $9,$9,-1
j LoopEnd:
°Branch is I-Format:opcode = 4 (look up in table)
rs = 9 (first operand)
rt = 0 (second operand)
immediate = ???
100123456789
101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263
100123456789
101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263
100123456789
101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263
0123456789
10111213141516171819202122232425262728293031
0123456789
10111213141516171819202122232425262728293031
0123456789
10111213141516171819202122232425262728293031
16000102030405060708090a0b0c0d0e0 f101112131415161718191a1b1c1d1e1 f202122232425262728292a2b2c2d2e2 f303132333435363738393a3b3c3d3e3 f
op(31:26)
jjalbeqbneblezbgtzaddiaddiusltisltiuandiorixoriluiz = 0z = 1z = 2z = 3
lblhlwllwlbulhulwr
sbshswlsw
swr
lwc0lwc1lwc2lwc3
swc0swc1swc2swc3
rs(25:21)mfcz
cfcz
mtcz
ctcz
copzcopz
(16:16)bcztbczt
tlbrtlbwi
tlbwrtlbp
rte
rt (20:16)
bltzbgez
bltzalbgezal
cvt.s.fcvt.d.f
cvt.w.f
c.f.fc.un.fc.eq.fc.ueq.fc.olt.fc.ult.fc.ole.fc.ule.fc.st.fc.ngle.fc.seq.fc.ngl.fc.lt.fc.nge.fc.le.fc.ngt.f
funct(5:0)add.fsub.fmul.fdiv.f
abs.fmov.fneg.f
funct(5:0)sll
srlsra
srlvsravjrjalr
syscallbreak
mfhimthimflomtlo
multmultudivdivu
addaddusubsubuandorxornor
sltsltu
if z = l,f = d
if z = l,f = s
if z = 0
01
funct(4:0)
Branch Example (2/3)
°MIPS Code:Loop: beq $9,$0,End
addi $8,$8,$10addi $9,$9,-1j Loop
End:
°Immediate Field:• Number of instructions to add to (or subtract from) the PC, starting at the instruction following the branch.
• In this case, immediate = 3* test this in PCspim, set bare machine in the setting
PC+4
3 inst.
Branch Example (3/3)°MIPS Code:
Loop: beq $9,$0,Endaddi $8,$8,$10
addi $9,$9,-1j Loop
End:
4 9 0 3
decimal representation:
binary representation:
000100 01001 00000 0000000000000011
Big Idea: Stored-Program Concept
°Computers built on 2 key principles:
1) Instructions are represented asnumbers.
2) Therefore, entire programs can be stored in memory to be read or written just like numbers (data).
Consequence #1: Everything Addressed
°Since all instructions and data are stored in memory as numbers, everything has a memory address: instructions, data words
• both branches and jumps use these
°C pointers are just memory addresses
°One register keeps address of instruction being executed: “Program Counter” (PC)
• Basically a pointer to memory: Intel calls it Instruction Address Pointer, which is better
Consequence #2: Binary Compatibility°Programs are distributed in binary form• Programs bound to specific instruction set
• Different version for Macintosh and IBM PC
°New machines want to run old programs (“binaries”) as well as programs compiled to new instructions
Review
°Machine Language Instruction: 32 bits representing a single MIPS instruction
opcode rs rt rd functshamtopcode rs rt immediate
R
Iopcode target addressJ
° Instructions formats are kept as similar as possible.
Jump instruction
°J-format
°General address: 32 bits
6 bits Target:26 bits
PC
31… 28
26 bits 00
wordalignment
J-Format Instructions (1/5)°For branches, we assumed that we won’t want to branch too far, so we can specify change in PC.
• beq, bne
°For general jumps (j and jal), we may jump to anywhere in memory.
• Ideally, we could specify a 32-bit memory address to jump to.
• Unfortunately, we can’t fit both a 6-bit opcode and a 32-bit address into a single 32-bit word, so we compromise.
opcode target addressJ
J-Format Instructions (2/5)°Define “fields” of the following number of bits each:
6 bits 26 bits
opcode target address
°As usual, each field has a name:
°Key Concepts• Keep opcode field identical to R-format and I-format for consistency.
• Combine all other fields to make room for target address.
J-Format Instructions (3/5)
°For now, we can specify 26 bits of the 32-bit bit address.
°Optimization:• Note that, just like with branches, jumps will only jump to word aligned addresses, so last two bits are always 00 (in binary).
• So let’s just take this for granted and not even specify them.
J-Format Instructions (4/5)°For now, we can specify 28 bits of the 32-bit address.
°Where do we get the other 4 bits?• By definition, take the 4 highest order bits from the PC.
• Technically, this means that we cannot jump to anywhere in memory, but it’s adequate 99.9999…% of the time, since programs aren’t that long.
• If we absolutely need to specify a 32-bit address, we can always put it in a register and use the jr instruction.
J-Format Instructions (5/5)
°Summary:• New PC = PC[31..28]
|| target address (26 bits) || 00
• Note: II means concatenation4 bits || 26 bits || 2 bits = 32-bit address
PC
31… 28
26 bits 00
Addressing mode
Byte Halfword Word
Registers
Memory
Memory
Word
Memory
Word
Register
Register
1. Immediate addressing
2. Register addressing
3. Base addressing
4. PC-relative addressing
5. Pseudodirect addressing
op rs rt
op rs rt
op rs rt
op
op
rs rt
Address
Address
Address
rd . . . funct
Immediate
PC
PC
+
+