Digital Instruments

The digital voltmeters generally referred as DVM, convert the analog signals intodigital and display the voltages to be measured as discrete numericals instead of pointerdeflection, on the digital displays. Such voltmeters can be used to measure a.c. and d.c.voltages and also to measure the quantities like pressure, temperature, stress etc. usingproper transducer and signal conditioning circuit. The transducer converts the quantityinto the proportional voltage signal and signal conditioning circuit brings the signal intothe proper limits which can be easily measured by the digital voltmeter. The outputvoltage is displayed on the digital display on the front panel. Such a digital outputreduces the human reading and interpolation errors and parallax errors.

The DVMs have various features and the advantages, over the conventional analogvoltmeters having pointer deflection on the continuous scale.

1. Due to the digital display, the human reading errors, interpolation errors andparallax errors are reduced.

2. They have input range from +1.000 V to +1000 V with the automatic rangeselection and the overload indication.

3. The accuracy is high upto ± 0.005% of the reading.4. The resolution is better as 1 I..lV reading can be measured on 1 V range.

5. The input impedance is as high as 10 MD.

6. The reading speed is very high due to digital display.

7. They can be programmed and well suited for computerised control.

8. The output in digital form can be directly recorded and it is suitable for furtherprocessing also.

l). With the development of IC chips, the cost of DVMs, size and power requirementsof DVMs are drastically reduced.

10. Due to small size, are portable.

11. The internal calibration does not depend on the measuring circuit.

12. The BCD output can be printed or used for digital processing.

13. The inclusion of additional circuitry make them suitable for the measurement 01quantities like current, impedance, capacitance, temperature, pressure etc.

1. Number of measurement ranges:

The basic range of any DVM is either 1V or 10 V. With the help of attenuator at theinput, the range can be extended from few microvolts to kilovolts.

2. Number of digits in readout: The number of digits of DVMs vary from 3 to 6. Morethe number of digits, more is the resolution.

3. Accuracy: The accuracy depends on resolution and resolution on number of digits.Hence more number of digits means more accuracy. The accuracy is as high upto ± 0.005%of the reading.

4. Speed of the reading: In the digital voltmeters, it is necessary to convert analogsignal into digital signal. The various techniques are used to achieve this conversion. Thecircuits which are used to achieve such conversion are called digitizing circuits and theprocess is called digitizing. The time required for this conversion is called digitizingperiod. The maximum speed of reading and the digitizing period are interrelated. Theinstrument user must wait, till a stable reading is obtained as it is impossible to follow thevisual readout at high reading speeds.

5. Normal mode noise rejection: This is usually obtained through the input filtering orby tise of the integration techniques. The noise present at the input, if passed to the analogto digital converting circuit then it can produce the error, especially when meter is usedfor low voltage measurement. Hence noise is required to be filtered.

6. Common mode noise rejection : This is usually obtained by guarding. A guard is asheet metal box sourrounding the circuitry. A terminal at the front panel makes this 'box'available to the circuit under measurement.

7. Digital output of several types: The digital readout of the instrument may be 4 lineBCD, single line serial output etc. Thus the type of digital output also determines thevariety of the digital voltmeter.

8. Input impedance : The input impedance of DVM must be as high as possible whichred l1ces the loading effects. Typically it is of the order of 10 :M.n.

Any digital instrument requires analog to digital converter at its input. Hence firstblock in a general DVM is ADC as shown in the Fig. 3.1.

Signalprocessing

Datatransmission

elementAnaloginput

Fig. 3.1 Basic block diagram of DVMEvery ADC requires a reference. The reference is generated internally and reference

generator circuitry depends on the type of ADC technique used. The output of ADC isdecoded and signal is processed in the decoding stage. Such a decoding is necessary todrive the seven segment display. The data from decoder is then transmitted to the display.The data transmission element may be a latches, counters etc. as per the requirement. Adigital display shows the necessary digital result of the measurement.

It uses a linear ramp technique or staircase ramp technique. The staircase ramptechnique is simpler than the linear ramp technique. Let us discuss both the techniques.

3.5.1 Linear Ramp TechniqueThe basic principle of such measurement is based on the measurement of the time

taken by l1 linear ramp to rise from a V to the level of the input voltage or to decreasefrom the level of the input voltage to zero. This time is measured with the help ofelectronic time interval counter and the count is displayed in the numeric form with thehelp of a digital display.

Start of ramp151 coincidence------------------

2nd coincidenceI II I

: I----r--..J-----I I

I.t"':I

Clock pulsesto counter Gate Gate

opened closed

Basically it consists of a linear ramp which is positive going or negative going. Therange of the ramp is ± 12 V while the base range is ± 10 V. The conversion from a voltageto c1 time interval is shown in the Fig. 3.2.

At the start of measurement, a ramp voltage is initiated which is continuouslycompared with the input voltage. When these two voltages are same, the comparatorgenerates a pulse which opens a gate i.e. the input comparator generates a start pulse. Theramp continues to decrease and finally reaches to 0 V or ground potential. This is sensedby the second comparator or ground comparator. At exactly 0 V, this comparator producesa stop pulse which closes the gate. The number of clock pulses are measured by thecounter. Thus the time duration for which the gate is opened, is proportional to the inputvoltage. fn the time interval between start and stop pulses, the gate remains open and theoscillator circuit drives the counter. The magnitude of the count indicates the magnitude ofthe input voltage, which is displayed by the display. The block diagram of linear rampDVM is shown in the Fig. 3.3.

Inputvoltage

Rangingand

attenuator

Fig. 3.3 Linear ramp type DVM

Properly attenuated input signal is applied as one input to the input comparator. Theramp generator generates the proper linear ramp signal which is applied to both tnecomparators. Initially the logic circuit sends a reset signal to the counter and the readout.The comparators are designed in such a way that when both the input signals ofcomparator are equal then only the comparator changes its state. The input comparator isused to send the start pulse while the ground comparator is used to send the stop pulse.

When the input and ramp are applied to the input comparator, and at the point whennegative going ramp becomes equal to input voltages the comparator sends start pulse,due to which gate opens. The oscillator drives the counter. The counter starts counting thepulses received from the oscillator. Now the same ramp is applied to the groundcomparator and it is decreasing. Thus when ramp becomes zero, both the inputs of groundcompaotor becomes zero (grounded) i.e. equal and it sends a stop pulse to the gate due towhich gate gets closed. Thus the counter stops receiving the pulses from the localoscillator. A definite number of pulses will be counted by the counter, during the start andstop pulses which is measure of the input voltage. This is displayed by the digital readout.'

The sample rate multivibrator determines the rate at which the measurement cycles areinitiated. The oscillation of this multivibrator is usually adjusted by a front panel controlnamed rate, from few cycles per second to as high as 1000 or more cycles per second. Thetypical value is 5 measuring cycles/second with an accuracy of ± 0.005% of thereading. The sample rate provides an initiating pulse to the ramp generator to start its nextramp voltage. At the same time, a reset pulse is also generated which resets the counter tothe zero state.

The advantages of this technique are:

i) The circuit is easy to design.

ii) The cost is low.

iii) The output pulse can be transferred over long feeder lines without loss ofinformation.

iv) The input signal is converted to time, which is easy to digitise.

v) By adding external logic, the polarity of the input also can be displayed.

vi) The resolution of the readout is directly proportional to the frequency of the localoscillator. So adjusting the frequency of the local oscillator, belter resolution can beobtained.

The disadvantages of this technique are:

i) The ramp requires excellent characteristics regarding its linearity.

ii) The accuracy depends on slope of the ramp and stability of the local oscillator.

iii) Large errors are possible if noise is superimposed on the input signal.

iv) The offsets and drifts in the two comparators may cause errors.

v) The speed of measurement is low.

vi) The swing of the ramp is ± 12 V, this limits the base range of measurement to± 10 V.

/"

In this type of DVM,instead of linear ramp, thestaircase ramp is used. Thestaircase ramp is generatedby the digital to analogconverter. The blockdiagam of staircase ramptype DV 1 is shown in theFig 3.4.

The technique of usingstaircase ramp is also callednull balance technique.

The input voltage is properly attenuated and is applied to a null detector. The anotherinput to null detector is the staircase ramp generated by digital to analog converter. Theramp is continuously compared with the input signal.

fnitially the logical control circuit sends a reset signal. This signal resets the counter.The digital to analog converter is also resetted by same signal.

At the start of the measurement, the logic control circuit sends a starting pulse whichopens the gate. The counter starts counting the pulses generated by the local oscillator.

The output of counter is given to the digital to analog converter which generates theramp signal. At every count there is an incremental change in the ramp generated. Thusthe staircase ramp is generated at the output of the digital to analog converter. This isgiven as the second input of the null detector. The increase in ramp continues till itachieves the voltage equal to input voltage.

When the two voltages are equal, the null detector generates a signal which in turninitiates the logic control circuit. Thus logic control circuit sends a stop pulse, which closesthe gate and the counter stops counting.

At the same time, the logic control circuit generates a transfer signal due to which thecounter information is transferred to the readout. The readout shows the digital result ofthe count.

The advantages of this technique are:

i) The greater accuracy is obtained than the linear ramp technique.

ii) The overall design is more simple hence economical.

iii) The input impedance of the digital to analog converter is high when thecompensation is reached.

The disadvantages of this technique are:

i) Though accuracy is higher than linear ramp, It IS dependent on the accuracy ofdigital to analog converter and its internal reference.

ii) The speed is limited upto 10 readings per second.

After the discussion of the non-integrating type of DVMs, let us see the operation andfeatures of integrating type of DVMs.

This is the most popular method of analog to digital conversion. In the ramptechniques, the noise can cause large errors but in dual slope method the noise is averagedout by the positive and negative ramps using the process of integration. The basicprinciple of this method is that the input signal is integrated for a fixed interval of time.And then the same integrator is used to integrate the reference voltage with reverse slope.Hence the name given to the technique is dual slope integration technique.

The block diagram of dual slope integrating type DVM is shown in the Fig. 3.5. Itconsists of five blocks, an op-amp used as an integrator, a zero comparator, clock pulsegenerator, a set of decimal counters and a block of control logic.

Input \ I

vOltage'i2

-vref

+

-=- Voltage ~

t1 t2

1 1

~Gate 1 2 Gateopen closed

Fig. 3.5 Dual slope integrating type DVM

When the switch Sl is in position 1, the capacitor C starts charging from zero level.The rate of charging is proportional to the input voltage level. The output of the op-amp isgiven by,

1 11

- Ref Vin dt1 0

After the interval t I, the input voltage is disconnected and a negative voltage -Vref isconnected by throwing the switch S1 in position 2. In this position, the output of theop-ilmp is given by,

1 12

Ref -Vref dt1 0

This basic principle of this method isshown in the Fig. 3.6.

At the start of the measurement, thecounter is resetted to zero. The output of theflip-flop is also zero. This is given to thecontrol logic. This control sends a signal soas to close an electronic switch to position 1and integration of the input voltage starts. Itcontinues till the time period t]. As theoutput of the integrator changes from its

J:t'ro value, the zero comparator output changes its state. This provides a signal to controllo~ic which inturn opens the gate and the counting of the clock pulses starts.

The counter counts the pulses and when it reaches to 9999, it generates a carry pulseand all digits go to zero. The flip flop output gets activated to the logic level T. Thisactivates the control logic. This sends a signal which changes the switch 5\ position from 1to 2 Thus -Vref gets connected to op-amp. As Vref polarity is opposite, the capacitor startsdischarging. The integrator output will have constant negative slope as shown in thFig. 3.5"1. The output decreases linearly and after the interval t2, attains zero value, whenthe capacitor C gets fully discharged.

Vref t2 Vin t]RtC R] C

Vret t2 Vll1 t]

Vin Vreft2= t]

IIIIII

- 11 -1-- 12 --: I

1-12'-: I

I" 12"-:

Fig, 3,6 Basic principle of dual slopemethod

Thus the input voltage is dependent onthe time periods t] and t2 and not on thevalues of R] and C.

At this instant, the output of zero comparator changes its state. This inturn sends asignal to the control logic and the gate gets closed. Thus gate remains open for the periodt 1+ t 2' The counting operation stops at this instant. The pulses counted by the counterthus have a direct relation with the input voltage. The counts are then transferred to thereildout.

From equation (3) we can write,

t2Vin = Vref·- t]

Let time period of clock oscillator be T and digital counter has counted the counts n]lllldn2 during the period t] and t2 respectively.

Thus the unknown voltage measurement is not dependent on the clock frequency, butdependent on the counts measured by the counter.

The advantages of this technique are:

i) Excellent noise rejection as noise and superimposed a.c. are averaged out duringthe process of integration.

ii) The RC time constant does not affect the input voltage measurement.

iii)The capacitor is connected via an electronic switch. This capacitor is an auto zerocapacitor and avoids the effects of offset voltage.

iv)The integrator responds to the average value of the input hence sample and holdcircuit is not necessary.

v) The accuracy is high and can be readily varied according to the specificrequirements.

In case of ramp type DVM, the voltage is converted to time. The time and frequencyare related to each other. Thus the voltage can be converted to frequency for themeasurement purpose. A train of pulses, whose frequency depends upon the voltage beingmeasured, is generated. Then the number of pulses appearing in a definite interval of timeis counted . Since the frequency of these pulses is a function of the unknown voltage, thenumber of pulses counted in that period of time is the indication of the unknown inputvoltage.

The heart of such integrating type of DVM is the operational amplifier used as anintegrator. The input voltage is integrated for a fixed interval. An integration of a constant

input voltage results a ramp at the output, the slope ofwhich is proportional to the input voltage. If the inputis positive, the output of op-amp is negative goingramp. After some time, the capacitor is discharged to 0,thus output returns back to zero and the next cyclebegins. Hence the waveform at the output is a sawtoothwaveform as shown in the Fig. 3.7.

If the input signal is doubled, the number of teeth in the output signal per unit timewill be also doubled. Thus the frequency of the output will be doubled. Thus the

o ,\-l\-r\-f\-r----~-~-~-~--- -v

frequency of the output is proportional to the input voltage. This is nothing but thevoltage to frequency conversion.

The sawtooth pulses are finally enter into a reversible counter. The measured value bythe reversible counter is finally displayed with the help of digital readout.

The block diagram of voltage to frequency converter type integrating DVM is shownin the Fig. 3.8.

Inputvoltage

Vin

~Summingjunction

Reversiblecounter %",'" ""'):(

Digitalread out

Initially output of an integrator is adjusted to zero volts. When the input voltage Vi" isapplied, the charging current Vin /Rj flows, which starts the charging of the capacitor C.This produces a ramp at the output. When input voltage is positive, the output ramp isnegative going. This ramp is given as one input of a comparator. A -V volts is given as areference to the second input terminal of a comparator. The negative going ramp and - Vvolts reference are compared by the comparator. When the ramp reaches to -V volts, thecomparator output changes its state. This signal triggers the pulse generator. The functionof the pulse generator is to produce a pulse of precision charge content. The polarity ofthis charge is opposite to that of capacitor charge. Thus the pulse generated by the pulsegenerator rapidly discharges the capacitor. Hence the output of the op-amp again becomeszero. This process continues so as to get a sawtooth waveform at the output of op-amp.The frequency of such waveform is directly proportional to the applied input voltage. Thusif the input voltage increases, the number of teeth per unit time in the sawtooth waveformalso increases i.e. the frequency increases.

Each teeth produces a pulse at the output of the pulse generator so number of pulsesis directly related to the number of teeth i.e. the frequency.

These pulses are allowed to pass through the pulse transformer. These are applied atone input of the gate. Gate length control signal is applied at the other input. The gatelength' may be 0.1 sec, Isec, 20 msec etc. The gate remains open for this much time period.

When the gate is open, the pulses are counted by the reversible counter. After gatelength period, when the gate is closed, the count measured by the counter is transferred tothe digital reddout.

Mathematical Analysis: The input voltage Vin charges the capilcitor with d currentVll1 I Rj upto the reference voltage connected to the comparator other end. Let this voltageis Yr' When capacitor voltage reaches this value, the comparator changes the stilte, givingtrigger to the pulse generiltor. This produces the pulse of precision charge content whichdischarges the capacitor rapidly.

Key Point: The mte of rlwrging and disc!zarging results in a sigual WIIUSt' /i'equeucy IS

directly proportional to the iuput voltage V,",

The wavefonns of integriltor output ilnd output of a pulse generator Zlre shown In theFig 3.9.

IIIIIIIIIII

I I I__ .L ..J

I I It1 t2 I I I

___ ••_.~ ••_I I

I_M_n_H-Integrator

output

Pulseoutput

From the analysis of dual slope technique, we can write,

t2Vin == Vr-t1

But in this type, both Vr and t2 are constants.

K2 Vrt2

Key Point : TIlliS the output frequency fo is directly proportional to tlu' input uoltllge Vin.

The discharging time of capacitor must be as small (/s possible.

Accuracy: The accuracy of voltage to frequency conversion technique depend:> on thel11<lgnilude and stability of the charge produced by the pulse generator. Thus the ,lCcuracvde}~enLis on the precision of the charge fedback in every pulse and also on the linearit,bdween voltage and frequency.

To obtain the better accuracy the rate of pulses generated by the pulse generator iskept equal to,

i) the voltage time integration of the input signal

ii) the total voltage time areas of the feedback pulses

There are two techniques to design the pulse generator for the better clCcuracy :

i) Using a precision capacitor : The precision capacitor is placed between the pulsegenerator and the summing junction of op-amp. The capacitor is allowed to charge llptoprecise voltage level and then this charge can be transferred to the summing junction ofop-c1mp.

ii) Using a transformer: The transformer can be placed between the pulse generatorand the summing junction of op-amp. The primary of the trzl11sformer is connected to thepulse generator. The secondary is connected to the summing junction of op-amp. Thetransformer material has a square type hysteresis loop characteristics. Due to this, there ioexcursion around the B-H loop of trans(~ This excursion can produce precise am.ountof chclrgc at the summing junction of op-amp.

The purpose of the reversible counter is to sense the polarity of input voltage andcount the pulses accordingly. If the input signal changes its polarity during a measuringI-wriod tlwn the pulses received by the counter after the reversal of polarity must besubtr'lCtcd from the previous count. For this purpose, the counter used is a reversiblecounter. If a reversible counter is not used, then the counter will keep on adding thenumber of pulses and total count will keep on increasing thOllgh actually the inputpolarity is reversed. This will give the incorrect reading. This type of situations may occurwhile measuring the low voltage of the order of mV in presence of a large amount ofsuperimposed noise signal.

When the reversible counting scheme is used, there are four conditions of counting arepossible which are,

i) r\lsitive up-counting

ii) Positive down-counting

iii).Negative up-counting

iv) Negative down-counting

For the measurement of bipolar voltages, one more set of compariltor and the pulsegeneriltor is necessary to add. The second comparator produces positive going pulse forthe negative input signal. A +V volts reference is used at the second input terminill of thiscomp,lrator. The only important thing is that, both the pulse generators should producesame amount of feedback charge at the summing point of the op-amp.

Let us study the waveforms at various stages of the DVM when c1 complex inputw<1l'efonn is applied to it. The various waveforms are shown in the Fig. 3.10.

The input voltage has positive polarity for the period t (I to t I and negative polarity forthe period t: to t 4' For the periods t I to t 1 and t 4 to t 5 I the vol tage level is zero.

The g<1te should be open for the entire time interval t (I to t (,. This if: shown in thew,lI'efonn Fig. 3.10 (d).

___ .!n'put voltage(a)

IIa ---+-I

-f

Pulse generator output forpositive input voltage

(b)

II,

Gate' 0 en,IIIIII

Pulse generator output fornegative input voltage

(e)

Gate opening

(d)

III

1 - VB :jCounUnglI down I

t. t~ t~

Count waveform(e)

Fig. 3.10 Integration of complex waveformWhen input voltage polarity is positive i.e. for the periods t (I to t I and t s to t hI the

output of the pulse generator is high. For other time period it is low. This is shown in theFig 310 (b).

When the input voltage polarity is negative i.e. for the period t 1 to t 4 the output ofthe pulse generator is high. This is due to other pulse generator used for the bipolarvoltages. This is shown in the Fig. 3.10 (c).

For the period toto t I I it is positive counting up. For the period t 1 to t} it is positivecounting down. For t 3 to t 4 negative counting up while for the period t 5 to t (, it isnegative counting down.

Transfer characteristics : The transfercharacteristics show the relation between theinput voltage and the output frequency. Thisshould be as linear as possible. It remainslinear upto a frequency called saturationfrequency. This is shown in the Fig. 3.11.

The slope of both the positive andnegative voltage characteristics must besame.

To increase the operating speed of this type of DVM, the upper frequency can beincreased i.e. increasing VI f conversion rate. But this results into reduced accuracy anddesign cost of such circuit is also very high.

Hence another method in which 5 digit resolution is available, is used to increase thespeed of operation. This is the modified version of VI f integrating type DVM and is calledinterpolating integrating DVM.

3.7.1 Interpolating Integrating DVMThe block diagram of interpolating integrating DVM is shown in the Fig. 3.12.

This is a modified version of V If integrating DVM. A zero comparator is theadditional circuitry in the DVM. The zero comparator ensures that the charge on thecapacitor is zero.

During first 20 msec, the operation is exactly similar to the normal V If integratingDVM. However during this time the pulses are directed to the 100 s decade. Here eachpulse is equivalent to the 100 counts.

After 20 msec, the switch SI is moved from position 1 to 2 and Vrer otoppositepolc1l'ity is offered. Some charge is still present on the capacitor. The opposite polarity Vrerhelps to remove the remaining charge at a constant rate. When the charge reaches zero,the zero comparator provides a pulse to the control logic. When the switch is moved fromposition 1 to 2, at the same time gate G2 is also opened. Hence the pulses from 50 kHzoscillator can reach to Is decade. When the zero comparator provides a pulse, the gate G1

is closed. This completes the reading operation.

SwitchInput 1 S1 R1

voltage 04-"2(Vref

The potentiometer used in the servo balancing type DVM is a linear divider but insuccessive approximation type a digital divider is used. The di ital divider is nothing butcl digital to analog (DJ A) converter. The servomotor is replaced by an electronic logic.

The basic principle of measurement by this method is similar to the simple example ofdetermination of weight of the object. The object is placed on one side of the balance andthe approximate weight is placed on other side. If weight placed is more, the weight IS

removed and smaller weight is placed. If this weight is smaller than the object, anothersmall weight is added, to the weight present. If now the total weight is higher than theobject, the added weight is removed and smaller weight is added. Thus by such successiveprocedure of adding and removing, the weight of the object is determined. The slIccessiveapproximation type DVM works exactly on the same principle.

In successive approximation type DVM, the comparator compares the output of digitalto an,llog converter with the unknown voltage. Accordingly, the comparator provides logichigh or low signals. The digital to analog converter successively generates the set patternof signals. The procedure continues till the output of the digital to analog converterbecomes equal to the unknown voltage.

The Fig. 3.13 shows the block diagram of successive approximation type DVM.

• 0Unknown )voltage (Vin

'~I

2 II

1- - - - Clock

Digilalloanalog

converter

Logic controland sequencer

'-"-"-11-' Digital• "_" 11-' display

Fig. 3.13 Successive approxi.mation type DVMThe capacitor is connected at the input of the comparator. The output of the digital to

analog converter is compared with the unknown voltage, by the comparator. The output ofthe comparator is given to the logic control and sequencer. This unit generates thesequence of code which is applied to digital to analog converter. The position 2 of theswitch 51 receives the output from digital to analog converter. The unknown voltage isavaihlble at the position 1 of the switch S1. The logic control also drives the clock which isused to alternate the switch S1 between the positions 1 and 2, as per the requirement.

Consider the voltage to be measured is 3.7924 V. The set pattern of digital to analogconverter is say 8-4-2-1. At the start, the converter generates 8 V and switch is at theposition 2. The capacitor C, charges to 8 V. The clock is used to change the switchposition. So during next time interval, switch position is 1 and unknown input is applied

to the capacitor. As capacitor is charged to 8 V which is more than the input voltage3.7924 V, the comparator sends HIGH signal to the logic control and sequencer circuit.This HIGH signal resets the digital to analog converter which generates its next step of 4V. This again generates HIGH signal. This again resets the converter to generate the nextstep of 2 V.

Now 2 V is less than the input voltage. The comparator generates LOW signal andsends it to logic control and sequence circuit. During the generation of LOW signal, thegenerated signal by the converter is retained. Thus the 2V step gets stored in theconverter. In addition to this, next step of 1 V is generated. Thus the total vo.l~~gelevelbecomes, stored 2 + generated 1 i.e. 3 V. This is again less than the input and generatesLOW signal. Due to low signal, this gets stored. After this 0.8 V step is generated for thesecond digit approximation.

Thus the process of successive approximation continues till the converter generates3.7924 V. This voltage is then displayed on the digital display.

At each low signal, there is an incremental change in the output of the digital toanalog converter. This output voltage approaches the value of the unknown voltage. Thelimit to how close this output can approach to the unknown voltage, depends on the levelof noise at the input of comparator and the stability of the input switch. To reduce thenoise, filters may be used but it reduces the speed of measurement. These limiting factorsusually determine the number of digits of resolution of an instrument. The general rangeof digits is 3 to 5. The speed depends upon the type of switches used in digital to analogconverter and comparator circuitry. If solid state switches are used, the high speed can beobtained. For electromechanical switches, the speed is few readings per second. Theaccuracy depends on the internal reference supply associated with the digital to analogconverter and the accuracy of the converter itself.

3.8.1 AdvantagesThe advantages of successive approximation DVM are,

1. Very high speed of the order of 100 readings per second possible.

2. The method of ADC is inexpensive.

3. The resolution upto 5 significant digits is possible.4. The accuracy is high.

3.8.2 DisadvantagesThe disadvantages of successive approximation DVM are,

1. The circuit is complex.2. The DAC is also required.

3. The input impedance is variable.

4. The noise can cause error due to incorrect decisions made by comparator.

3.9 3· ~ and 4 . ~ Digit

o to 9Oor1~

I: 1111 :11: :11: :1Three full

digits

Fig. 3.14 3 • ~ digit display

The resolution of digital meters depends on thenumber of digits used in the display. The three digitdisplay for 0-1 V range can indicate the values from 0to 999 mV with the smallest increment of 1 mV.

Practically one more digit which can display onlya or 1 is added. This digit is called half digit and

display is ca~led 3 - ~ digit display. This IS shown in

the Fig. 3.14.

Tn such a display the meter can read the values above 999 upto 1999, to give theoverlap between the ranges for convenience. This process is called over-ranging.

In case of 4 - ~ digit display, there are 4 full digits and 1 half digit. The number

obtilined is from a to 19999. For this operation the time period required for countingopcriltion should be reduced. This can be achieved by changing the frequency of the clock

signaL The wave shaping and amplifier circuitry should be more accurate for 4 - ~ digit

display. It is necessary to add one more BCD counter, latch, BCD to 7 segment decoder

and 7 segment display unit. The resolution of 4 -~ digit display is better than 3 - ~ digit

display while the accuracy is 10 times better.

1Ion

Thus for 3 digit display, n = 3

1R = - = 10-3 = 0,001 or o.n;,103

The sensitivity is the smallest change in the input which a digital meter should be ableto detect. Hence, it is the full scale value of the lowest range multiplied by the resolutionof thE meter.

(fs)min = Full scale value on minimum range.

R Resolution expressed as decimal.

llI. Example 3.1 : What is the resolution of a 3 - ~ digit display on 1 V t7nd 50 V

ranges 7

Solution : The number of full digits are n = 3

R = _1_ = 0.00110 ~

Thus meter cannot distinguish between the values that differ from each other bv lessthan 0.001 of full scale.

Thus for 1 V range, the resolution is 1 x 0.001 = 0.001 V

while for 50 V range, the resolution is 50 x 0.001 = 0.05 V.

Thus on 50 V range, the meter cannot distinguish between the readings that differ byless than 0.05 V.

llI. Example 3.2 : A voltmeter uses 4 - ~ digit display. i) Find its resolution ii) How would

the 11.87 V be displayed on a 10 V range? iii) How would 0.5573 be displayed 011 1V and10 V ranges 7

Solution : i) For 4 ~ digit display the full digits are n = 4

1R = - = 0.0001

104

ii) There are 5 digit places in 4 - ~ digits hence 11.87 would be displayed as 11.870.

iii) Resolution on IV range is IV x 0.0001 = 0.0001 V

Hence any reading upto 4th decimal can be displayed.

Hence 0.5573 will be displayed as 0.5573

But resolution on 10 V range is 10 V x 0.0001 = 0.001 V

Hence decimals upto the 3rd place can be displayed.

Therefore on 10 V range, the reading will be displayed as 0.557 rather than 0.5573.

))1. Example 3.3 : A 3 - ~ digit DVM has an accuracy specification of ± 0.5'?;, of the

reading ± 1 digit. i) What is the error in volts, when the reading is 5.00 V on its 10 Vrange. ii) What is the % error of reading, when the reading is 0.10 V on its 10 V range?