chapter 10 boundary scan and core -based testing -...
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VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 1
Chapter 10 Chapter 10
Boundary Scan and Boundary Scan and
CoreCore--Based TestingBased Testing
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VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 2
OutlineOutline
� Introduction
� Digital Boundary Scan (1149.1)
� Boundary Scan for Advanced Networks (1149.6)
� Embedded Core Test Standard (1500)
� Comparison between 1149.1 and 1500
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VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 3
Boundary ScanBoundary Scan� Original objective: board-level digital testing
� Now also apply to:
� MCM and FPGA
� Analog circuits and high-speed networks
� Verification, debugging, clock control, power
management, chip reconfiguration, etc.
� History:
� Mid-1980: JETAG
� 1988: JTAG
� 1990: First boundary scan standard – 1149.1
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Boundary Scan FamilyBoundary Scan Family
Std. 1149.6-2003High-speed network interface1149.6
Std. 1149.5-1995
(not endorsed by
IEEE since 2003)
Standard module test and
maintenance (MTM) bus
1149.5
Std. 1149.4-1999Mixed-signal test bus1149.4
DiscontinueDirect access testability interface1149.3
DiscontinueExtended digital serial interface1149.2
Std. 1149.1-2001Digital chips and interconnects
among chips
1149.1
StatusMain targetNo.
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CoreCore--Based SOC DesignBased SOC Design
ADC
DAC
PLL
RAM RAMROM
DSP
BUS &
INTERCONNECT
CPU
ASIC 1
ASIC
2
GLUE LOGIC
IP 1
IP 2
RAM
ROM
ASIC
ASIC
ALUDSP
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VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 6
Digital Boundary Scan Digital Boundary Scan –– 1149.11149.1
� Basic concepts
� Overall test architecture & operations
� Hardware components
� Instruction register & instruction set
� Boundary scan description language
� On-chip test support
� Board/system-level control architectures
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VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 7
Basic Idea of Boundary Scan Basic Idea of Boundary Scan
Internal
Logic
Boundary-scan cell
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VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 8
A Board Containing 4 ICA Board Containing 4 IC’’s with s with
Boundary Scan Boundary Scan
Internal
Logic
Internal
Logic
Internal
Logic
Internal
Logic
Boundary-scan cell Boundary-scan chain
System interconnect
Serial
Data in
Serial
Data out
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VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 9
1149.1 Boundary1149.1 Boundary--Scan Architecture Scan Architecture
Internal
Logic
Internal Registers
Bypass Register
Miscellaneous Register
Instruction Register
TAP
Controller
1
1
1
Boundary-Scan Register
(consists of boundary
Scan cells)
Test Data In (TDI)
Test Mode Select (TMS)Test Clock (TCK)
Test Reset (TRST*) (optional)
Test Data Out (TDO)
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VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 10
Hardware Components of 1149.1Hardware Components of 1149.1
� A test access port (TAP) consisting of : � 4 mandatory pins: Test data in (TDI), Test data out (TDO),
Test mode select (TMS), Test clock (TCK), and
� 1 optional pin: Test reset (TRST)
� A test access port controller (TAPC)
� An instruction register (IR)
� Several test data registers� A boundary scan register (BSR) consisting of boundary
scan cells (BSCs)
� A bypass register (BR)� Some optional registers (Device-ID register, design-
specified registers such as scan registers, LFSRs for BIST, etc.)
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VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 11
Basic OperationsBasic Operations
1. Instruction sent (serially) through TDI into
instruction register.
2. Selected test circuitry configured to respond to
the instruction.
3. Test pattern shifted into selected data register
and applied to logic to be tested
4. Test response captured into some data register
5. Captured response shifted out; new test pattern
shifted in simultaneously
6. Steps 3-5 repeated until all test patterns are
applied.
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VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 12
BoundaryBoundary--Scan Circuitry in A Chip Scan Circuitry in A Chip
TDOTDI
TRST*TMSTCK
Design-Spec. Reg.
Device-ID Reg.
Boundary Scan Reg.
Bypass Reg. (1-bit)
Instruction Register
IR decode
Data Register
MUX
MUX
0
11D
ENTA
PClockDR, ShiftDR, UpdateDR
3
Reset*
ClockIR, ShiftIR, UpdateIR
3
T
A
PC
SelectTCK Enable
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Data registersData registers
� Boundary scan register: consists of boundary scan cells
� Bypass register: a one-bit register used to pass test signal from a chip when it is not involved in current test operation
� Device-ID register: for the loading of product information (manufacturer, part number, version number, etc.)
� Other user-specified data registers (scan chains, LFSR for BIST, etc.)
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VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 14
A Typical BoundaryA Typical Boundary--Scan Cell (BSC)Scan Cell (BSC)
� Operation modes� Normal: IN → OUT (Mode = 0)� Shift: TDI → ... → IN → OUT → ... → TDO (ShiftDR = 1, ClockDR)� Capture: IN → R1, OUT driven by IN or R2 (ShiftDR = 0, ClcokDR)� Update: R1 → OUT (Mode_Control = 1, UpdateDR)
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TAP ControllerTAP Controller
� A finite state machine with 16 states
� Input: TCK, TMS
� Output: 9 or 10 signals included ClockDR, UpdateDR, ShiftDR, ClockIR, UpdateIR, ShiftIR, Select, Enable, TCK and TRST* (optional).
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State Diagram of TAP ControllerState Diagram of TAP Controller
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Main functions of TAP controllerMain functions of TAP controller
� Providing control signals to
� Reset BS circuitry
� Load instructions into instruction register
� Perform test capture operation
� Perform test update operation
� Shift test data in and out
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VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 18
States of TAP ControllerStates of TAP Controller
� Test-Logic-Reset: normal mode
� Run-Test/Idle: wait for internal test such as BIST
� Select-DR-Scan: initiate a data-scan sequence
� Capture-DR: load test data in parallel
� Shift-DR: load test data in series
� Exit1-DR: finish phase-1 shifting of data
� Pause-DR: temporarily hold the scan operation (e.g., allow the bus master to reload data)
� Exit2-DR: finish phase-2 shifting of data
� Update-DR: parallel load from associated shift registers
Note: Controls for IR are similar to those for DR.
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Instruction SetInstruction Set
� BYPASS
� Bypass data through a chip
� SAMPLE
� Sample (capture) test data into BSR
� PRELOAD
� Shift-in test data and update BSR
� EXTEST
� Test interconnection between chips of board
� Optional
� INTEST, RUNBIST, CLAMP, IDCODE, USERCODE,
HIGH-Z, etc.
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Execution of BYPASS InstructionExecution of BYPASS Instruction
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VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 21
Execution of SAMPLE InstructionExecution of SAMPLE Instruction
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VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 22
Execution of PRELOAD InstructionExecution of PRELOAD Instruction
R1 R2R1 R2
Internal
Logic
TDI TDO
Output
Input
PRELOADM
U
X
M
U
X
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VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 23
Execution of EXTEST Instruction (1/3)Execution of EXTEST Instruction (1/3)
� Shift-DR (Chip1)
Internal
Logic
Registers
TAP controller
TDI TDO
Internal
Logic
Registers
TAP controller
TDI TDO
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VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 24
Execution of EXTEST Instruction (2/3)Execution of EXTEST Instruction (2/3)
� Update-DR (Chip1)
� Capture-DR (Chip2)
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� Shift-DR (Chip2)
Internal
Logic
Registers
TAP controller
TDI TDO
Internal
Logic
Registers
TAP controller
TDI TDO
Execution of EXTEST Instruction (3/3)Execution of EXTEST Instruction (3/3)
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� Shift-DR
Execution of INTEST Instruction (1/4)Execution of INTEST Instruction (1/4)
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� Update-DR
Execution of INTEST Instruction (2/4)Execution of INTEST Instruction (2/4)
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� Capture-DR
Internal
Logic
Registers
TAP controller
TDI TDO
Execution of INTEST Instruction (3/4)Execution of INTEST Instruction (3/4)
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� Shift-DR
Internal
Logic
Registers
TAP controller
TDI TDO
Execution of INTEST Instruction (4/4)Execution of INTEST Instruction (4/4)
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Boundary Scan Description Boundary Scan Description
Language (BSDL)Language (BSDL)� Now a part of IEEE 1149.1-2001
� Purposes:� Provide standard description language for BS devices.
� Simplify design work for BS – automated synthesis is possible.
� Promote consistency throughout ASIC designers, device
manufacturers, foundries, test developers and ATE manufacturers.
� Make it easy to incorporation BS into software tools for test generation, analysis and failure diagnosis.
� Reduce possibility of human error when employing boundary scan in a design.
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Features of BSDLFeatures of BSDL
� Describes the testability features of BS devices that are compatible with 1149.1.
� S subset of VHDL.
� System-logic and the 1149.1 elements that are absolutely mandatory need not be specified.
� Examples: BYPASS register, TAP controller, etc.
� Commercial tools to synthesize BSDL exist.
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Scan and BIST Support with Scan and BIST Support with
Boundary ScanBoundary Scan
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� Ring architecture with shared TMS
TDI
TCK
TMS
TDO
#1
TDI
TCK
TMS
TDO
#2
TDI
TCK
TMS
TDO
#N
TDI
TDO
TMS
TCK
Bus master
Application chips
Bus Master for Chips with Bus Master for Chips with
Boundary Scan (1/5)Boundary Scan (1/5)
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VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 34
� Ring architecture with separate TMS
TDI
TCK
TMS
TDO
#1
TDI
TCK
TMS
TDO
#2
TDI
TCK
TMS
TDO
#N
Bus master
Application chips
TDI
TDO
TMS1
TMS2
TMSN
TCK
Bus Master for Chips with Bus Master for Chips with
Boundary Scan (2/5)Boundary Scan (2/5)
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VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 35
� Star architecture
Bus Master for Chips with Bus Master for Chips with
Boundary Scan (3/5)Boundary Scan (3/5)
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VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 36
� Multi-drop architecture
Bus master
TDI
TMS
TCK
TDOTest Bus
Multi-Drop
DeviceMulti-Drop
Device
Multi-Drop
Device
Bus Master for Chips with Bus Master for Chips with
Boundary Scan (4/5)Boundary Scan (4/5)
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VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 37
� Hierarchical architecture
Bus Master for Chips with Bus Master for Chips with
Boundary Scan (5/5)Boundary Scan (5/5)
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Boundary scan for advanced networks Boundary scan for advanced networks ––
1149.61149.6
� Rationale
� Analog test receiver
� Digital driver logic
� Digital receiver logic
� Test access port for 1149.6
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RationaleRationale
� Advanced signaling techniques are required for multiple-mega-per-second I/O.
� Differential or AC-coupling networks
� Coupling capacitor in AC-coupled networks blocks DC signals.
� DC-level applied during EXTEST may decay to undefined logic level.
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VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 40
Capturing ACCapturing AC--Coupled Signal with 1149.1Coupled Signal with 1149.1
C U
TX RX
C U
VT
TX
RX
Update-DR
Capture-DR
VH
VL
VH
VL
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VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 41
1149.1 Configuration for Differential 1149.1 Configuration for Differential
Signaling Signaling
C U
TX RX
C U
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Analog Test Receiver Response to AC Analog Test Receiver Response to AC
and DCand DC--Coupled SignalsCoupled Signals
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Digital Driver Logic Digital Driver Logic
0
1
0
1 C U
ShiftDRShift in
ClockDR
UpdateDR
Mode
Shift out
Data
Mission
0
1
AC Mode
TCK
RTI StateAC Test Signal
(distributed to all ACdrivers)
Train/Pulse
Mode AC Mode Train/Pulse
1149.1 Bypass
1149.1 Extest
Extest_Pulse
Extest_Train
0 X X
1 0 X
1 1 0
1 1 1
AC Test Signal Generator(near TAP Controller)
AC Test SignalInsertion, per driver
D Q
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Digital Receiver LogicDigital Receiver Logic
VHyst
VHyst
Pad RF
CF
VT
DC
AC
EXTEST_PULSE
or EXTEST_TRAIN
Selected
Hyst
MemClear
Set
Shift In
Init_Memory
(common to all test receivers)
Capture
FF
Update
FF
ClockDR
0
1
ShiftDR
Shift Out
UpdateDR
0
1
Optional, Required for Observe-and-Control Capabilty on Single-Ended Inputs Only
Boundary
Register
Cell
Test
Receiver
D
EXTEST_PULSE, EXTEST_TRAIN:
Init_Memory
Latch Q
NOTE: The generated clock (Init_Memory) shown is suitable for rising edge-sensitive behavior only.
TCK
Capture-DR Shift_DR
TAP State
TMS
TCK
EXTEST:
Init_Memory
TAP State
Clock_DR
Exit*-DR Update_DR
May be located near TAP controller
TCK
Capture-DR
EXTEST
EXTEST_TRAINEXTEST_PULSE
Exit1-DRExit2-DRQ
QSET
CLR
D
L
DQ
G
TMS
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Example of Modification on 1149.1 TAP Example of Modification on 1149.1 TAP ––
Driver Behavior During EXTEST_PULSEDriver Behavior During EXTEST_PULSE
TCK
Capture PointUpdate Point
(TAP State)
Test-Logic Reset Select-DR Capture-DR
AC Test Signal
Data Inverted Data Data
Pulse Width
Update-xR Run-Test/Idle
AC Pin Driver
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Embedded Core Test Standard Embedded Core Test Standard -- 15001500
� SOC test problems
� Overall architecture
� Wrapper components and functions
� Instruction set
� Core test language
� Core test supporting and system test configurations
� Hierarchical test control and plug & play
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VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 47
� Mixing technologies: logic, processor, memory, analog
� Need various DFT/BIST/other techniques
� Deeply embedded cores
� Need Test Access Mechanism
� Hierarchical core reuse
� Need hierarchical test management
� Different core providers and SOC test developers
� Need standard for test integration
� IP protection/test reuse
� Need core test standard/documentation
SOC Test Problems/Requirements (1/2)SOC Test Problems/Requirements (1/2)
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� Higher-performance core pins than SOC pins
� Need on-chip, at-speed testing
� External ATE inefficiency
� Need “on-chip ATE”
� Long test application time
� Need parallel testing or test scheduling
� Test power must be considered
� Need lower power design or test scheduling
� Testable design automation
� Need new testable design tools and flow
SOC Test Problems/Requirements (2/2)SOC Test Problems/Requirements (2/2)
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A System Overview of IEEE 1500 A System Overview of IEEE 1500
Standard Standard
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Test Interface of A Core Wrapper Test Interface of A Core Wrapper
Core
WSC
WPI WPO
WPC
WSI WSOWrapper
Wrapper
Serial Control
Wrapper
Serial Input
Wrapper
Serial Output
Wrapper
Parallel Control
Wrapper
Parallel Input
Wrapper
Parallel Output
Required Wrapper
Serial Port (WSP)
Optional Wrapper
Parallel Port (WPP)
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Serial Test Circuitry of 1500 for a Core Serial Test Circuitry of 1500 for a Core
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Wrapper ComponentsWrapper Components
� Wrapper series port (WSP)
� Wrapper series input (WSI), Wrapper series output
(WSO), Wrapper series control (WSC)
� Wrapper parallel port (WPP) (optional)
� Wrapper parallel input (WPI), Wrapper parallel output (WPO), wrapper parallel control (WPC)
� Wrapper instruction register (WIR)
� Wrapper bypass regiester (WBY)
� Wrapper data register (WBR)
� Consists of wrapper boundary cells (WBC’s)
� Core data register (CDR) (optional)
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VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 53
Wrapper Series Control (WSC) signals Wrapper Series Control (WSC) signals
� WRCK: wrapper clock terminal
� AUXCKn: Optional auxiliary clocks, where n is the number of the clocks.
� WRSTN: wrapper reset
� SelectWIR: determine whether WIR is selected
� CaptureWR: enable Capture operation
� ShiftWR: enable Shift operation
� UpdateWR: enable Update operation
� TransferDR: enable Transfer operation
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Wrapper Instruction RegisterWrapper Instruction Register
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Wrapper Boundary Register (WBR)Wrapper Boundary Register (WBR)
� Consists of Wrapper boundary cells (WBC’s)
� WBC
� Terminals: Cell functional input (CFI), cell
functional output (CFO), cell test input (CTI), cell
test output (CTO)
� Functional modes: Normal, inward facing, outward
facing, nonhazardous (safe).
� Operation events: Shift, capture, update, transfer,
apply.
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Events of WBR (WBC)Events of WBR (WBC)
� Shift: data advance one-bit forward on WBR’sshift path
� Capture: data on CFI or CFO are captured and stored in WBC
� Update: data stored in WBC’s shift path storage are loaded into an off-shift-path storage of the WBC
� Transfer: move data to the storage closest to CTI or one bit closer to CTO
� Apply: a derivative event inferred from other events to apply data to functional inputs of cores or functional outputs of WBR
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Four Symbols Used in Bubble Diagrams for Four Symbols Used in Bubble Diagrams for
WBCWBC’’ss
Storageelement
Datapath
Decisionpoint
Data pathsfrom a source
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Some Typical Some Typical WBCWBC’’ss Represented by Represented by
Bubble DiagramsBubble Diagrams
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Example 10.1 Example 10.1 -- WIR Interface of WBY, WIR Interface of WBY,
WBR WBR WDR(sWDR(s) and ) and CDR(sCDR(s))
WIR
Circu
itry
WBY_Cntrl
WBR_Cntrl
DR_Select[n:0]
CDR_Cntrl
WDR_Cntrl
Core_Cntrl
WSI
{SelectWIR,
WRCK,
WRSTN,
CaptureWR,
ShiftWR,
UpdateWR}
WBR
CDR k
WBY
WDR k
DR_WSO
DR_Select[n:0]
SelectWIR
WIR_WSO
WSO
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Example 10.2 Example 10.2 -- Schematic Diagram of Schematic Diagram of
WBC WC_SD2_CIOWBC WC_SD2_CIO
CFO
MODE
D2
D1
WRCKIO_FACE
CAPT
CFI
XFER
CTISHIFT WRCK
CTO
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WS_BYPASS InstructionWS_BYPASS Instruction
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WS_EXTEST InstructionWS_EXTEST Instruction
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WP_EXTEXT InstructionWP_EXTEXT Instruction
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WS_SAFE InstructionWS_SAFE Instruction
WSO
Disabled
Core
FO
FI
WSC
FO
FI
W
B
R
W
B
R
Safe States
Safe States
WSIWIR
Bypass
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WS_PRELOAD InstructionWS_PRELOAD Instruction
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WP_PRELOAD InstructionWP_PRELOAD Instruction
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WS_CLAMP InstructionWS_CLAMP Instruction
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WS_INTEST InstructionWS_INTEST Instruction
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WS_INTEST_SCAN InstructionWS_INTEST_SCAN Instruction
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General Parallel TAM StructureGeneral Parallel TAM Structure
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Multiplexed TAM Architectures Multiplexed TAM Architectures
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Daisy chained TAM ArchitectureDaisy chained TAM Architecture
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Direct Access TAM ArchitecturesDirect Access TAM Architectures
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Local Controller TAM ArchitecturesLocal Controller TAM Architectures
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Core Access Switch (CAS) ArchitectureCore Access Switch (CAS) Architecture
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Different Functional Modes of CASDifferent Functional Modes of CAS
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Various Types of Test Supporting Various Types of Test Supporting
Using CAS StructureUsing CAS Structure
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A Hierarchical Test Architecture A Hierarchical Test Architecture
Supporting Plug & Play FeatureSupporting Plug & Play Feature
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Detailed I/O and CTC of The Detailed I/O and CTC of The
Hierarchical Test ArchitectureHierarchical Test Architecture
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A Hierarchical Test Architecture with I/Os A Hierarchical Test Architecture with I/Os
Compatible to 1149.1Compatible to 1149.1
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Comparison between 1149.1 and 1500Comparison between 1149.1 and 1500
NoYesLatency between
operations
YesNoTransfer Mode
YesNoParallel Mode
WS_EXTEST, WS_BYPASS,
one Wx_INTEST,
WS_PRELOAD (cond. required)
EXTEST, BYPASS,
SAMPLE, PRELOAD
Mandatory
Instructions
NoYesFSM
Mandatory: WSI, WSO, 6 WSC
Optional: TransferDR, WPP,
AUXCKn(s)
Mandatory: TDI, TDO,
TMS, TCK
Optional: TRST
Extra Data/Control
I/Os
Core-basedBoard-level Purpose
15001149.1