CHAPTER 3IMPLEMENTATION OF DWT BASED WIBRO MODELIn this the problem of Bit Error Rate (BER) is addressed by replacing IFFT/FFT transformation with IDWT/DWT Transformation in orthogonal Frequency division multiplexing block at transmitter and receiver. This improves the Signal to noise ratio (SNR) of the overall system to an acceptable limit. 3.1 Proposed DWT based WiBro Model

Figure 3.1 General Block Diagram of WiBro with DWT 3.1.1 Data Generator

Figure 3.2 Data GeneratorThe data are the predetermined set of integers values that are known between transmitter and the receiver side in order to calculate the performance of the system both the input data and the received data are compared and the BER is calculated for a specific given SNR in additive white Gaussian noise channel. The Integer to bit converter Maps a vector of integer-values inputs to a vector of bits. Block inputs must be integer values in the range [-2(M-1), 2(M-1)-1] when they are treated as signed and [0, 2M-1] when they are treated as unsigned. For fixed-point inputs, the stored integer value is used. Thus it converts integer data in to Binary bits.

3.1.2 Randomizer The Randomizer performs randomization of input data on each burst on each allocation to avoid long sequence of continuous ones and zeros.

Figure 3.3 PRBS Generator for RandomizationThis is implemented with a Pseudo Random Binary Sequence (PRBS) generator which uses a 15 stage shift register with a generator polynomial of with XOR gates in feedback configuration as shown in Fig.3.3.

Figure 3.4 RandomizerThe PN sequence generates a pseudorandom noise (PN) sequence using a linear feedback shift register (LFSR). The LFSR is implemented using a simple shift register generator (SSRG, or Fibonacci) configuration. The 'Generator polynomial' parameter values specify the shift register connections. For the binary vector representation, the first and last elements of the vector must be 1. For the descending-ordered polynomial representation, the last element of the vector must be 0. The 'Output mask source' may be from a dialog parameter or an input port. The 'Output mask vector' is a binary vector corresponding to the shift register states that are to be XORed to produce the output sequence values. Alternatively, you may enter an integer 'scalar shit value' to produce an equivalent advance or delay in the output sequence.

3.1.3 Reed-Solomon encoder The properties of Reed-Solomon codes make them suitable to applications where errors occur in bursts. Reed Solomon error correction is a coding scheme which works by first constructing a polynomial from the data symbols to be transmitted, and then sending an oversampled version of the polynomial instead of the original symbols themselves. A Reed-Solomon code is specified as RS (n, k, t) with l-bit symbols. This means that the encoder takes k data symbols of l bits each and adds 2t parity symbols to construct an n-symbol codeword. Thus, n, k and t can be defined as: n: number of bytes after encoding; k: number of data bytes before encoding, and t: number of data bytes that can be corrected. The error correction ability of any RS code is determined by (n k), the measure of redundancy in the block. If the location of the erroneous symbols is not known in advance, then a Reed-Solomon code can correct up to t symbols, where t can be expressed as t = (n k)/2. As specified in the standard, the Reed Solomon encoding shall be derived from a systematic RS (n = 255, k = 239, t = 8) code using a Galois field specified as GF(28).

Figure 3.5 EncoderThe Reed-Solomon encoder, encodes the message in the input vector using an (N, K) with the narrow-sense generator polynomial. This block accepts a column vector input signal with an integer multiple of K elements. Each group of K input elements represents one message word to be encoded. Each symbol must have ceil (log2 (N+1)) bits. If log2 (N+1) does not equal M, where 3