CS 151: Digital Design

Chapter 3: Combinational Functions and Circuits3-5 to 3-7: Decoders

CS 151

Overview Part II Functions and functional blocks Rudimentary logic functions Decoding Encoding Selecting Implementing Combinational Functions

Using: Decoders and OR gates Multiplexers (and inverter)

CS 151

Functions and Functional Blocks

The functions considered are those found to be very useful in design

Corresponding to each of the functions is a combinational circuit implementation called a functional block.

In the past, many functional blocks were implemented as SSI, MSI, and LSI circuits.

Today, they are often simply parts within a VLSI circuits.

CS 151

Rudimentary Logic Functions Functions of a single variable X Can be used on the

inputs to functionalblocks to implementother than the block’sintended function

TABLE 4-1Functions of One Variable

X F = 0 F = X F = F = 1

01

00

01

10

11

X

0

1

F= 0

F= 1

)a(

F= 0

F= 1

VCC or V DD

)b(

X F= X)c(

X F= X

)d(

CS 151

Multiple-bit Rudimentary Functions Multi-bit Examples:

A wide line is used to representa bus which is a vector signal

In (b) of the example, F = (F3, F2, F1, F0) is a bus. The bus can be split into individual bits as shown in (b) Sets of bits can be split from the bus as shown in (c)

for bits 2 and 1 of F. The sets of bits need not be continuous as shown in (d) for bits 3, 1, and

0 of F.

F(d)

0

F31 F2

F1A F0

(a)

01

A12 3 4 F

0

(b)

4 2:1 F(2:1)2

F(c)

4 3,1:0 F(3), F(1:0)3

A A

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Enabling Function

Enabling permits an input signal to pass through to an output

Disabling blocks an input signal from passing through to an output, replacing it with a fixed value

The value on the output when it is disable can be Hi-Z (as for three-state buffers and transmission gates), 0 , or 1

When disabled, 0 output When disabled, 1 output See Enabling App in text

X FEN(a)

ENX F

(b)

CS 151

A binary code of n bits is capable of representing 2n elements.

Decoding - the conversion of an n-bit coded input to a maximum of 2n unique outputs.

Circuits that perform decoding are called decoders. Here, functional blocks for decoding are

called n-to-m line decoders, where m ≤ 2n, and generate 2n (or fewer) minterms for the n input variables

Decoding

n-to-m Line Decoder. . .n

inpu

ts

m o

utpu

ts

m <

= 2n

CS 151

1-to-2-Line Decoder

2-to-4-Line Decoder

Note that the 2-4-line made up of 2 1-to-2- line decoders and 4 AND gates.

Decoder ExamplesA D0 D1

0 1 01 0 1

(a) (b)D1 5 AA

D0 5 A=

=

A1

0011

A0

0101

D0

1000

D1

0100

D2

0010

D3

0001

(a)

D0 5 A1 A0

D1 5 A1 A0

D2 5 A1 A0

D3 5 A1 A0

(b)

A 1

A 0

=

=

=

=

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D0 = m0 = A2’A1’A0’

D1= m1 = A2’A1’A0

…etc

Decoder Examples3-to-8-Line Decoder: example: Binary-to-octal conversion.

CS 151

In general, attach m-enabling circuits to the outputs See truth table below for function

Note use of X’s to denote both 0 and 1 Combination containing two X’s represent four binary combinations

Decoder with Enable

ENA 1

A 0D0

D1

D2

D3

)b(

EN A1 A0 D0 D1 D2 D3

01111

X0011

X0101

01000

00100

00010

00001

)a(

CS 151

Decoder Expansion - Example 1 Decoders with enable inputs can be

connected together to form a larger decoder circuit.

Enable

CS 151

Decoder Expansion - Example 2 Construct a 5-to-32-line decoder using four 3-8-line

decoders with enable inputs and a 2-to-4-line decoder.

D0 – D7

D8 – D15

D16 – D23

D24 – D31

A3

A4

A0

A1

A2

2-4-line Decoder

3-8-line Decoder

3-8-line Decoder

3-8-line Decoder

3-8-line Decoder

E

E

E

E

CS 151

Decoders can implement any function! Since any function can be represented as a some-of-minterms, a decoder can be

used to generate the minterms, and an external OR gate to form their sum. A combinational circuit with n inputs and m outputs can be implemented with an n-

to-2n line decoder and m OR gates.

S(X,Y,Z)= m (1,2,4,7)

C(X,Y,Z)= m (3,5,6,7)

Number of Ones = 3

Number of Ones = 0

Number of Ones = 1

Number of Ones = 2

XYZCS00000

00101

01001

10001

01110

11010

10110

11111