EKT 121 / 4 ELEKTRONIK DIGIT 1

EKT 124 / 3 DIGITAL ELEKTRONIC 1CHAPTER 3 Counters1 One of the common requirement in digital circuits/system iscounting, both direction (forward and backward) Digital clocks and watches are everywhere, timers are found in a range of appliances from microwave ovens to VCRs, and counters for other reasons are found in everything from automobiles to test equipment. Although we will see many variations on the basic counter, they are all fundamentally very similar. The demonstration below shows the most basic kind of binary counting circuit.

INTRODUCTIONCounters can be implemented quite easily using register-type circuits such as the flip-flop, and a wide variety of classifications exist:Asynchronous (ripple) counter changing state bits are used as clocks to subsequent state flip-flopsSynchronous counter all state bits change under control of a single clockDecade counter counts through ten states per stageUp/down counter counts both up and down, under command of a control inputRing counter formed by a shift register with feedback connection in a ringJohnson counter atwistedring counterCascaded counterEach is useful for different applications

INTRODUCTION cont.INTRODUCTION cont. A counter a group of flip-flops connected together to perform counting operations. The number of flip-flops used and the way in which they are connected determine the number of states (modulus). Two broad categories according to the way they are clocked: Asynchronous counter Synchronous counterASYNCHRONOUS COUNTER

A 2-bit asynchronous binary counter.Dont have fixed time relationship with each other.Triggering dont occur at the same time.Dont have a common clock pulseThe Timing diagram

Notice that : Main clock pulse only applied to FF0. Clock for next FF, taken from previous complemented output ( Q ). All inputs (J, K) are high (Vcc).The Timing diagram

The Binary State SequenceCLOCK PULSEQ1Q0Initially001012103114 (recycles)00

0110110000Three-bit asynchronous binary counter and its timing diagram for one cycle.

The Binary State Sequence for a 3-bit Binary CounterCLOCK PULSEQ2Q1Q0Initially00010012010301141005101611071118 (recycles)000Propagation delays in a 3-bit asynchronous (ripple-clocked) binary counter.

Four-bit asynchronous binary counter and its timing diagram.

ASYNCHRONOUS DECADE COUNTER The modulus of a counter is the number of unique states that the counter will sequence through.The maximum possible number of states (max modulus) is 2n . Where n is the number of flip-flops.Counter can also be designed to have a number of states in their sequence that is less than the maximum of 2n. The resulting sequence is called truncated sequence.Counter with ten states are called decade counter.To obtain a truncated sequence it is necessary to force the counter to recycle before going through all of its possible states.An asynchronously clocked decade counter

Read example 9-2 page 465!! Modulus 12The 74LS93A 4-bit asynchronous binary counter logic diagram. (Pin numbers are in parentheses, and all J and K inputs are internally connected HIGH.)

SYNCHRONOUS COUNTER OPERATION A 2-bit synchronous binary counter.

Timing details for the 2-bit synchronous counter operation (the propagation delays of both flip-flops are assumed to be equal).

The Binary State SequenceCLOCK PULSEQ1Q0Initially001012103114 (recycles)00

0001101100A 3-bit synchronous binary counter.

The Binary State Sequence for a 3-bit Binary CounterCLOCK PULSEQ2Q1Q0Initially00010012010301141005101611071118 (recycles)000A 4-bit synchronous binary counter and timing diagram. Points where the AND gate outputs are HIGH are indicated by the shaded areas.

A 4-Bit Synchronous BCD Decade Counter.

The Binary State Sequence for BCD Decade CounterCLOCK PULSEQ3Q2Q1Q0Initially000010001200103001140100501016011070111810009100110 (recycles)0000General clocked sequential circuit :

DESIGN OF SYNCHRONOUS COUNTERSSteps used in the design of sequential circuit: Specify the counter sequence and draw a state diagramDerive a next-state table from the state diagramDevelop a transition table showing the flip-flop inputs required for each transition. The transition table is always the same for a given type of flip-flopTransfer the J and K states from the transition table to Karnaugh maps. There is a Karnaugh map for each input of each flip-flop.Group the Karnaugh map cells to generate and derive the logic expression for each flip-flop input.Implement the expressions with combinational logic, and combine with the flip-flops to create the counter.State diagram for a 3-bit Gray code counter.

0 1 3 2 6 7 5 4 0 1... Next-state table for a 3-bit Gray code counter.Present StateNext StateQ2Q1Q0Q2Q1Q0000001001011011010010110110111111101101100100000Transition Table for a J-K flip-flopOutput TransitionsFlip-flop InputsQNQN+1JK000X011X10X111X0QN : present stateQN+1: next stateX: Dont careKarnaugh maps for present-state J and K inputs.

Three-bit Gray code counter.