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cpe 252: Computer Organization 1 Lo’ai Tawalbeh Lecture #4 Register Transfer and Microoperations 23/2/2006 Chapter 4:

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  • Loai Tawalbeh Lecture #4

    Register Transfer and Microoperations 23/2/2006Chapter 4:

    ECE271 - Digital Logic Design

  • contents Register Transfer Language

    Register Transfer

    Bus and Memory Transfers

    Arithmetic Microoperations

    Logic Microoperations

    Shift Microoperations

    Arithmetic Logic Shift Unit

    ECE271 - Digital Logic Design

  • 4-1 Register Transfer Language (RTL)Digital System: An interconnection of hardware modules that do a certain task on the information.Registers + Operations performed on the data stored in them = Digital ModuleModules are interconnected with common data and control paths to form a digital computer system

    ECE271 - Digital Logic Design

  • 4-1 Register Transfer Language cont.Microoperations: operations executed on data stored in one or more registers.For any function of the computer, a sequence of microoperations is used to describe itThe result of the operation may be: replace the previous binary information of a register or transferred to another register101101110011010110111001Shift Right Operation

    ECE271 - Digital Logic Design

  • 4-1 Register Transfer Language cont.The internal hardware organization of a digital computer is defined by specifying:The set of registers it contains and their functionThe sequence of microoperations performed on the binary information stored in the registersThe control that initiates the sequence of microoperationsRegisters + Microoperations Hardware + Control Functions = Digital Computer

    ECE271 - Digital Logic Design

  • 4-1 Register Transfer Language cont. Register Transfer Language (RTL) : a symbolic notation to describe the microoperation transfers among registersNext steps: Define symbols for various types of microoperations, Describe the hardware that implements these microoperations

    ECE271 - Digital Logic Design

  • 4-2 Register Transfer (our first microoperation)Computer registers are designated by capital letters (sometimes followed by numerals) to denote the function of the registerR1: processor registerMAR: Memory Address Register (holds an address for a memory unit)PC: Program CounterIR: Instruction RegisterSR: Status Register

    ECE271 - Digital Logic Design

  • 4-2 Register Transfer cont.The individual flip-flops in an n-bit register are numbered in sequence from 0 to n-1 (from the right position toward the left position)R17 6 5 4 3 2 1 0A block diagram of a registerRegister R1Showing individual bits

    ECE271 - Digital Logic Design

  • 4-2 Register Transfer cont.PCNumbering of bitsPartitioned into two parts150PC(H)PC(L)07815Lower byteUpper byteOther ways of drawing the block diagram of a register:

    ECE271 - Digital Logic Design

  • 4-2 Register Transfer cont.Information transfer from one register to another is described by a replacement operator: R2 R1This statement denotes a transfer of the content of register R1 into register R2The transfer happens in one clock cycleThe content of the R1 (source) does not changeThe content of the R2 (destination) will be lost and replaced by the new data transferred from R1We are assuming that the circuits are available from the outputs of the source register to the inputs of the destination register, and that the destination register has a parallel load capability

    ECE271 - Digital Logic Design

  • 4-2 Register Transfer cont.Conditional transfer occurs only under a control condition

    Representation of a (conditional) transfer P: R2 R1A binary condition (P equals to 0 or 1) determines when the transfer occursThe content of R1 is transferred into R2 only if P is 1

    ECE271 - Digital Logic Design

  • 4-2 Register Transfer cont.nClockR1R2Control CircuitLoadtt+1ClockLoadTransfer occurs hereSynchronized with the clockPHardware implementation of a controlled transfer: P: R2 R1Block diagram:Timing diagram

    ECE271 - Digital Logic Design

  • 4-2 Register Transfer cont.

    ECE271 - Digital Logic Design

  • 4-3 Bus and Memory TransfersPaths must be provided to transfer information from one register to anotherA Common Bus System is a scheme for transferring information between registers in a multiple-register configurationA bus: set of common lines, one for each bit of a register, through which binary information is transferred one at a timeControl signals determine which register is selected by the bus during each particular register transfer

    ECE271 - Digital Logic Design

  • 4-3 Bus and Memory Transfers3 2 1 0Register DD3 D2 D1 D0 3 2 1 0Register CC3 C2 C1 C0 3 2 1 0Register BB3 B2 B1 B0 3 2 1 0Register AA3 A2 A1 A0 D3 C3 B3 A3 S0S1MUX33 2 1 0D2 C2 B2 A2 S0S1MUX23 2 1 0D1 C1 B1 A1 S0S1MUX13 2 1 0D0 C0 B0 A0 S0S1MUX03 2 1 04-Line Common Bus

    ECE271 - Digital Logic Design

  • 4-3 Bus and Memory TransfersThe transfer of information from a bus into one of many destination registers is done:By connecting the bus lines to the inputs of all destination registers and then: activating the load control of the particular destination register selectedWe write: R2 C to symbolize that the content of register C is loaded into the register R2 using the common system bus It is equivalent to: BUS C, (select C) R2 BUS (Load R2)

    ECE271 - Digital Logic Design

  • 4-3 Bus and Memory Transfers: Three-State Bus BuffersA bus system can be constructed with three-state buffer gates instead of multiplexersA three-state buffer is a digital circuit that exhibits three states: logic-0, logic-1, and high-impedance (Hi-Z)

    Normal input AControl input CThree-State BufferOutput B

    ECE271 - Digital Logic Design

  • 4-3 Bus and Memory Transfers: Three-State Bus Buffers cont.AC=1BABAC=0BABBufferOpen Circuit

    ECE271 - Digital Logic Design

  • 4-3 Bus and Memory Transfers: Three-State Bus Buffers cont.24 DecoderSelectEnable0123S1S0EBus line for bit 0A0B0C0D0Bus line with three-state buffer (replaces MUX0 in the previous diagram)

    ECE271 - Digital Logic Design

  • 4-3 Bus and Memory Transfers: Memory TransferMemory read : Transfer from memoryMemory write : Transfer to memoryData being read or wrote is called a memory word (called M)- (refer to section 2-7) It is necessary to specify the address of M when writing /reading memoryThis is done by enclosing the address in square brackets following the letter MExample: M[0016] : the memory contents at address 0x0016

    ECE271 - Digital Logic Design

  • 4-3 Bus and Memory Transfers: Memory Transfer cont.Assume that the address of a memory unit is stored in a register called the Address Register ARLets represent a Data Register with DR, then:Read: DR M[AR]Write: M[AR] DR

    ECE271 - Digital Logic Design

  • 4-3 Bus and Memory Transfers: Memory Transfer cont.ARx12x0Cx0Ex10x12x14x16x181934456601322R1M[AR]R1100R166RAMR1100

    ECE271 - Digital Logic Design

  • 4-4 Arithmetic MicrooperationsThe microoperations most often encountered in digital computers are classified into four categories:Register transfer microoperationsArithmetic microoperations (on numeric data stored in the registers)Logic microoperations (bit manipulations on non-numeric data)Shift microoperations

    ECE271 - Digital Logic Design

  • 4-4 Arithmetic Microoperations cont.The basic arithmetic microoperations are: addition, subtraction, increment, decrement, and shiftAddition Microoperation:R3 R1+R2Subtraction Microoperation: R3 R1-R2 or :R3 R1+R2+11s complement

    ECE271 - Digital Logic Design

  • 4-4 Arithmetic Microoperations cont.Ones Complement Microoperation:R2 R2Twos Complement Microoperation:R2 R2+1Increment Microoperation:R2 R2+1Decrement Microoperation:R2 R2-1

    ECE271 - Digital Logic Design

  • Half Adder/Full AdderHalf Adder0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1cn = xy + xcn-1+ ycn-1 = xy + (x y)cn-1

    s = xycn-1+xycn-1+xycn-1+xycn-1 = x y cn-1 = (x y) cn-1xycn-1xycn-1cnsc = xy s = xy + xy = x yxycn-1S

    cnFull Adderx y cn-1 cn s0010011101011010

    ECE271 - Digital Logic Design

  • 4-4 Arithmetic Microoperations Binary AdderC0A0B0S0A1B1S1A2B2S2A3B3S3C1C2C3C44-bit binary adder (connection of FAs)

    ECE271 - Digital Logic Design

  • 4-4 Arithmetic Microoperations Binary Adder-SubtractorC0A0B0S0A1B1S1A2B2S2A3B3S3C1C2C3C44-bit adder-subtractorM

    ECE271 - Digital Logic Design

  • 4-4 Arithmetic Microoperations Binary Adder-SubtractorFor unsigned numbers, this gives A B if AB or the 2s complement of (B A) if A < B (example: 3 5 = -2= 1110)For signed numbers, the result is A B provided that there is no overflow. (example : -3 5= -8) 1101 1011 + 1000

    C3C4V =1, if overflow0, if no overflowOverflow detector for signed numbers

    ECE271 - Digital Logic Design

  • 4-4 Arithmetic Microoperations Binary Adder-Subtractor cont.What is the range of unsigned numbers that can be represented in 4 bits?What is the range of signed numbers that can be represented in 4 bits?Repeat for n-bit?!

    ECE271 - Digital Logic Design

  • 4-4 Arithmetic Microoperations Binary IncrementerCSxyHACSxyHACSxyHACSxyHAS0S1S2S3C41A0A1A2A34-bit Binary Incrementer

    ECE271 - Digital Logic Design

  • 4-4 Arithmetic Microoperations Binary IncrementerBinary Incrementer can also be implemented using a counterA binary decrementer can be implemented by adding 1111 to the desired register each time!

    ECE271 - Digital Logic Design

  • 4-4 Arithmetic Microoperations Arithmetic CircuitThis circuit performs seven distinct arithmetic operations and the basic component of it is the parallel adderThe output of the binary adder is calculated from the following arithmetic sum:D = A + Y + Cin

    ECE271 - Digital Logic Design

  • 4-4 Arithmetic Microoperations Arithmetic Circuit cont.B03 2 1 0 S1 S041 MUXFAFAFAFACinD0D1D2D3C1C2C3CoutB010S1S0B13 2 1 0 S1 S041 MUXB110S1S0B23 2 1 0 S1 S041 MUXB210S1S0B33 2 1 0 S1 S041 MUXB310S1S0A0A1A2A34-bit Arithmetic CircuitX0Y0X1Y1X2Y2X3Y3Figure A

    ECE271 - Digital Logic Design

  • 4-5 Logic MicrooperationsThe four basic microoperationsOR MicrooperationSymbol: , +

    Gate:

    Example: 1001102 10101102 = 11101102

    P+Q: R1R2+R3, R4R5 R6 ORORADD

    ECE271 - Digital Logic Design

  • 4-5 Logic MicrooperationsThe four basic microoperations cont.AND MicrooperationSymbol:

    Gate:

    Example: 1001102 10101102 = 00001102

    ECE271 - Digital Logic Design

  • 4-5 Logic MicrooperationsThe four basic microoperations cont.Complement (NOT) MicrooperationSymbol:

    Gate:

    Example: 10101102 = 01010012

    ECE271 - Digital Logic Design

  • 4-5 Logic MicrooperationsThe four basic microoperations cont.XOR (Exclusive-OR) MicrooperationSymbol:

    Gate:

    Example: 1001102 10101102 = 11100002

    ECE271 - Digital Logic Design

  • 4-5 Logic MicrooperationsOther Logic MicrooperationsSelective-set OperationUsed to force selected bits of a register into logic-1 by using the OR operation Example: 01002 10002 = 11002

    In a processor registerLoaded into a register from memory to perform the selective-set operation

    ECE271 - Digital Logic Design

  • 4-5 Logic MicrooperationsOther Logic Microoperations cont.Selective-complement (toggling) OperationUsed to force selected bits of a register to be complemented by using the XOR operation Example: 00012 10002 = 10012

    In a processor registerLoaded into a register from memory to perform the selective-complement operation

    ECE271 - Digital Logic Design

  • 4-5 Logic MicrooperationsOther Logic Microoperations cont.Insert OperationStep1: mask the desired bitsStep2: OR them with the desired value Example: suppose R1 = 0110 1010, and we desire to replace the leftmost 4 bits (0110) with 1001 then:Step1: 0110 1010 0000 1111Step2: 0000 1010 1001 0000 R1 = 1001 1010

    ECE271 - Digital Logic Design

  • 4-5 Logic Microoperations Other Logic Microoperations cont.NAND MicrooperationSymbols: and

    Gate:

    Example: 1001102 10101102 = 11110012

    ECE271 - Digital Logic Design

  • 4-5 Logic Microoperations Other Logic Microoperations cont.NOR MicrooperationSymbols: and

    Gate:

    Example: 1001102 10101102 = 00010012

    ECE271 - Digital Logic Design

  • 4-5 Logic Microoperations Other Logic Microoperations cont.Set (Preset) MicrooperationForce all bits into 1s by ORing them with a value in which all its bits are being assigned to logic-1Example: 1001102 1111112 = 1111112Clear (Reset) MicrooperationForce all bits into 0s by ANDing them with a value in which all its bits are being assigned to logic-0Example: 1001102 0000002 = 0000002

    ECE271 - Digital Logic Design

  • 4-5 Logic MicrooperationsHardware ImplementationThe hardware implementation of logic microoperations requires that logic gates be inserted for each bit or pair of bits in the registers to perform the required logic functionMost computers use only four (AND, OR, XOR, and NOT) from which all others can be derived.

    ECE271 - Digital Logic Design

  • 4-5 Logic MicrooperationsHardware Implementation cont.S1S0012341 MUXEiAiBiThis is for one bit iFigure B

    ECE271 - Digital Logic Design

  • 4-6 Shift MicrooperationsUsed for serial transfer of dataAlso used in conjunction with arithmetic, logic, and other data-processing operationsThe contents of the register can be shifted to the left or to the rightAs being shifted, the first flip-flop receives its binary information from the serial inputThree types of shift: Logical, Circular, and Arithmetic

    ECE271 - Digital Logic Design

  • 4-6 Shift Microoperations cont.r0r1r3rn-1r0r1r2r3rn-1Shift RightShift LeftSerial InputSerial OutputSerial OutputSerial InputDetermines the shift typer2**Note that the bit ri is the bit at position (i) of the register

    ECE271 - Digital Logic Design

  • 4-6 Shift Microoperations: Logical ShiftsTransfers 0 through the serial inputLogical Shift Right: R1shr R1

    Logical Shift Left: R2shl R2The sameThe sameLogical Shift Left?0r0r1r2r3rn-1

    ECE271 - Digital Logic Design

  • 4-6 Shift Microoperations: Circular Shifts (Rotate Operation)Circulates the bits of the register around the two ends without loss of informationCircular Shift Right: R1cir R1

    Circular Shift Left: R2cil R2The sameThe sameCircular Shift Leftr0r1r2r3rn-1

    ECE271 - Digital Logic Design

  • 4-6 Shift Microoperations Arithmetic ShiftsShifts a signed binary number to the left or rightAn arithmetic shift-left multiplies a signed binary number by 2: ashl (00100): 01000An arithmetic shift-right divides the number by 2 ashr (00100) : 00010An overflow may occur in arithmetic shift-left, and occurs when the sign bit is changed (sign reversal)

    ECE271 - Digital Logic Design

  • 4-6 Shift Microoperations Arithmetic Shifts cont.Arithmetic Shift RightSign BitArithmetic Shift LeftSign Bit?0?r0r1r2r3rn-1r0r1r2r3rn-1

    ECE271 - Digital Logic Design

  • 4-6 Shift Microoperations Arithmetic Shifts cont.An overflow flip-flop Vs can be used to detect an arithmetic shift-left overflow

    Vs = Rn-1 Rn-2

    Rn-2Vs=Rn-11 overflow0 no overflow

    ECE271 - Digital Logic Design

  • 4-6 Shift Microoperations cont.Example: Assume R1=11001110, then:Arithmetic shift right once : R1 = 11100111Arithmetic shift right twice : R1 = 11110011Arithmetic shift left once : R1 = 10011100Arithmetic shift left twice : R1 = 00111000Logical shift right once : R1 = 01100111Logical shift left once : R1 = 10011100Circular shift right once : R1 = 01100111Circular shift left once : R1 = 10011101

    ECE271 - Digital Logic Design

  • 4-6 Shift Microoperations Hardware Implementation cont.A possible choice for a shift unit would be a bidirectional shift register with parallel load (refer to Fig 2-9). Has drawbacks:Needs two pulses (the clock and the shift signal pulse)Not efficient in a processor unit where multiple number of registers share a common busIt is more efficient to implement the shift operation with a combinational circuit

    ECE271 - Digital Logic Design

  • 4-6 Shift Microoperations Hardware Implementation cont.S10S10S10S10A3A2A1A0Serial Input IRSerial Input ILSelect0 for shift right1 for shift leftH3H2H1H0MUXMUXMUXMUX4-bit Combinational Circuit Shifter

    ECE271 - Digital Logic Design

  • 4-7 Arithmetic Logic Shift UnitInstead of having individual registers performing the microoperations directly, computer systems employ a number of storage registers connected to a common operational unit called an Arithmetic Logic Unit (ALU)

    ECE271 - Digital Logic Design

  • 4-7 Arithmetic Logic Shift Unit cont.0123S3S2S1S0BiAiAi+1Ai-1Select41 MUXCiCi+1One stage of arithmetic circuit (Fig.A)One stage of logic circuit (Fig.B)DiEiFishrshlOne stage of ALU

    ECE271 - Digital Logic Design