chapter 4 fault simulation

Chapter 4 Chapter 4 Fault Simulation Fault Simulation

Jin-Fu LiAd d R li bl S t (ARES) L bAdvanced Reliable Systems (ARES) Lab.

Department of Electrical EngineeringNational Central University

Jungli, Taiwan

Outline

IntroductionFault SimulationFault Simulation

Parallel Fault SimulationDeductive Fault SimulationDeductive Fault SimulationConcurrent Fault Simulation

SummarySummary

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2

Simulation

DefinitionSimulation refers to modeling of a design, its g g ,function and performance.

A software simulator is a computer pprogram; an emulator is a hardware simulatorSimulator is used for design verification

Validate assumptionsValidate assumptionsVerify logicVerify performance (timing) Verify performance (timing)


Levels of Simulation

System levelArchitecture levelArchitecture levelFunctional level/RTL levelG t / t t l l lGate/structural levelSwitch/transistor/circuit levelMixed level

S stem le el RTL le el Gate le elSystem level RTL level

Reg A Reg B

ab

Gate level

clk

Adder cz


Simulation Process

Stimuli Model

SimulatorLibrary

Response


Modeling

Modules, blocks or components described byy

Input/output (I/O) functionDelays associated with I/O signalsy / gExamples: binary adder, Boolean gate, etc.

Interconnects representInterconnects representIdeal signal carriers or ideal electrical conductorsconductors

NetlistA format (or language) that describes a design A format (or language) that describes a design as an interconnection of modules. Netlist may use hierarchy.


y

Example: Full-Adder Netlists

HA; i t b

cinputs: a, b;outputs: c, f;AND: A1, (a, b), (c);AND: A2, (d, e), (f);

a

d

e

f , ( , ), ( );OR: O1, (a, b), (d);NOT: N1, (c), (e);

bd f

HA

FA;inputs: A B C;D inputs: A, B, C;outputs: Carry, Sum;HA: HA1, (A, B), (D, E);HA: HA2 (E C) (F Sum);

HA1HA2

AB C

D E F

Sum

Carry

HA: HA2, (E, C), (F, Sum);OR: O2, (D, F), (Carry);

C


Types of Simulation

Compiled simulationApplicable to zero-delay combinational logicAlso used for cycle-accurate synchronous sequential circuits for logic verificationEfficient for highly active circuits but inefficient for low-Efficient for highly active circuits, but inefficient for low-activity circuitsHigh-level (e.g., C language) models can be used

Event-driven simulationOnly gates or modules with input events are evaluated (event means a signal change)Delays can be accurately simulated for timing verificationEfficient for low activity circuitsEfficient for low-activity circuitsCan be extended for fault simulation


Compiled Simulation

Step 1: L li bi ti l l i d d i Levelize combinational logic and encode in a compilable programming language

Step 2Step 2:Initialize internal state variables (flip-flops)

Step 3: For each input vector

Set primary input variablesRepeat (until steady-state or max. iterations)

Execute compiled codeExecute compiled codeReport or save computed variables


Event-Driven Simulation

Scheduledevents

Activitylist

2a =1c =1 0

e =1

1

0

events

c = 0

list

d, e

22

d = 0

g =1 1

2 d = 1, e = 0 f, g

4b =1 f =0

3

4 g = 0

e st

ack

g5

6 f = 1 g

Tim

e

Time, t0 4 86

7

8

f 1

1

g


8 g = 1

Time Wheel (Circular Stack)

t=0maxCurrent

time

1

2

pointer Event link-list

3

44

56

7


Efficiency of Event-Driven Simulator

Simulates events (value changes) onlySpeed up over compiled-code can be ten Speed up over compiled code can be ten times or more; in large logic circuits about 0.1 to 10% gates become active for an 0.1 to 10% gates become active for an input change

Large logicSteady 0St d 0 Large logic

block withoutactivity

y

0 to 1 event

Steady 0(no event)


Fault Simulation

Fault simulationIn general simulating a circuit in the presence In general, simulating a circuit in the presence of faults is known as fault simulation

The main goals of fault simulationThe main goals of fault simulationMeasuring the effectiveness of the test patternsGuiding the test pattern generator programGuiding the test pattern generator programGenerating fault dictionaries

O t t f f lt i l tiOutputs of fault simulationFault coverage - fraction (or percentage) of

d l d f lt d t t d b t t tmodeled faults detected by test vectorsSet of undetected faults


Elements of Fault Simulation

The fault simulation process is illustrated as below

Test SetDesignModelFault List

Fault SimulatorLibrary Fault SimulatorLibrary

The fault simulator affects the speed of

Evaluation

The fault simulator affects the speed of overall fault simulation


Fault Simulation Scenario

Circuit model: mixed-levelMostly logic with some switch-level for high-y g gimpedance (Z) and bidirectional signals

Signal states: logicg gTwo states (0, 1), three states (0, 1, X), four states (0, 1, X, Z), etc.

Timing:Zero-delay Zero delay

For combinational circuits with no feedback

Unit-delay yIt can maintain the proper sequencing of signal changes


Multiple-delay

Fault Simulation Scenario

FaultsMostly single stuck-at faultsy gSometimes stuck-open, transition, and path-delay faults; analog circuit fault simulators are not yet in common useEquivalence fault collapsing of single stuck-at f lfaultsFault dropping -- a fault once detected is d d f id ti t dropped from consideration as more vectors are simulated; fault-dropping may be suppressed for diagnosissuppressed for diagnosisFault sampling -- a random sample of faults is simulated when the circuit is large


s u ated e t e c cu t s a ge

Serial Fault Simulation

Serial fault simulation algorithm Simulate fault-free circuit and save responses. pRepeat following steps for each fault in the fault list

Modify netlist by injecting one faultSimulate modified netlist, vector by vector, comparing responses with saved responsesresponses with saved responsesIf response differs, report fault detection and suspend simulation of remaining vectors

Advantages Easy to implement; needs only a true-value simulatorLess memory is required


Serial Fault Simulation

Disadvantages Much repeated computation; CPU time p p ;prohibitive for VLSI circuits

AlternativeSimulate many faults together

Test vectors Fault-free circuit

Circuit with fault f1

Comparator f1 detected?



Comparator f2 detected?

Comparator fn detected?


Circuit with fault fn

Parallel Fault SimulationAssumptions

The simulated circuit consists of only logic gates and all gates have the same delaysgates and all gates have the same delaysSignals take only binary (0 and 1) values

Main idea Main idea Take advantage of the bit-parallelism of logical operations in a digital computeroperations in a digital computer

For a 32-bit machine word, an integer consists of a 32-bit binary vectorA logic AND or OR operation involving two words A logic AND or OR operation involving two words performs simultaneous AND or OR operations on all respective pairs of bits

Storage requirementOne word per line for two-state simulation


Speedup

If the computer word size is N, then N-1copies of faulty circuit are also generatedcopies of faulty circuit are also generated

For a total M faults in the circuit, simulation runs are then necessary

⎡ ⎤)1/( −NMsimulation runs are then necessary

Speedup over serial fault simulation about N-1N-1Disadvantages

k h b l lLacking the capability to simulate accurate rise and fall delays of signalsN t it bl f i it ith B l l i Not suitable for circuits with non-Boolean logic


An Example of Parallel Fault Sim.

Bit 0: fault-free circuitBit 0: fault free circuitBit 1: circuit with c s-a-0

Bit 2: circuit with f s-a-1

a 1 1 1

1 0 1 c s-a-0 detecteda

b c e

1 1 1 1 0 1

1 0 1

1 0 1s-a-0 g

0 0 0

s a 0

d f s-a-1 0 0 1


Deductive Fault Simulation

Simulating only the behavior of the fault-free logic circuitsfree logic circuitsNeed only one pass for each test patternll i l l i h f l i iAll signal values in each faulty circuit are

deduced from the fault-free circuit values d h i i and the circuit structure

For each test pattern, a deductive procedure is applied to all lines in a level-order (for combinational logic) from inputs to outputs


Deductive Fault Simulation

DefinitionThe fault list LA is defined as the set containing The fault list LA is defined as the set containing the name or index of every fault that produces an error on line A when the circuit is in its current logic state

Fault lists are to be propagated from PIs to the POsA fault list is generated for each signal A fault list is generated for each signal lines, and updated as necessary with every change in the logic state of the circuitchange in the logic state of the circuitList events occur when a fault list changes


An Example of Deductive Fault Sim

Consider a 4-input NOR gate with input {ABCD}={0011}, given the initial fault lists { } { }, gas show below

ALA={a,e}L {b c}A

BCD

ELB={b,c}LC={a,b,c,d}LD={a,d,f}

The faults that propagate to E are those causing E to be complemented

D { , , }

We also have to consider internal faults }&|{)('

BADCDCBAE LLLLLLLLL ∪∩∩∩∪ ≠∈==∴ ααα

producing incorrect output for the current good input


}1/,{}1/{' EdELL EE ==∴ ∪

Fault List PropagationLet I be the set of inputs of a gate with output Z, controlling value c, and inversion i. Let C be the

t f i t ith l Th f lt li t L i set of inputs with value c. The fault list LZ is computed as follows:if ( ) then φ=C )};/({}{ icZLL ⊕= ∪∪if ( ) then

else

φ=C

)}/({}){}({ icZLLL jjZ ⊕−= ∪∪∩

)};/({}{ icZLL jIj

Z ⊕=∈

∪∪

)}({}){}({ jCIj

jCj

Z−∈∈

0 f AND/NAND tControlling value: c=

0, for AND/NAND gates

1, for OR/NOR gates

inversion: i=0, for AND/OR gates

1, for NAND/NOR gates


An Example of Deductive Fault Sim

Notation: Lk is fault list for line k

L = L U L U {e/0}

kkn is s-a-n fault on line k

a

b e

1

1 1

{a/0}

{b/0, c/0}

Le = La U Lc U {e/0}= {a/0, b/0, c/0, e/0}1

b c

d

e

f

g

1

0

1{ / , / }

{b/0}

d f 0

{b/0, d/0}Lg = (Le Lf ) U {g/0}

= {a/0, c/0, e/0, g/0}

U

{b/0, d/0, f/1}

Faults detected bythe input vector


Concurrent Fault SimulationEvent-driven simulation of fault-free circuit and only those parts of the faulty circuit th t diff i i l t t f th f ltthat differ in signal states from the fault-free circuit.A li t t t i i i f th t A list per gate containing copies of the gate from all faulty circuits in which this gate differs List element contains fault ID gate differs. List element contains fault ID, gate input and output values and internal states, if anyif any.All events of fault-free and all faulty circuits are implicitly simulatedcircuits are implicitly simulatedFaster than other methods, but uses most memory


memory.

An Example of Concurrent Fault Sim

0 10

1 10

a/0 b/0 c/0 e/0

a 1

11

10

00

00

10

b c e

g

1

0

111

10

1

d f 0

1 0

00

001

100

000

0

a/0 b/0 c/0 e/0

10

011

1 11

0 1 0 0

b/0 d/0 f/1 0 1 1

0 1 0 1 1 1

b/0d/0

d/0g/0 f/1

f/1


Summary

Fault simulator is an essential tool for test d l tdevelopmentThe main goals of fault simulation

Measuring the effectiveness of the test patternsGuiding the test pattern generator programGenerating fault dictionaries

Concurrent fault simulation algorithm Concurrent fault simulation algorithm offers the best choice


chapter 4 fault simulation

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