chapter 47 i2s 8-channel 47.1 overviewrockchip.fr/rk312x trm/chapter-47-i2s-8-channel.pdf · the...

RK3128 Technical Reference Manual Rev 1.0

High Performance and Low-power Processor for Digital Media Application 1573

Chapter 47 I2S 8-channel

47.1 Overview

The I2S/PCM controller is designed for interfacing between the AHB bus and the I2S bus.

The I2S bus (Inter-IC sound bus) is a serial link for digital audio data transfer

between devices in the system and be invented by Philips Semiconductor. Now it is widely used by many semiconductor manufacturers.

Devices often use the I2S bus are ADC, DAC, DSP, CPU, etc. With the I2S

interface, we can connect audio devices and the embedded SoC platform

together and provide an audio interface solution for the system.

47.1.1 Features

Not only I2S but also PCM mode surround audio output (up to 7.1channel) and stereo input are supported in I2S/PCM controller.

Support five internal 32-bit wide and 32-location deep FIFOs, four for

transmitting and one for receiving audio data

Support AHB bus interface Support 16 ~ 32 bits audio data transfer

Support master and slave mode

Support DMA handshake interface and configurable DMA water level Support transmit FIFO empty, underflow, receive FIFO full, overflow

interrupt and all interrupts can be masked

Support configurable water level of transmit FIFO empty and receive FIFO full interrupt

Support combine interrupt output

Support 2,4,6,8 channels audio transmitting in I2S and PCM mode Support 2 channels audio receiving in I2S and PCM mode

Support up to 192kHz sample rate

Support I2S normal, left and right justified mode serial audio data transfer Support PCM early, late1, late2, late3 mode serial audio data transfer

Support MSB or LSB first serial audio data transfer

Support 16 to 31 bit audio data left or right justified in 32-bit wide FIFO Support two 16-bit audio data store together in one 32-bit wide location

Support 3 independent LRCK signals, one for receiving and two for

transmitting audio data

Support configurable SCLK and LRCK polarity Support SCLK is equivalent to MCLK divided by an even number range from

2 to 64 in master mode



47.2 Block Diagram

System

Interface

Transmit

FIFOs

Receive

FIFO

Transmitters

Receiver

Clock Generator

AHB BUSI2S BUS

dma

interface

interrupt

interface

surround

audio

output

stereo

audio

input

Fig.47-1 I2S/PCM controller (8 channel) Block Diagram

System Interface

The system interface implements the AHB slave operation. It contains not only control registers of transmitters and receiver inside but also interrupt and DMA

handshake interface.

Clock Generator

The Clock Generator implements clock generation function. The input source

clock to the module is MCLK_I2S, and by the divider of the module, the clock

generator generates SCLK and LRCK to transmitter and receiver.

Transmitters

The Transmitters implement transmission operation. The transmitters can act as

either master or slave, with I2S or PCM mode surround (up to 7.1 channel) serial audio interface.

Receiver

The Receiver implements receive operation. The receiver can act as either master or slave, with I2S or PCM mode stereo serial audio interface.

Transmit FIFOs

The Transmit FIFOs are the buffer to store transmitted audio data. Each of the

size of the four FIFOs is 32bits x 32.

Receive FIFO

The Receive FIFO is the buffer to store received audio data. The size of the FIFO

is 32bits x 32.

47.3 Function description

In the I2S/PCM controller, there are four conditions: transmitter-master &

receiver-master; transmitter-master & receiver-slave; transmitter-slave &

receiver-master; transmitter-slave & receiver-slave.



I2S Transmitter Master I2S Receiver Slave

SCLK

SD

LRCK

Fig.47-2 I2S transmitter-master & receiver-slave condition

When transmitter acts as a master, it sends all signals to receiver (slave), and

CPU control when to send clock and data to the receiver. When acting as a slave, SD signal still goes from transmitter to receiver, but SCLK and LRCK signals are

from receiver (master) to transmitter. Based on three interface specifications,

transmitting data should be ready before transmitter receives SCLK and LRCK signals. CPU should know when the receiver to initialize a transaction and when

to send data.

I2S Receiver MasterI2S Transmitter Slave

SCLK

LRCK

SCLK

Fig.47-3 I2S transmitter-slave& receiver-master condition

When the receiver acts as a master, it sends SCLK and LRCK signals to the transmitter (slave) and receives serial data. So CPU must tell the transmitter

when to start a transaction for it to prepare transmitting data then start a

transfer and send clock and channel-select signals. When the receiver acts as a slave, CPU should only do initial setting and wait for all signals and then start

reading data.

Before transmitting or receiving data, CPU need do initial setting to the I2S register. These includes CPU settings, I2S interface registers settings, and

maybe the embedded SoC platform settings. These registers must be set before

starting data transfer.

47.3.1 i2s normal mode

This is the waveform of I2S normal mode. For LRCK (i2s_lrck_rx/i2s_lrck_tx0)

signal, it goes low to indicate left channel and high to right channel. For SD (i2s_sdo0, i2s_sdo1, i2s_sdo2, i2s_sdo3, i2s_sdi) signal, it transfers MSB or

LSB first and sends the first bit one SCLK clock cycle after LRCK changes. The

range of SD signal width is from 16 to 32bits.



0 02322211 2322211 0

i2s0_sclk

i2s0_lrck_rx/

i2s0_lrck_tx0

i2s0_sdo0

0 02322211 2322211 0

0 02322211 2322211 0

0 02322211 2322211 0

0 02322211 2322211 0

Left channel Right channel

i2s0_sdo3

i2s0_sdo2

i2s0_sdo1

i2s0_sdi Fig.47-4 I2S normal mode timing format

47.3.2 i2s left justified mode

This is the waveform of I2S left justified mode. For LRCK (i2s_lrck_rx /

i2s_lrck_tx0) signal, it goes high to indicate left channel and low to right channel. For SD (i2s_sdo0, i2s_sdo1, i2s_sdo2, i2s_sdo3, i2s_sdi) signal, it transfers

MSB or LSB first and sends the first bit at the same time when LRCK changes.

The range of SD signal width is from 16 to 32bits.

0 02322211 2322211 0 1

0 02322211 2322211 0 1

0 02322211 2322211 0 1

0 02322211 2322211 0 1

0 02322211 2322211 0 1

Left channelRight channel

i2s0_sclk

i2s0_lrck_rx/

i2s0_lrck_tx0

i2s0_sdo0

i2s0_sdo3

i2s0_sdo2

i2s0_sdo1

i2s0_sdi Fig.47-5 I2S left justified mode timing format

47.3.3 i2s right justified mode

This is the waveform of I2S right justified mode. For LRCK (i2s_lrck_rx /

i2s_lrck_tx0) signal, it goes high to indicate left channel and low to right channel. For SD (i2s_sdo0, i2s_sdo1, i2s_sdo2, i2s_sdo3, i2s_sdi) signal, it transfers

MSB or LSB first; but different from I2S normal or left justified mode, its data is

aligned to last bit at the edge of the LRCK signal. The range of SD signal width is from 16 to 32bits.

0 02322211 2322211

0 02322211 2322211

0 02322211 2322211

0 02322211 2322211

0 02322211 2322211

Left channel Right channel

i2s0_sclk

i2s0_lrck_rx/

i2s0_lrck_tx0

i2s0_sdo0

i2s0_sdo3

i2s0_sdo2

i2s0_sdo1

i2s0_sdi

Fig.47-6 I2S right justified modetiming format



47.3.4 PCM early mode

This is the waveform of PCM early mode. For LRCK (i2s_lrck_rx / i2s_lrck_tx0) signal, it goes high to indicate the start of a group of audio channels. For SD

(i2s_sdo0, i2s_sdi) signal, it transfers MSB or LSB first and sends the first bit at

the same time when LRCK goes high. The range of SD signal width is from 16 to 32bits.

0 0231 231 0

i2s0_sclk

i2s0_sdo0 231 0

channel0 left channel0 right channel1 left ~ channel3 right

1

i2s0_lrck_rx

/i2s0_lrck_tx0

(slave mode)At least one sclk cycle in slave mode

Always one sclk cycle in master mode

no valid data

0 0231 231i2s0_sdi 0

channel0 left channel0 right

1

no valid data

i2s0_lrck_rx

/i2s0_lrck_tx0

(master mode)

Fig.47-7 PCM early modetiming format

47.3.5 PCM late1 mode

This is the waveform of PCM early mode. For LRCK (i2s_lrck_rx / i2s_lrck_tx0)

signal, it goes high to indicate the start of a group of audio channels. For SD (i2s_sdo0, i2s_sdi) signal, it transfers MSB or LSB first and sends the first bit

one SCLK clock cycle after LRCK goes high. The range of SD signal width is from

16 to 32bits.

0 0231 231 0 231 0


At least one sclk cycle in slave mode


0 0231 231 0

channel0 left channel0 right no valid data

no valid data

i2s0_sclk

i2s0_sdo0

i2s0_lrck_rx

/i2s0_lrck_tx0

(slave mode)

i2s0_sdi

i2s0_lrck_rx

/i2s0_lrck_tx0

(master mode)

Fig.47-8 PCM late1 modetiming format




two SCLK clock cycles after LRCK goes high. The range of SD signal width is from

16 to 32bits.



0 0231 231 0 231




0 0231 231

channel0 left channel0 right no valid data

no valid data

i2s0_sclk

i2s0_sdo0

i2s0_lrck_rx

/i2s0_lrck_tx0

(slave mode)

i2s0_sdi

i2s0_lrck_rx

/i2s0_lrck_tx0

(master mode)





three SCLK clock cycles after LRCK goes high. The range of SD signal width is

from 16 to 32bits.

0 0231 231 0 231




0 0231 231

channel0 left channel0 right no valid datano valid data

no valid datano valid data

i2s0_sclk

i2s0_sdo0

i2s0_lrck_rx

/i2s0_lrck_tx0

(slave mode)

i2s0_sdi

i2s0_lrck_rx

/i2s0_lrck_tx0

(master mode)


47.4 Register Description

This section describes the control/status registers of the design.

47.4.1 Registers Summary

Name Offset Size Reset Value Description

I2S_TXCR 0x0000 W 0x0000000f transmit operation control register

I2S_RXCR 0x0004 W 0x0000000f receive operation control register

I2S_CKR 0x0008 W 0x00071f1f clock generation register

I2S_FIFOLR 0x000c W 0x00000000 FIFO level register

I2S_DMACR 0x0010 W 0x001f0000 DMA control register

I2S_INTCR 0x0014 W 0x01f00000 interrupt control register

I2S_INTSR 0x0018 W 0x00000000 interrupt status register

I2S_XFER 0x001c W 0x00000000 Transfer Start Register



Name Offset Size Reset Value Description

I2S_CLR 0x0020 W 0x00000000 SCLK domain logic clear Register

I2S_TXDR 0x0024 W 0x00000000 Transimt FIFO Data Register

I2S_RXDR 0x0028 W 0x00000000 Receive FIFO Data Register

Notes:Size:B- Byte (8 bits) access, HW- Half WORD (16 bits) access, W-WORD (32 bits) access

47.4.2 Detail Register Description

I2S_TXCR Address: Operational Base + offset (0x0000)

transmit operation control register

Bit Attr Reset Value Description

31:23 RO 0x0 reserved

22:17 RW 0x00

RCNT right jusitified counter

(Can be written only when XFER[0] bit is 0.)

Only vailid in I2S Right justified format and slave tx mode is selected.

Start to tramsmit data RCNT sclk cycles after

left channel valid.

16:15 RW 0x0

CSR

Channel select register (Can be written only when XFER[0] bit is 0.)

0:channel 0 enable

1:channel 0 & channel 1 enable 2:channel 0 & channel 1 & channel 2 enable

3:channel 0 & channel 1 & channel 2 & channel

3 enable

14 RW 0x0

HWT

Halfword word transform (Can be written only when XFER[0] bit is 0.)

Only valid when VDW select 16bit data.

0:32 bit data valid from AHB/APB bus. Low 16 bit for left channel and high 16 bit for right

channel.

1:low 16bit data valid from AHB/APB bus, high 16 bit data invalid.

13 RO 0x0 reserved

12 RW 0x0

SJM Store justified mode


16bit~31bit DATA stored in 32 bits width fifo. If VDW select 16bit data, this bit is valid only

when HWT select 0.Because if HWT is 1, every

fifo unit contain two 16bit data and 32 bit space is full, it is impossible to choose justified

mode.

0:right justified

1:left justified




11 RW 0x0

FBM First Bit Mode


0:MSB 1:LSB

10:9 RW 0x0

IBM I2S bus mode


0:I2S normal 1:I2S Left justified

2:I2S Right justified

3:reserved

8:7 RW 0x0

PBM

PCM bus mode (Can be written only when XFER[0] bit is 0.)

0:PCM no delay mode

1:PCM delay 1 mode 2:PCM delay 2 mode

3:PCM delay 3 mode

6 RO 0x0 reserved

5 RW 0x0

TFS

Transfer format select

(Can be written only when XFER[0] bit is 0.) 0: I2S format

1: PCM format

4:0 RW 0x0f

VDW

Valid Data width

(Can be written only when XFER[0] bit is 0.) 0~14:reserved

15:16bit

16:17bit 17:18bit

18:19bit

…… 28:29bit

29:30bit

30:31bit 31:32bit

I2S_RXCR

Address: Operational Base + offset (0x0004) receive operation control register






14 RW 0x0

HWT Halfword word transform


Only valid when VDW select 16bit data. 0:32 bit data valid to AHB/APB bus. Low 16 bit

for left channel and high 16 bit for right

channel. 1:low 16bit data valid to AHB/APB bus, high 16

bit data invalid.

13 RO 0x0 reserved

12 RW 0x0

SJM Store justified mode


16bit~31bit DATA stored in 32 bits width fifo. If VDW select 16bit data, this bit is valid only

when HWT select 0.Because if HWT is 1, every

fifo unit contain two 16bit data and 32 bit space is full, it is impossible to choose justified

mode.

0:right justified 1:left justified

11 RW 0x0

FBM First Bit Mode


0:MSB 1:LSB

10:9 RW 0x0

IBM

I2S bus mode

(Can be written only when XFER[1] bit is 0.) 0:I2S normal

1:I2S Left justified

2:I2S Right justified

3:reserved

8:7 RW 0x0

PBM PCM bus mode


0:PCM no delay mode 1:PCM delay 1 mode

2:PCM delay 2 mode

3:PCM delay 3 mode

6 RO 0x0 reserved

5 RW 0x0

TFS

Transfer format select

(Can be written only when XFER[1] bit is 0.) 0:i2s

1:pcm




4:0 RW 0x0f

VDW Valid Data width


0~14:reserved 15:16bit

16:17bit

17:18bit 18:19bit

……

28:29bit

29:30bit 30:31bit

31:32bit

I2S_CKR

Address: Operational Base + offset (0x0008)

clock generation register



27 RW 0x0

MSS

Master/slave mode select

(Can be written only when XFER[1] or XFER[0] bit is 0.)

0:master mode(sclk output)

1:slave mode(sclk input)

26 RW 0x0

CKP

Sclk polarity (Can be written only when XFER[1] or XFER[0]

bit is 0.)

0: sample data at posedgesclk and drive data at negedge sclk

1: sample data at negedge sclk and drive data

at posedgesclk

25 RW 0x0

RLP

Receive lrck polarity (Can be written only when XFER[1] or XFER[0]

bit is 0.)

0:normal polartiy (I2S normal: low for left channel, high for right

channel

I2S left/right just: high for left channel, low for right channel

PCM start signal:high valid)

1:oppsite polarity (I2S normal: high for left channel, low for right

channel

I2S left/right just: low for left channel, high for right channel

PCM start signal:low valid)




24 RW 0x0

TLP Transmit lrck polarity

(Can be written only when XFER[1] or XFER[0]

bit is 0.) 0:normal polartiy

(I2S normal: low for left channel, high for right

channel I2S left/right just: high for left channel, low for

right channel

PCM start signal:high valid)

1:oppsite polarity (I2S normal: high for left channel, low for right

channel

I2S left/right just: low for left channel, high for right channel

PCM start signal:low valid)

23:16 RW 0x07

MDIV

mclk divider (Can be written only when XFER[1] or XFER[0]

bit is 0.)

Serial Clock Divider = Fmclk /

Ftxsclk-1.(mclkfrequecy / txsclk frequecy-1) 0 :Fmclk=Ftxsclk;

1 :Fmclk=2*Ftxsclk;

2,3 :Fmclk=4*Ftxsclk; 4,5 :Fmclk=6*Ftxsclk;

……

60,61:Fmclk=62*Ftxsclk; 62,63:Fmclk=64*Ftxsclk;

……

252,253:Fmclk=254*Ftxsclk; 254,255:Fmclk=256*Ftxsclk;

15:8 RW 0x1f

RSD Receive sclk divider


bit is 0.) Receive sclk divider= Fsclk/Frxlrck

0~30:reserved

31: 32fs 32: 33fs

33: 34fs

34: 35fs ……

253: 254fs

254: 255fs 255: 256fs




7:0 RW 0x1f

TSD Transmit sclk divider


bit is 0.) Transmit sclk divider=Ftxsclk/Ftxlrck

0~30:reserved

31: 32fs 32: 33fs

33: 34fs

34: 35fs

…… 253: 254fs

254: 255fs

255: 256fs

I2S_FIFOLR

Address: Operational Base + offset (0x000c) FIFO level register



29:24 RO 0x00

RFL

Receive FIFO Level Contains the number of valid data entries in

the receive FIFO.

23:18 RO 0x00

TFL3

Transmit FIFO3 Level

Contains the number of valid data entries in the transmit FIFO3.

17:12 RO 0x00

TFL2

Transmit FIFO2 Level

Contains the number of valid data entries in

the transmit FIFO2.

11:6 RO 0x00

TFL1 Transmit FIFO1 Level

Contains the number of valid data entries in

the transmit FIFO1.

5:0 RO 0x00

TFL0

Transmit FIFO0 Level Contains the number of valid data entries in

the transmit FIFO0.

I2S_DMACR Address: Operational Base + offset (0x0010)

DMA control register



24 RW 0x0

RDE

Receive DMA Enable

0 : Receive DMA disabled

1 : Receive DMA enabled





20:16 RW 0x1f

RDL

Receive Data Level This bit field controls the level at which a DMA

request is made by the receive logic. The

watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of

valid data entries in the receive FIFO is equal

to or above this field value + 1.


8 RW 0x0

TDE

Transmit DMA Enable 0 : Transmit DMA disabled

1 : Transmit DMA enabled

7:5 RO 0x0 reserved

4:0 RW 0x00

TDL

Transmit Data Level

This bit field controls the level at which a DMA request is made by the transmit logic. It is

equal to the watermark level; that is, the

dma_tx_req signal is generated when the

number of valid data entries in the TXFIFO(TXFIFO0 if CSR=00;TXFIFO1 if

CSR=01,TXFIFO2 if CSR=10,TXFIFO3 if

CSR=11)is equal to or below this field value.

I2S_INTCR

Address: Operational Base + offset (0x0014) interrupt control register



24:20 RW 0x1f

RFT

Receive FIFO Threshold When the number of receive FIFO entries is

more than or equal to this threshold plus 1,

the receive FIFO full interrupt is triggered.

19 RO 0x0 reserved

18 WO 0x0

RXOIC

RX overrun interrupt clear

Write 1 to clear RX overrun interrupt.

17 RW 0x0

RXOIE RX overrun interrupt enable

0:disable

1:enable

16 RW 0x0

RXFIE

RX full interrupt enable 0:disable

1:enable





8:4 RW 0x00

TFT Transmit FIFO Threshold

When the number of transmit FIFO (TXFIFO0

if CSR=00; TXFIFO1 if CSR=01, TXFIFO2 if CSR=10, TXFIFO3 if CSR=11) entries is less

than or equal to this threshold, the transmit

FIFO empty interrupt is triggered.

3 RO 0x0 reserved

2 WO 0x0

TXUIC

TX underrun interrupt clear

Write 1 to clear TX underrun interrupt.

1 RW 0x0

TXUIE TX underrun interrupt enable

0:disable

1:enable

0 RW 0x0

TXEIE

TX empty interrupt enable 0:disable

1:enable

I2S_INTSR Address: Operational Base + offset (0x0018)

interrupt status register



17 RO 0x0

RXOI

RX overrun interrupt

0:inactive 1:active

16 RO 0x0

RXFI RX full interrupt

0:inactive

1:active


1 RO 0x0

TXUI

TX underrun interrupt 0:inactive

1:active

0 RO 0x0

TXEI

TX empty interrupt

0:inactive 1:active

I2S_XFER

Address: Operational Base + offset (0x001c) Transfer Start Register






1 RW 0x0

RXS RX Transfer start bit

0:stop RX transfer.

1:start RX transfer

0 RW 0x0

TXS

TX Transfer start bit 0:stop TX transfer.

1:start TX transfer

I2S_CLR Address: Operational Base + offset (0x0020)

SCLK domain logic clear Register



1 RW 0x0

RXC

RX logic clear

This is a self cleard bit. Write 1 to clear all receive logic.

0 RW 0x0

TXC TX logic clear

This is a self cleard bit. Write 1 to clear all

transmit logic.

I2S_TXDR

Address: Operational Base + offset (0x0400~0x7FC)

Transimt FIFO Data Register


31:0 WO 0x00000000

TXDR

Transimt FIFO Data Register When it is written to, data are moved into the

transmit FIFO.

I2S_RXDR Address: Operational Base + offset (0x0800~0xBFC)

Receive FIFO Data Register


31:0 RO 0x00000000

RXDR

Receive FIFO Data Register

When the register is read, data in the receive FIFO is accessed.



47.5 Application Notes

Disable I2Sx transmitter by writing 0x0 to I2Sx_XFER[0]

Clear control logic by writing 0x1 to I2Sx_CLR[0]

Read I2Sx_CLR[0]

Write I2Sx_TXCR &I2Sx_CKR to config I2Sx

operation mode

Config a DMA channel for I2Sx transmitter and the destination

address is I2Sx_TXDR

Write I2Sx_DMACR to determine when to issue dma request

Enable I2Sx transmitter by writing 0x1 to I2Sx_XFER[0]

I2Sx_XFER[0] can not be disabled until the current transfer has

completed

I2Sx

Contrlloller

(8 channel)

Configuration

DMA

Controller

Configuration

I2Sx_CLR[0]= 0x1

I2Sx_CLR= 0x0

x=0

Fig.47-11 I2S/PCM controller (8 channel) transmit operation flow chart



Disable I2Sx receiver by writing 0x0 to I2Sx_XFER[1]

Clear control logic by writing 0x1 to I2Sx_CLR[1]

Read I2Sx_CLR[1]

Write I2Sx_RXCR &I2Sx_CKR to config I2Sx

operation mode

Config a DMA channel for I2Sx receiver and the source

address is I2Sx_RXDR

Write I2Sx_DMACR to determine when to issue dma request

Enable I2Sx receiver by writing 0x1 to I2Sx_XFER[1]

I2Sx_XFER[1] can not be disabled until the current transfer has

completed

I2Sx_CLR[1]= 0x1

I2Sx_CLR[1]= 0x0

I2Sx

Contrlloller

(8 channel)

Configuration

DMA

Controller

Configuration

x=0

Fig.47-12 I2S/PCM controller (8 channel) receive operation flow chart

chapter 47 i2s 8-channel 47.1 overviewrockchip.fr/rk312x trm/chapter-47-i2s-8-channel.pdf · the...

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