Chapter 6Digital System Design

242-208 Digital Systems and Logic Designs

Content

•Programmable Logic Devices (PLDs)•PLD programming•Combinational PLDs•Sequential PLDs•Field programmable gate arrays (FPGAs)

•Systematic Design•ASM methods and charts•Controller and data processor designs

•References

PLD: Why we need ?

Design is more economical to implement using a fewLarge chips than many small chips.

Design and fabrication time for VLSI chips are extremely long

PLD can be mage in large volume and PROGRAMMED toimplement large numbers of different low-volume designs

What is PLD ?An IC that contains large numbers of gates, flip-flops, etc. that can be configured by the user to perform different functions

Two PLD types which are : SPLD (Simple PLD) CPLSs (Complex PLD)

PLD programming methods: Antifuse technology Two metal layers sandwich a layer of non-conductive, amorphous silicon. When voltage is applied to this middle layer, the amorphous silicon is turned into polysilicon, which is conductive.

After

PLD programming methods: Floating gate

Used in EPROM device !!

High voltage applied to the Drain, electrons jump to gate 1

Current cannot passed since no channel for carrier charge. Potential energy is still high !!

UV light strikes electrons,causes more enough energy for electrons to jump back to the channel,The transistor starts conducting !!

PLD programming methods: SRAM

Combinational PLD:PROM Programmable Read Only Memory (PROM) :A memory device that stores data at specific locationsthat can be addressed through a set of address pins. Another view : a large array of AND gates followed by a large array of OR gates

Combinational PLD:PLA Programmable Logic Array (PAL) : Both arrays of logic AND and OR are programmable

Combinational PLD:PAL Programmable Array Logic (PAL) consists of a programmable array of AND gates that connect to a fixedarray of OR gates

The PAL structure allows any SOP expression with a defined number ofvariables to be implemented

Combinational PLD:GAL A PAL that can be reprogrammed.

Sequential PLD: Consists of combinational PLDs with a set of FFs.See the diagram of IC PAL16R8.

Sequential PLD: Implement three-bit Gray code counter using PAL16R8

Complex PLD

•Programmable PLD blocks•Programmable interconnects•Electrically erasable links

Field Programmable Gate ArrayWhy we need FPGA ?

Large complex functions(millions gates)Customised designExpensive to design (in small quantities)Hard to design and long design cyclesNot reprogrammableHigh risks

Limited complexityThousands of gatesCheap and easy to designReprogrammable

Field Programmable Gate ArrayWhy we need FPGA ?

InexpensiveEasy and rapid design PrototypingReprogrammable

Field Programmable Gate Array

Simple programmable Logic blocksMassive of programmable interconnects

FPGA architecture

FPGA CLB

Look up tableFF, registers, clock storage elementsMUX

CLBFPGA architecture

FPGA CLB with Look Up Table LUT contains memory cells to implement logic functionEach cell holds ‘0’ or ‘1’Programmed with outputs of truth tableInputs select content of one of the cells as output

What is in a LUT ?4 input – 16 outputs LUT requires 16 storage elementswith 16 latches.

FPGA CLBLarger logic functions built by connecting many CLBstogether

Programmable routingConnections routing signals between CLBsDetermined by SRAM cells

Programmable routing

Programmable routing Switch matrix

FPGA : I/O Blocks

Systematic DesignFor circuit design:

small circuit : gate-level design (truth tables, K maps, etc) large circuit : block-level design (ICs)

Larger digital systems need more abstract and systematic design techniques.Systematic design methodology :

Top-down approachPartitioningDeveloping overall architecture Detailing hardware.

Systematic Design : Top-down approach

Starting from original problem and gradually refine it towards solution.Steps for a top-down design procedure:

Specify the problem clearly (at global/top level without unnecessary details).

Break the problem into smaller sub-problems.Repeat the process until sub-problems are small

enough to be solved directly.

Systematic Design : Top-down approach

Relevant to goal-directed approach

State goal, then find sub-goals to solve main goal.Repeat until sub-goals are directly solvable.

Systematic Design : PartitioningA digital system consists of two components

A control algorithm (Controller)An architecture (Data processor)

Control unit (Controller)

Data Processor (Architecture)

Commands

Input data

External command

Status condition

Output data

ASM Algorithmic State Machine (ASM) Chart is a high-level flowchart-like notation to specify the hardware algorithms in digital systems to obtain “control” and “data processor” units.Major differences from flowcharts are:

only three box types:- 1) state box (similar to operation box), 2) decision box 3) conditional box

contains exact (or precise) timing information while flowcharts impose a relative timing order for the operations.

Components of ASM chart State box Rectangular shape One entry point and one exit point Used to specify one or more operations which could be simultaneously completed in one clock cycle.

one or more operations

statebinary code

Components of ASM chart Decision box Diamond in shapeOne entry point but multiple exit points Used to specify a number of alternative paths that can be followed.

deciding factors

deciding factors

Components of ASM chart Conditional box Rectangle with rounded cornersAlways follows a decision box and contains one or more conditional operations that are only invoked when the path containing the conditional box is selected by the decision box.

conditional operations

Example of using ASM chartInitial state

S

A 0F 0

A A + 1

A2

E 0 E 1

A3

F 1

0

0

0

1

1

1

T2

T1

T0

Init S=0 if S equal 1 { A = 0 F = 0 } increase A if A2 equal 1 { E =1 if A3 equal 1 { F = 1 } }

Register operationRegisters present in the data processor for storing and processing data. Flip-flops (1-bit registers) and memories (set of registers) are also considered as registers.The register operations are specified in either the state and/or conditional boxes, and are written in the form:

destination register function(other registers)

Timing in ASM chartsInitial state

S

A 0F 0

A A + 1

A2

E 0 E 1

A3

F 1

0

0

0

1

1

1

T2

T1

T0Precise timing is implicitly presented in ASM charts.Each state box, together with its immediately following decision and conditional boxes, occurs within one clock cycle.A group of boxes which occur within a single clock cycle is called an ASM block.

Timing in ASM chartsOperations of ASM can be illustrated through a timing diagram.Two factors which must be considered are

operations in an ASM block occur at the same time in one clock cycledecision boxes are dependent on the status of the previous clock cycle (that is, they do not depend on operations of current block)

Timing in ASM charts

A = A4A3A2A1

Initial state

S

A 0F 0

A A + 1

A2

E 0 E 1

A3

F 1

0

0

0

1

1

1

T2

T1

T0

clock 1 2 3 4 5 6

states T0 T0 T1 T1 T1 T1

input S=0 S=1 S=0

registervalues

A=0F=0

A=1

E=0

A=2

E=0

A=3

E=1

OperationsA0F0

AA+1E0

AA+1E0

AA+1E1

AA+1E1

AA+1E0

AA+1E0

AA+1E1

F1

clock 7 8 9 10 11 12 13

states T1 T1 T1 T2 T0 T0 T0

input

registervalues

A=4

E=1

A=5

E=0

A=6

E=0

A=7

E=1F=1

Operations

Digital system synthesisFrom ASM chart, we can synthesize

Controller logic (via State Table/Diagram)Architecture/Data Processor

Design of controller is determined from the decision boxes and the required state transitions.Design requirements of data processor can be obtained from the operations specified with the state and conditional boxes.

Controller synthesis procedure

Step 1: Identify all states and assign suitable codes.Step 2: Draw state diagram.Step 3: Formulate state table usingState from state boxesInputs from decision boxesOutputs from operations of state/conditional boxes.Step 4: Obtain state/output equations and draw circuit.

Controller synthesisInitial state

S

A 0F 0

A A + 1

A2

E 0 E 1

A3

F 1

0

0

0

1

1

1

T2

T1

T0 T0

T1

T2

Assign codes to states: T0 = 00 T1 = 01 T2 = 11

Presentstate inputs

Nextstate outputs

G1 G0 S A2 A3 G1+ G0

+ T0 T1 T2

0 0 0 X X 0 0 1 0 0

0 0 1 X X 0 1 1 0 00 1 X 0 X 0 1 0 1 0

0 1 X 1 0 0 1 0 1 0

0 1 X 1 1 1 1 0 1 0

1 1 X X X 0 0 0 0 1

Inputs from conditions in decision boxes. Outputs = present state of controller.

Controller synthesisDecoder + D flip-flops

-suitable for moderately large controllers.- procedure: use decoder to obtain individual states; from the state table, obtain the next-state functions by inspection.

The flip-flop input functions can be obtained directly from the state table by inspection.This is because for the D flip-flops,

the next state = flip-flop D input.Decoder is then used to provide signals to represent different states.

Controller synthesisD Q

D Q

2x4 decoder

T0

T1

T2

unused

G1

G0

?

?

clock

Given the state table:

Presentstate inputs

Nextstate outputs

G1 G0 S A2 A3 G1+ G0

+ T0 T1 T2

0 0 0 X X 0 0 1 0 0

0 0 1 X X 0 1 1 0 00 1 X 0 X 0 1 0 1 0

0 1 X 1 0 0 1 0 1 0

0 1 X 1 1 1 1 0 1 0

1 1 X X X 0 0 0 0 1

The inputs of the D flip-flops for G1 and G0 are

DG1 = T1.A2.A3 DG0 = T0.S + T1

Controller synthesis

D Q

D Q

2x4 decoder

T0

T1

T2

unused

G1

G0

clock

A2

A3

S

Data processor synthesisArchitecture is more difficult to design than controller.Nevertheless, it can be deduced from the ASM chart. In particular, the operations from the ASM chart determine:

What registers to useHow they can be connectedWhat operations to supportHow these operations are activated.

Guidelines:always use high-level unitssimplest architecture possible.

Data processor synthesisInitial state

S

A 0F 0

A A + 1

A2

E 0 E 1

A3

F 1

0

0

0

1

1

1

T2

T1

T0

Various operations are:Counter incremented (A A + 1) when state = T1.Counter cleared (A 0) when state = T0 and S = 1.E is set (E 1) when state = T1 and A2 = 1.E is cleared (E 0) when state = T1 and A2 = 0.F is set (F 1) when state = T2.

Deduce:One 4-bit register A (e.g.: 4-bit synchronous counter with clear/increment).Two flip-flops needed for E and F (e.g.: JK flip-flops).

Data processor synthesis

Controller

K

J Q

K

J Q

Clk

4-bit syn. counter A

A2

A1A2

A3

A3A4

start S

E

F

clock

CP

count

clear

T2

T1

T0

References[1] A. T. T. Choy, Lecture notes on CS1104-Computer Organization.[2] M. M. Mano, Digital Design 3rd , Prentice-Hall.[3] John Coughlan, Lecture note on Introduction to Programmable Logic Device.[4] P. Cheung, Lecture note on Programmable Logic Devices.[5] F. Floyd, Digital Fundamentals 9th Edition, Prentice-Hall.