CHAPTER 7 DESIGNING SEQUENTIAL SYSTEMS CE6. A system with one input x and one output z such that z = 1 iff x has been 1 for at least three consecutive clock times. A none, that is, the last input was 0 B one C two D three or more CE7. A system with one input x and one output z such that z = 1 at a clock time iff x is currently 1 and was also 1 at the previous two clock times. CE7#. A Mealy system with one input x and one output z such that z = 1 iff x has been 1 for three consecutive clock times. A none, that is, the last input was 0 B one C two or more Design a Mealy system with one input x and one output z such that z = 1 iff x has been 1 for exactly three consecutive clock times. A sample input/output trace for such a system is x z A none, that is, the last input was 0 B one 1 in a row C two 1s in a row D three 1s in a row E too many (more than 3) 1s in a row Design a Moore system with one input, x, and one output z such that z = 1 iff x has been 1 for exactly three consecutive clock times. x z CE8. Design a Moore system whose output is 1 iff three consecutive 0 inputs occurred more recently than three consecutive 1 inputs. A sample input/output trace for such a system is x z? ? ? CE11. Design a Moore model bus controller that receives requests on separate lines, R 0 to R 3, from four devices desiring to use the bus. It has four outputs, G 0 to G 3, only one of which is 1, indicating which device is granted control of the bus for that clock period. The low number device has the highest priority, if more than one device requests the bus at the same time. We look at both interrupting controllers (where a high priority device can preempt the bus) and one where a device keeps control of the bus once it gets it until it no longer needs it. The bus controller has five states: A: idle, no device is using the bus B: device 0 is using the bus C: device 1 is using the bus D: device 2 is using the bus E: device 3 is using the bus