chapter 7 dft turboscan 2003 7
TRANSCRIPT
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Chip Implementation Center (CIC)National Applied Research
Laboratories Hsinchu, Taiwan
Design for TestabilityDesign for Testability
陳正斌 (03)5773693#157
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AgendaAgendaAgendaAgenda Logic Testing
Basic Concept Design for Testability RTL Rule Checker DFT Guidelines and Rules Synopsys DFT Design Flow
Memory Testing Basic Concept Memory BIST SynTest SRAMBIST Flow
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Chapter 1Chapter 1
Logic Testing Logic Testing
Chapter 1Chapter 1
Logic Testing Logic Testing
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Basic ConceptBasic Concept Basic ConceptBasic Concept
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What is TestingWhat is TestingWhat is TestingWhat is Testing Testing is a process of determining whether a
device is good (function correctly) or not
Testing includes test pattern generation, application and output evaluation
DUT
Compare Output(Response)
Compare Output(Response)
Apply Input(Stimulus)
Apply Input(Stimulus)
Test PatternTest Pattern
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Why TestingWhy TestingWhy TestingWhy Testing In order to guarantee the product quality,
reliability, performances, etc.
Cost is the most important.
The rule of ten
Defect detected during IC testing
Defect detected during system testing
Defect detected during field testing
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Simplified IC Production FlowSimplified IC Production FlowSimplified IC Production FlowSimplified IC Production Flow
Wafer Probe Test
Final Test PackagingMarking
QA Sample Test Shipping
Design
Process
Layout Specification
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Verification v.s. Test (1/2)Verification v.s. Test (1/2)Verification v.s. Test (1/2)Verification v.s. Test (1/2) Design verification ensures “design” matches
intent
Manufacturing test ensures “parts” are manufactured correctly
How is manufacturing test performed ?
Device Under Test (DUT)
Test Pattern (Test Problem)
Good
FailTester (ATE)
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Verification v.s. Test (2/2)Verification v.s. Test (2/2)Verification v.s. Test (2/2)Verification v.s. Test (2/2)
always @(a or b) begin c = a & b end
Design Synthesis Manufacture
TestVerificationVerification
Diagnosis
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Automatic Test EquipmentAutomatic Test EquipmentAutomatic Test EquipmentAutomatic Test Equipment Tester (ATE)
Key features to be aware of Number of pins Number of clocks Frequency Accuracy Precision Number of scan channels Amount of memory Vector application formats … … …
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Type of TestingType of TestingType of TestingType of Testing On Wafer Test
Characterization Test
Production Test
Burn-In Test
Diagnostic Test
… … …
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Test ItemsTest ItemsTest ItemsTest Items Function Test
Verify functionality
Structural Test Verify manufacturability
Parametric Test Verify AC and DC parameters
At-Speed Test Verify performance
Leakage Test Defects may cause high leakage current
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Pins/GatesPins/GatesPins/GatesPins/Gates
TTL logic allowed easy access to individual gates.
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
1.E+08
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02
Year
Tra
ns
isto
rs
8080
286
Pentium486
386Pins / Gates << 0.001Hard to access to a chip.
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What is Fault & Fault ModelWhat is Fault & Fault ModelWhat is Fault & Fault ModelWhat is Fault & Fault Model Fault is a physical defect in a circuit or system
Fault model is the logical effect of a fault (physical defect) Reduce the test complexity Independent of technology
OutputShorted
to 1
I nputShorted
to 0
IN OUT
GROUND
POWER
I nputOpen
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Yield & Fault CoverageYield & Fault CoverageYield & Fault CoverageYield & Fault Coverage Yield (Y) is the ratio of the number of good dies
per wafer to the number of dies per wafer
Y = (# of good dies) / (# of all dies)
Fault coverage (FC) is the measure of the ability of a test set to detect a given class of faults that may occur on the device under test (DUT)
FC = (# of detected faults) / (# of possible faults)
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Defect Level & Fault CoverageDefect Level & Fault CoverageDefect Level & Fault CoverageDefect Level & Fault Coverage Defect level (DL) is the fraction of devices that
pass all the tests and are shipped but still contain some faults DL = 1-Y(1-FC) [Williams and Brown 1981]
Defect level is measured in terms of DPM (detects per million), and typical requirement is less than 200 DPM i.e. 0.02 %
Y (%) 10 50 90 95 99
FC(%) 99.99 99.97 99.8 99.6 98
DL = 200 DPM
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Defect Level & QualityDefect Level & QualityDefect Level & QualityDefect Level & Quality
0
10
20
30
40
50
60
70
80
90
10,000 1,000 100
40 Chips
200 Chips
Defect Level (DPM)
Board Failing Probability (%)
99.99 99.9 99 9010
100
1,000
10,000
Chip Defect Level (DPM)
Fault Coverage
Y = 90%Y = 50%
Data Source: Prof. Ed. McCluskey 1988, 1998
High fault coverage minimizes DPM
High fault coverage is imperative when yield is low
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The Testing ProblemThe Testing ProblemThe Testing ProblemThe Testing Problem Given a set of faults in a device under test (DUT),
how to obtain a small number of test patterns which detects high fault coverage ?
What faults to test ? (fault modeling) How are the test patterns obtained ? (test pattern
generation) How is the test quality (fault coverage) measure ?
(fault simulation) How are test patterns applied and results
evaluated ? (ATE/BIST)
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Fault Model (1/3)Fault Model (1/3)Fault Model (1/3)Fault Model (1/3) Single stuck-at fault
A line (gate input/output) in the circuit is fixed at logic 0 or logic 1 and independent of other signal values
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Fault Model (2/3)Fault Model (2/3)Fault Model (2/3)Fault Model (2/3) Multiple stuck-at fault
several stuck-at faults occur at the same time
Bridging fault Two or more normally distinct adjacent lines are
shorted together
Other fault models
Single stuck-at fault is the most popular reduce the complexity of testing single stuck-at fault cover a lot of multiple stuck-at
fault
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Fault Model (3/3)Fault Model (3/3)Fault Model (3/3)Fault Model (3/3)
95 %
5 %
Good Fail
Fault Model
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Fault Simulation (1/2)Fault Simulation (1/2)Fault Simulation (1/2)Fault Simulation (1/2) To evaluate the quality of a test set
i.e. to compute its fault coverage
Reduce the time of test pattern generation A pattern usually detected multiple faults Fault simulation is used to compute the faults
accidentally detected by a particular pattern
To generate fault dictionary For post test diagnosis
To analyze the reliability of a circuit
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Fault Simulation (2/2)Fault Simulation (2/2)Fault Simulation (2/2)Fault Simulation (2/2)
Primary Inputs (PIs)Primary Outputs (POs)
Patterns(Sequences)(Vectors)
Response Comparison
Detected?
Fault-free Circuit
A B
CD
Faulty Circuit #1 (B/0)
A B
CD
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Test Pattern GenerationTest Pattern GenerationTest Pattern GenerationTest Pattern Generation
TA/0={10}, TA/1={00}
TB/0={01}, TB/1={00}
TY/0={01}or{10}or{11},TY/1={00}
T= {00,01,10}
A B YY(A/0)
Y(A/1)
Y(B/0)
Y(B/1)
Y(Y/0)
Y(Y/1)
0 0 0 0 1 0 1 0 1
0 1 1 1 1 0 1 0 1
1 0 1 0 1 1 1 0 1
1 1 1 1 1 1 1 0 1
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Fault Coverage (Example)Fault Coverage (Example)Fault Coverage (Example)Fault Coverage (Example)
Test Pattern (A,B) Faults Detected FC
{(0,0)} A/1, B/1, Y/1 3/6= 50%
{(0,1)} B/0, Y/0 2/6=33.33%
{(1,1)} Y/0 1/6=16.67%
{(0,0),(0,1),(1,0)} all 6/6= 100%
Functional test need four pattern => reduce test cost
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Test Pattern Generation (1/5)Test Pattern Generation (1/5)Test Pattern Generation (1/5)Test Pattern Generation (1/5) Path-oriented Techniques
D-algorithm Step 1. Target a specific stuck at fault
D
C
B
A
Z
SA0
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Test Pattern Generation (2/5)Test Pattern Generation (2/5)Test Pattern Generation (2/5)Test Pattern Generation (2/5) Fault activate
Step 2. Drive the fault site opposite value D: 1/0 D’: 0/1
D
C
B
A
Z
SA0
1/0
1/ 0
Fault-Free Logic
Faulty Logic
D
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Test Pattern Generation (3/5)Test Pattern Generation (3/5)Test Pattern Generation (3/5)Test Pattern Generation (3/5) Back tracing (controllability)
Step 3. Specify inputs value to generate the appropriate value at fault site
D
C
B
A
Z
SA0
1/00
D
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Test Pattern Generation (4/5)Test Pattern Generation (4/5)Test Pattern Generation (4/5)Test Pattern Generation (4/5) Fault propagation (observability)
Step 4. Select a path from the fault site to the primary output
D
C
B
A
Z
SA0
1/00
1 1/0
D
D
D’
0/1
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Test Pattern Generation (5/5)Test Pattern Generation (5/5)Test Pattern Generation (5/5)Test Pattern Generation (5/5) Line justification
Step 5. specify all other inputs
Fault detection If Z(T)faulty differs from Z(T)good
D
C
B
A
Z
SA0
1/00
1 1/0
1
1
X
0/1
Test Pattern T Discrepancy
D
D
D’
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Automatic Test Pattern GenerationAutomatic Test Pattern GenerationAutomatic Test Pattern GenerationAutomatic Test Pattern Generation Goal
Generate the test patterns for target fault model and keep the number of test pattern as small as possible
How ? Computer-Aided-Design Tools
Test Generation Fault Simulation
Add pattern to test set
Fault list
Test SetRemove all detected fault
and select next fault
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Fault EquivalenceFault EquivalenceFault EquivalenceFault Equivalence A set of faults is equivalent if no test pattern
exists to tell them apart.
The function under these faults is equivalent for any input combination
B/1
Y/1A/1
A B YY(A/0)
Y(A/1)
Y(B/0)
Y(B/1)
Y(Y/0)
Y(Y/1)
0 0 0 0 1 0 1 0 1
0 1 1 1 1 0 1 0 1
1 0 1 0 1 1 1 0 1
1 1 1 1 1 1 1 0 1
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Fault CollapsingFault CollapsingFault CollapsingFault Collapsing By testing for only one fault per equivalence set,
we can greatly reduce (or collapse) the fault universe
Speed up fault simulation
B/0
Y/0A/0
Y/1
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A fault cannot be excited and/or propagated
Untestable fault is caused by a redundant design of the DUT, that is the line and the associate gate can be removed without changing the logic function of the DUT
Untestable fault is also called as redundant fault
F=ab+a’b+bc
F=ab+a’b
Untestable faultUntestable faultUntestable faultUntestable fault
abacbc
f s-a-0
F
1
1
0
0
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Sequence Logic is Harder to TestSequence Logic is Harder to TestSequence Logic is Harder to TestSequence Logic is Harder to Test Testing requires a sequence of test vectors
Requires initialization of the machine, which may be difficult Long initialization sequence Invalid state justification
Faults may cause increasing of internal states
Apply test input at PI and set value here to test SA0
SA0 occurs at here Observe/Verify output at PO
1
0
1
0
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Sequence ATPGSequence ATPGSequence ATPGSequence ATPG Time-frame Expansion
CombinationalLogic
F/F
Primary outputs
Primary inputs
present state next state
Sequential circuit model
CombinationalLogic
Primary outputs
Primary inputs
Pseudo-PI’s
Pseudo-PO’s
A single time-frame
Cost Issue:For large sequential logic blocks with complexcircuits, sequential ATPG is just not practical.
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Design for TestabilityDesign for Testability Design for TestabilityDesign for Testability
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Design for Testability (1/2)Design for Testability (1/2)Design for Testability (1/2)Design for Testability (1/2) The design technologies which make test
generation and diagnosis easier
Testability = controllability + observability
DFT Methods Ad-hoc methods Scan, full and partial Built-In Self-Test (BIST) Boundary scan
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Design for Testability (2/2)Design for Testability (2/2)Design for Testability (2/2)Design for Testability (2/2) No single DFT technique solves all VLSI testing
problems
No single DFT technique is effective for all kinds of circuits
No DFT approach is free Manpower and tool costs Area overhead and performance penalty
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Scan Design (1/2)Scan Design (1/2)Scan Design (1/2)Scan Design (1/2) Provide controllability and observability at internal
flip-flops for testing
Method Add scan enable control signal(s) to circuit Connect flip-flops to form shift registers in test
mode Make inputs/outputs of the flip-flops in the shift
register controllable and observable
Types Internal scan
Full scanPartial scan
Boundary scan
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Scan Design (2/2)Scan Design (2/2)Scan Design (2/2)Scan Design (2/2)
CombinationalLogic
FF
FF
FF
Mode Switch(normal or test)
scan_en
Scan In
Scan Out
Primary Input
Primary Output
1. scan_en=1, shift in the scan pattern (clk trig.)
2. scan_en=0, apply pattern in PI, CL evaluates the response (clk not trig.)
3. scan_en=0, observe the PO (clk not trig.)
4. scan_en=0, capture the response (clk trig. once) first scan out
5. scan_en=1, shift out response (clk trig.)
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Scan Test Waveform (1/2)Scan Test Waveform (1/2)Scan Test Waveform (1/2)Scan Test Waveform (1/2)
Test CLK
Scan Enable
Scan inScan outScan in and scan out
Test Mode
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Scan Test Waveform (2/2)Scan Test Waveform (2/2)Scan Test Waveform (2/2)Scan Test Waveform (2/2)
Test CLK
Scan Enable
PI readyPO compare
PPO capture
Shift out responseShift in pattern
First scan out
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Impact of Scan DesignImpact of Scan DesignImpact of Scan DesignImpact of Scan Design
If you plan to insert internal scan, you must account for the impact of scan registers on a chip early in the design flow!
If you plan to insert internal scan, you must account for the impact of scan registers on a chip early in the design flow!
Non-Scan Register
Multiplexed Scan Register Chain
DOTI
DI
TE
CLK
0
1 1
0
CLK
Larger setup time requirement. (Timing impact)
Larger area than non-scan registers; (Area overhead)
TI
DI
Additional pin overhead
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Why DFT ?Why DFT ?Why DFT ?Why DFT ? Product quality
Reduce field returns (Defect Level) Improve yield
Test cost Reduce the complexity of test generation Reduce the cost of testing
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DFT ToolsDFT ToolsDFT ToolsDFT Tools Synopsys
LEDA DFT Compiler TetraMAX BSD Compiler
SynTest TurboCheck-RTL TurboCheck-Gate TurboScan TurboBSD TurboFault
Mentor DFTAdvisor FastScan BSDArchitect LBISTArchitect
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RTL Rule CheckerRTL Rule Checker RTL Rule CheckerRTL Rule Checker
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Why RTL Rule Checker?Why RTL Rule Checker?Why RTL Rule Checker?Why RTL Rule Checker? Motivation
Early identification of RTL design errors. Reusability of RTL code. Testability of RTL code. Fast iteration process
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Synopsys LEDASynopsys LEDASynopsys LEDASynopsys LEDA Features
Check for syntatic/semantic, coding style for synthesis
DFT rules check RMM rules check Many Synopsys tools (DC,VCS,Formality ……) Report the file name and line number of
problematic code Support User defined rule
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SynTest TurboCheck-RTLSynTest TurboCheck-RTLSynTest TurboCheck-RTLSynTest TurboCheck-RTL Features
Lint capability ( more than 400 rules)Check for syntatic/semantic, coding style for
synthesis DFT rules check (more than 40 rules) RMM rules check Report the file name and line number of
problematic code Support User defined rule
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DFT Guidelines and RulesDFT Guidelines and Rules DFT Guidelines and RulesDFT Guidelines and Rules
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DFT Guideline for Combinational LogicDFT Guideline for Combinational LogicDFT Guideline for Combinational LogicDFT Guideline for Combinational Logic Partition large circuit into small one
Avoid gates with large fan-in
Disable one-shots, mono-stables circuit during testing
Delayelement
One-shot
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DFT Guideline for Combinational LogicDFT Guideline for Combinational LogicDFT Guideline for Combinational LogicDFT Guideline for Combinational Logic Avoid combinational feedback loops
Avoid redundancy
Provide test points to enhance controllability and observability
QB
A
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DFT Guideline for Sequential LogicDFT Guideline for Sequential LogicDFT Guideline for Sequential LogicDFT Guideline for Sequential Logic Make flip-flops initializable
Disable internal oscillators and clocks
Make latch transparent under test
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DFT Guideline for Scan ArchitectureDFT Guideline for Scan ArchitectureDFT Guideline for Scan ArchitectureDFT Guideline for Scan Architecture No clocks used as data i.e. pulse generator
No data used as clock i.e. ripple counter
No flip-flops are non-scanned
Control test mode and scan enable signal directly
Replace tri-state buses by multiplexers to avoid bus contention
ENB
ENB
O
Ena
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DFT Guideline for Scan ArchitectureDFT Guideline for Scan ArchitectureDFT Guideline for Scan ArchitectureDFT Guideline for Scan Architecture Feed all inputs and outputs of embedded memory
to scannable flip-flops
Scan enable should be routed as clock-tree
Balance the scan chains
Memory
Log
ic
Log
ic
Un-observable
Un-controllable
Log
ic
Log
ic
Memory
Sca
n re
gist
er
Sca
n re
gist
er
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DFT Rule ViolationsDFT Rule ViolationsDFT Rule ViolationsDFT Rule Violations Generated clock (gated clock)
Generated set/reset
Combinational loop
Bi-direction
Tri-state
Latch
Cross clock domain
Constant or Floating signal
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How to Fix DFT Rule ViolationsHow to Fix DFT Rule ViolationsHow to Fix DFT Rule ViolationsHow to Fix DFT Rule Violations Add a new signal TestMode
TestMode =1’b0 for normal function TestMode =1’b1 for test
Introduce Extra Signal
Set to Constant Value
TestMode TestMode
Set to 0 Set to 1
Extra Signal
TestMode
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DFT Rule Violation (1/6)DFT Rule Violation (1/6)DFT Rule Violation (1/6)DFT Rule Violation (1/6) Generated clock (gated clock)
D Q
CLK
EN
D Q
CLK
D Q
D Q
PrimaryInput
GeneratedCLK
D Q
Logic gates
Combinationally gated clocks
Sequentially gated clocks
Generated gated clocks
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DFT Rule Violation (2/6)DFT Rule Violation (2/6)DFT Rule Violation (2/6)DFT Rule Violation (2/6) Generated set/reset (Asynchronous set/reset)
D Q
CLR
D Q
CLR
D Q
CLR
Combinationally gated set/reset
Sequentially gated set/reset
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DFT Rule Violation (3/6)DFT Rule Violation (3/6)DFT Rule Violation (3/6)DFT Rule Violation (3/6) Pulse generator
Combinational feedback loop
Potentially combinational feedback loop
Q
QB
A
QB
A
EN
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DFT Rule Violation (4/6)DFT Rule Violation (4/6)DFT Rule Violation (4/6)DFT Rule Violation (4/6) Tri-state contention
Bi-direction Force one direction
Latch Make latch transparent
ENB
ENB
O
Ena
Enable
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DFT Rule Violation (5/6)DFT Rule Violation (5/6)DFT Rule Violation (5/6)DFT Rule Violation (5/6) Floating primary input/output
Floating primary bi-directional port
Floating input/output
Floating net
Inaccessible memory objects A memory object is inaccessible if there is no path
existed from the memory object to any one of primary output port, and if it is not in the scan chain.
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DFT Rule Violation (6/6)DFT Rule Violation (6/6)DFT Rule Violation (6/6)DFT Rule Violation (6/6) Cross clock domain
Add lockup latch
D Q
CLK 2
D Q
CLK 1
Cross clock
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Synopsys DFT Design FlowSynopsys DFT Design Flow Synopsys DFT Design FlowSynopsys DFT Design Flow
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Synopsys DFT Compiler FlowSynopsys DFT Compiler FlowSynopsys DFT Compiler FlowSynopsys DFT Compiler Flow
Pre-Scan DRC
Insert ScanScan-Ready
Synthesis
Post-Scan DRC
check_test check_testinsert_scancompile -scan
Constraints:Scan style,speed, area
TechnologyLibrary:Gates, flip-flops,scan equivalents
Constraint-Based Scan Synthesis:Routing, balancing,gate-level optimization
HDLPreview
Coverage
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Scan-Ready SynthesisScan-Ready SynthesisScan-Ready SynthesisScan-Ready Synthesis
HDLCode
technologylibrary
compile -scan
DFTCDFTC
DODIDFF DO
DI
TI1
0
TO
DFF
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Pre-Scan CheckPre-Scan CheckPre-Scan CheckPre-Scan Check Check gate-level scan design rule before scan chain
synthesis.
Looks at four categories of testability issues: Modeling problems, such as lack of a scan equivalent. Topological problems, like unclocked feedback loops. Protocol inference, such as test clocks and test holds. Protocol simulation, to verify proper scanning of bits.
dc_shell> check_test
...basic checks...
...checking combinational feedback loops...
...inferring test protocol...Inferred system/test clock port CLK (45.0,55.0)....simulating parallel vector...simulating serial scan-in…Information: The first scan-in cycle does not shift in data.(TEST-301)Warning: Cell U1 (FD1S) is not scan controllable. (TEST-302)Information: Because it clocks in an unknown value from pin TI.(TEST-512)Information: Because port SI is unknown. (TEST-514)Information: As a result, 3 other cells are not scan controllable.(TEST-502)Information: Test design rule checking completed. (TEST-123)
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Scan Chain InsertionScan Chain InsertionScan Chain InsertionScan Chain Insertion Scan-Chain Insertion Algorithm:
1. Targets the previewed scan-path architecture.2. Performs any remaining scan replacements.3. Adds disabling/enabling logic to tristate buses.4. Conditions the directionality of bidirectional ports.5. Wires the scan flops into the specified chains.6. Optimizes the logic, minimizing constraint
violations.
insert_scan -map_effort medium
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Post-Scan CheckPost-Scan CheckPost-Scan CheckPost-Scan Check Why run check_test again?
Confirm there are no new DFT problems. Verify the scan chains synthesized operates
properly. Create an ATPG-ready database.
check_test
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Estimate Test coverageEstimate Test coverageEstimate Test coverageEstimate Test coverage
• Use the DFTC ATPG command: estimate_test_coverage will call TetraMAX for fault estimate.
estimate_test_coverage
Pattern Summary Report
Uncollapsed Stuck Fault Summary Report ----------------------------------------------- fault class code #faults ------------------------------ ---- --------- Detected DT 3084 Possibly detected PT 0 Undetectable UD 12 ATPG untestable AU 0 Not detected ND 0 ----------------------------------------------- total faults 3096 test coverage 100.00% -----------------------------------------------
Information: The test coverage above may be inferior than the real test coverage with customized
protocol and test simulation library.
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AutoFix and Shadow LogicDFTAutoFix and Shadow LogicDFTAutoFix and Shadow LogicDFTAutoFix and Shadow LogicDFT By default, the AutoFix and Shadow LogicDFT
utilities are disabled.
To use AutoFix, you enable the utility and specify the scope of the design on which it will apply.
set_dft_configuration -order {autofix}set_dft_configuration -order {wrapper}set_dft_configuration -order {autofix,wrapper}
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AutoFix and Shadow LogicDFTAutoFix and Shadow LogicDFTAutoFix and Shadow LogicDFTAutoFix and Shadow LogicDFT
To use AutoFix and Shadow LogicDFT, we need to change our command from scan to dft.
compile -scancheck_scanpreview_scaninsert_scanreport_testset_scan_configurationset_scan_signal
compile -scancheck_dftpreview_dftinsert_dftreport_test -dftset_dft_configurationset_dft_signal
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Block BoxBlock BoxBlock BoxBlock Box
scan_in scan_out
Black Box
Un
-co
ntro
llable
Un
-o
bservab
le
Scan
R
egisters
Scan
R
egisters
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Shadow LogicDFTShadow LogicDFTShadow LogicDFTShadow LogicDFT
Black Box
con
trollab
le
ob
servabl
e
Scan
R
egisters
Scan
R
egisters
Wrap
pe
r
Wrap
pe
r
scan_in scan_out
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DFT Compiler to TetraMAXDFT Compiler to TetraMAXDFT Compiler to TetraMAXDFT Compiler to TetraMAX
Fault Fault ReportsReportsATE VectorsATE Vectors
DCDC
Write –f verilog –hierarchy \–output “design_dft.v”
Write_test_protocol –f stil \ –out “design.spf”
design_dft.v
design.spf
TetraMaxTetraMax
read netlist design_dft.v
run drc design.spf
SimulationSimulationLibraryLibrary read netlist library.v
Simulation Simulation TestbenchesTestbenches
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Synopsys TetraMAX FlowSynopsys TetraMAX FlowSynopsys TetraMAX FlowSynopsys TetraMAX Flow
DONDONEE
Library
DRCProcedures
BEGINBEGIN
Design
Build ModelBuild Model
Run DRCRun DRC
Run ATPGRun ATPGReviewReviewResultResult
Compress & Compress & Save PatternsSave Patterns
1
2
3
45
6
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Chapter 2Chapter 2
Memory TestingMemory Testing
Chapter 2Chapter 2
Memory TestingMemory Testing
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Basic ConceptsBasic Concepts Basic ConceptsBasic Concepts
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IntroductionIntroductionIntroductionIntroduction Memory is the key component in electronic
system
Embedded memory is one of the most universal block in a SoC
Embedded memory testing is a more and more difficult problem I/O pins limited Speeds
BIST is considered as the best solution
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Type of Memory TestType of Memory TestType of Memory TestType of Memory Test Parametric Test: DC & AC
Reliability Screening Long-cycle testing Burn-in: static & dynamic BI
Functional Test Device characterization
Failure analysis Fault modeling
Simple but effective Test algorithm generation
Small number of test patterns (data backgrounds) High fault coverage Short test
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RAM Functional Fault Model (1/3)RAM Functional Fault Model (1/3)RAM Functional Fault Model (1/3)RAM Functional Fault Model (1/3) Stuck-At Fault (SAF)
Cell or line stuck-at 0/1
Transition Fault (TF) Cell fails to transit from 0 to 1 or 1 to 0
Address-Decoder Fault (AF) No cell accessed by a certain address Multiple cells accessed by certain address Certain cell not accessed by any address Certain cell accessed by multiple address
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RAM Functional Fault Model (2/3)RAM Functional Fault Model (2/3)RAM Functional Fault Model (2/3)RAM Functional Fault Model (2/3) Coupling Fault (CF)
State Coupling Fault (CFst)Coupled (victim) cell is forced to 0 or 1 if coupling
(aggressor) cell is in given state Inversion Coupling Fault (CFin)
Transition in coupling cell complements (inverts) coupled cell
Idempotent Coupling Fault (Cfid)Coupled cell is forced to 0 or 1 if coupling cell
transits from 0 to 1 or 1 to 0
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RAM Functional Fault Model (3/3)RAM Functional Fault Model (3/3)RAM Functional Fault Model (3/3)RAM Functional Fault Model (3/3) Stuck-Open Fault (SOF)
Cell can’t access due to broken line
Bridging Fault (BF) Short between cells (AND Type or OR Type)
Other Faults
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RAM Test AlgorithmRAM Test AlgorithmRAM Test AlgorithmRAM Test Algorithm A test algorithm is a finite sequence of test
elements A test element contains a number of memory
operations Data patterns (backgrounds)Address (sequence)
A march test is a finite sequence of march elements A march element is specified by an address order
and a number of read/write operations {(w1,r1); }
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Default Test AlgorithmsDefault Test AlgorithmsDefault Test AlgorithmsDefault Test Algorithms Moving Inversion (MOVI) Algorithm [De jonge &
Smeulders 1976]
{(w0); (r0,w1,r1);(r1,w0,r0);(r0,w1,r1); (r1,w0,r0);}
Test length (13N)
Target faults:AF, SAT, TF and most CF
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Test Algorithm (Example)Test Algorithm (Example)Test Algorithm (Example)Test Algorithm (Example) March C- [Goor 1991]
{w(0); (r0,w1); (r1,w0); (r0,w1); (r1,w0);(r0)}
Test length: 10 N
Target faults:AF, SAT, TF and all CF
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Test Algorithm Summary (1/2)Test Algorithm Summary (1/2)Test Algorithm Summary (1/2)Test Algorithm Summary (1/2)
AlgorithmFault coverage
SAF AF TF CFin CFid CFst Length
MATS All Some 4N
MATS+ All All 5N
MATS++ All All All 6N
MARCH X All All All All 6N
MARCH C- All All All All All All 10N
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Test Algorithm Summary (2/2)Test Algorithm Summary (2/2)Test Algorithm Summary (2/2)Test Algorithm Summary (2/2)
Algorithm Description Ref
MATS {w(0);(r0,w1);(r1)} [1]
MATS+ {w(0);(r0,w1);(r1,w0)} [2]
MATS++ {w(0);(r0,w1);(r1,w0,r0)} [3]
MARCH X {w(0);(r0,w1);(r1,w0);(r0)} [3]
MARCH C- {w(0);(r0,w1);(r1,w0);(r0,w1);(r1,w0);(r0)} [4]
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How to detect faults?How to detect faults?How to detect faults?How to detect faults? Algorithm: MATS+ {w(0);(r0,w1);(r1,w0)}
Cell (2,1) SA0
0 0 00 0 00 0 0
1 1 11 1 11 1 1
0 0 00 0 00 0 0
0 0 00 0 00 0 0
1 1 10 1 11 1 1
0 0 00 0 00 0 0
Good Memory
Bad Memory
After M0
After M0
After M1 After M2
After M1 After M2
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Word-Oriented RAMWord-Oriented RAMWord-Oriented RAMWord-Oriented RAM Background bit is replaced by background word
For example: 8bit memory Background 0 ->
(00000000,01010101,00110011,00001111) Background 1 ->
(11111111,10101010,11001100,11110000)
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Memory BISTMemory BIST Memory BISTMemory BIST
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Memory BIST ToolsMemory BIST ToolsMemory BIST ToolsMemory BIST Tools Synopsys
DesignWare SRAM BIST MacroCell RAM coreConsultant GUI Gate-level
SynTest TurboBIST-Memory ROM, RAM Edit a memory spec. file RTL
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Memory BIST ToolsMemory BIST ToolsMemory BIST ToolsMemory BIST Tools Mentor
MBISTArchitect ROM, RAM Edit a memory spec. file RTL
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Memory Built-In Self-TestMemory Built-In Self-TestMemory Built-In Self-TestMemory Built-In Self-Test
Memory Wrapper
BISTController
Memory
Mux
Analyzer
BistMode
Original Memory Port
mem_ctrl
bist_ctrl
Q
BistFail
Finish
ErrorMap
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BIST Controller Memory wrapper
BistMode
Original memory port
Q
Finish
BistFailErrMap
mem_ctrl
bist_ctrl
SynTest Memory BIST ArchitectureSynTest Memory BIST ArchitectureSynTest Memory BIST ArchitectureSynTest Memory BIST Architecture
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SynTest Memory BIST ArchitectureSynTest Memory BIST ArchitectureSynTest Memory BIST ArchitectureSynTest Memory BIST Architecture Memory Wrapper
Memory Control
Address
Data In
BistMode
From BIST
Original
From BIST
From BIST
Original
Original
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SynTest Memory BIST ArchitectureSynTest Memory BIST ArchitectureSynTest Memory BIST ArchitectureSynTest Memory BIST Architecture Share BIST controller
BISTcontroller
mem_ctrl
wrapper1wrapper0
mem_ctrl0mem_ctrl1
bist_ctrl
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SynTest Memory BIST ArchitectureSynTest Memory BIST ArchitectureSynTest Memory BIST ArchitectureSynTest Memory BIST Architecture Group Memory
BISTcontroller
wrapper1wrapper0
Group0MemGroupSel[0]
wrapper1wrapper0
Group1MemGroupSel[1]
MemGroupSel[1:0]
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SynTest SRAMBIST FlowSynTest SRAMBIST Flow SynTest SRAMBIST FlowSynTest SRAMBIST Flow
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SRAMBIST FlowSRAMBIST FlowSRAMBIST FlowSRAMBIST Flow
Study Spec.
Create Memory Description File
Create TestAlgorithm
Create BIST Configuration File
Generate BIST
RTL Level Simulation
Synthesize the BIST RTL Code
Gate Level Simulation
Yes
No
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Memory Spec. & MBIST AttributeMemory Spec. & MBIST AttributeMemory Spec. & MBIST AttributeMemory Spec. & MBIST Attribute Study memory spec. form cell library document
Describe memory spec. in memory description file (memory_name.mdf)
MBIST Attribute Decide BIST clock rate Decide BIST clock trigger edge Do multiple memories share one bist controller? Create Test Algorithm?
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Memory Description FileMemory Description FileMemory Description FileMemory Description File
BIS Timp lementc o ns traint
S R AMinfo rmatio n I
S R AMinfo rmatio n II
C re a teT u rb o B I S T _ M e m o ry
c o n s tra in t file
B IS T fu n c tio n a lc o n s tra in t
BIS T c lo c kinfo rmatio n
o therintegratio nc o ns traint
glo b alinfo rmatio n
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GLOBAL SectionGLOBAL SectionGLOBAL SectionGLOBAL Section%GLOBAL{ %TIMESCALE 1ns/10ps; %SYNC_RESET TRUE; //Default: TRUE %CLK_CYCLE 20; //Same as memory //%BIST_CLK_TRIGGER posedge; %ANALYZER_ON_MEM TRUE; //Default: FALSE %RESET_PIN BIST_rst;//Default:Use BistMode}
Memory Wrapper
BISTController
Memory
Mux
Analyzer
BistMode
Original Memory Port
mem_ctrl
bist_ctrl
Q
BistFail
Finish
ErrorMap
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Memory Group SectionMemory Group SectionMemory Group SectionMemory Group Section%MEMORY_GROUP{ %GROUP c4mtram72x8,c4mtram72x8; %GROUP c4msram32x16s;}
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Memory SectionMemory SectionMemory SectionMemory Section%MEMORY c4msram32x16s{ %TYPE SRAM; %DATA_BITS 16; %ADDR_BITS 5; %LOW_ADDR 5'b00000; %HIGH_ADDR 5'b11111; %LATENCY 0; %CLOCK CE; %SELECT -CSB;// %NO_MUX TRUE; %FORCE OEB = 0; %OTHER_INPUT PWN; …
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Memory SectionMemory SectionMemory SectionMemory Section%MEMORY c4msrom0101{ %TYPE ROM; %MISR_BITS 16; %MISR_POLY 15,3,1,0; %Q_CONNECT 15,13,12,11,0; %MISR_SEEDS 0000000111001010; %ROM_CONTENT_FILE rom.cod
rom.cod
110010
010110
111111
100000
.......
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MISRMISRMISRMISR Polynomial:
cnXn+cn-1Xn-1+...+c1X+1
Dn+
Dn-1+++
D2D1
c1c2cn-1cn
I0 I1 In-2 In-1
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Port SectionPort SectionPort SectionPort Section%MEMORY c4msram32x16s{ … %PORT p1 { %TYPE rw; %ADDRESS A4,A3,A2,A1,A0; %DATA_IN I; %DATA_OUT O; %CLOCK CE; %WRITE_EN -WEB; %SELECT -CSB; %OUTPUT_EN -OEB; %READ_EN REN; } %PORT p2
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BIST Configuration FileBIST Configuration FileBIST Configuration FileBIST Configuration File
%ALGORITHM MARCH_CM{ %MARCH U{%W(0);} %MARCH U{%R(0);%W(1);} %MARCH U{%R(1);%W(0);} %MARCH D{%R(0);%W(1);} %MARCH D{%R(1);%W(0);} %MARCH D{%R(0);} %REPEAT_PAT 0 (0000,0011,0101); %REPEAT_PAT 1 (1111,1100,1010);}
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SRAMBISTSRAMBISTSRAMBISTSRAMBIST Command syntax:
srambist <options> <design name> srambist c4mtram72x8
Options bcf_file <file name> algorithm <algorithm name> serial_test
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Input/Output FilesInput/Output FilesInput/Output FilesInput/Output Files
srambist
sram.mdf
sram.bist.rpt
sram_top.vsram_wrapper.v
sram_rb.v
sram_sim.v
sram.scpsram.tcl
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RTL Level SimulationRTL Level SimulationRTL Level SimulationRTL Level Simulation
sram_top.vsram_wrapper.v
sram_rb.v
sram_sim.v
RTL level simulation
sram.v
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Synthesis BIST RTL CircuitSynthesis BIST RTL CircuitSynthesis BIST RTL CircuitSynthesis BIST RTL Circuit
sram_top.vsram_wrapper.v
sram_rb.v
sram.scpsram.tcl
synthesis tool
gate-netlist
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ReferenceReferenceReferenceReference [1] J. Knaizuk, Jr. and C.R.P. Hartmann, “An
Optimal Algorithm for Testing Stuck-at-Faults in Random Access Memories,” IEEE Trans. On Computers, 1977
[2] M.S. Abadir and J. K. Reghbati, “Functional Testing of Semiconductor Random Access Memories” ACM Computing Surveys 1983
[3] A. J. van de Goor, Testing Semiconductor Memories: Theory and Practice. Chichester, UK: John Wiley & Sons, Inc., 1991
[4]M. Marinescu, “Simple and Efficient Algorithms for Functional RAM Testing,” in Proc, of the International Test Conf. 1998