chapter 7. storage componentscourses.cecs.anu.edu.au/.../datapath/gajski_datapaths.pdf · 2010. 6....

7. Storage Components 7-1

Chapter 7. Storage Components

Introduction

✯ Storage components store data and perform simple data transformations, suchas counting and shifting.

✩ Registers, counters, register files, memories, etc.

✯ Register: a group of binary cells (FFs) suitable for holding binary informa-tion.

✩ In addition to the FFs, a register may have combinational gates that con-trol when and how new information is transferred into the register.

✯ Counter: a register that goes through a predetermined sequence of states uponthe application of input pulses.

✩ The gates in a counter are connected in such a way as to produce a pre-scribed sequence of binary states in the register.

✯ Memory unit: a collection of storage cells together with associated circuitsneeded to transfer information in and out of storage.

✩ For example, SRAM & DRAM.

Registers

☞ A register can be viewed as a bitwise extension of a FF.

✏ The simplest of the storage components:n inputs,n outputs, and aclocksignal.

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2005


✏ All the n FFs are driven by the common clock signal.

☞ Registers are readily available as MSI circuits, it becomes convenient at timesto employ a register as part of the sequential circuit. The combinational-circuit part of the sequential circuit can be implemented by any of the meth-ods discussed in Chapters 4 & 5.

☞ D-FFs are normally used for registers.

☞ The register may be enhanced byasynchronous PresetandClear (Reset)sig-nals, which are not controlled by the clock signal.

Q Q Q Q0

Register0I I I I123

3 2 1

(a) Graphic symbol

(b) Register schematic

I 3

Q3

Q3

3D

I

Q

Q

I

Q

Q

I

Q

Q

D

Clk

2 1 0

00

01

D1 12D2

2

Figure 1: A 4-bit register [Gajski].



Q Q Q Q0

Register0I I I I123

3 2 1

(a) Graphic symbol

(b) Register schematic

I 3

Q3

Q3

3D

I

Q

Q

I

Q

Q

D

I

Q

Q

Clk

2

D2 2

2 1

1 1

1 0

D0 0

0

preet

clear

preset

clear

Figure 2: A 4-bit register with asynchronous Preset and Clear [Gajski].



✯ To be able to control when the data will be entered into a register, and forhow long it will be stored there before being sent to the output, we add theLoad (Enable)input to form aparallel-load register.

Q3

3

3D Q QD QD

Clk

I

Selector

1 0

I

Selector

1 0

I

Selector

1 0

I

Selector

1 0

Load

3 2 1 0

D2 2 1 1 0 0

Y Y Y01Y2

(a) Graphic symbol

Q Q Q Q0

Register0I I I I123

3 2 1

Load

(b) Operation table

Present state

Load

Next state

Q3 Q Q Q2 1 0

3 2 1 0I I I I

No change0

1

(c) Register schematic

Figure 3: Register with parallel load [Gajski].



Shift Registers

✯ A shift registercan shift the stored data right and/or left.


(a) Graphic symbol (b) Operation table

Q Q Q Q0

I

3 2 1Shift

Shift Register

Present state

Next state

Q3 Q Q Q2 1 0

I

No change0

1 3 2 1QQQ

Shift

L

L

Q3

3

3D Q QD QD

Clk

I

Selector

1 0

Selector

1 0

Selector

1 0

Selector

1 0

D 2 1 1 0 0

Y Y Y01Y2

Shift

L

2


Q3

3

3D Q QD QD

Clk

I

Selector

I

Selector

I

Selector

I

Selector

3 2 1 0

D2 2 1 1 0 0

Y Y Y01Y2

S0

S1

3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0

RLI

I


0 0

0 1

1 0

1 1

Present state

S0S1

Next state

Q3 Q Q Q2 1 0

3 2 1 0I I I I

Q QQ2 1 0

Q Q

Operation

No change

Shift right

Shift left

Load input

IS0S1

Shift Register

Q0QQQ

I I 0II IL R

R

L

I

I

3 2 1

3 2 1

Q3 Q Q Q2 1 0

Q3 2 1

Figure 4: Shift registers [Gajski].



Counters

✯ A counteris a special type of register that counts upward, downward, or inany prespecified sequence.

Clk

Q

Q

D2 2

2

Q

Q

D

1

1 1 Q

Q

D0 0

0

Q3

Q3

3D

HAHA HA HA

Output carry


Q Q Q Q03 2 1

CounterOperations

0

1

No change

Count

Qi Ci Ci+1 Di

0 00 11 01 1

0 00 10 11 0

(c) HA truth table

E

3C 2C 1C 0CC4

E

(d) Counter schematic

E

Clear

Clear

(d) Logic schematic

(a) Graphic symbol (c) HAS truth table(b) Operation table

Q Q Q Q03 2 1

Up/Down Counter

Operations

No change

Count up

Count down

0

1

1

X

0

1

DE

Qi Ci Ci+1 Di

0 00 11 01 1

0 00 11 01 1

0000

1111

0 00 10 11 0

0 01 10 10 0

DE

1111

1111

Clk

Q3

Q33D

Q3’

HAS

Q2

QD2 2

Q2’

Q1

QD1 1

Q1’

Q

Q

D0 0

0

Q0’

HAS HAS HAS

D

E

Output carry

0C1C2C3CC4

Clear

DE

Clear

Figure 5: Binary up and up/down counters [Gajski].




Q Q Q Q03 2 1

Up/Down Counter0I I I I123DE

Load

OperationsLoad

No change

Count up

Count down

Load the input

X

0

1

X

0

1

1

X

0

0

0

1

E D


3

I I I I

Load

3 2 1 0

Y Y Y01Y2

33 QD

Clk

QD Q QDD2 2 1 1 0 0

3 QQ Q Q2 1 0

Selector

1 0

HAS

Selector

1 0

HAS

Selector

1 0

HAS

Selector

1 0

HAS

’ ’ ’ ’

E

D

Output carry

Figure 6: Binary up/down counter with parallel load [Gajski].



BCD Counter

✯ A BCD countercounts in the sequence 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, ....

Q Q Q Q03 2 1


Load

"0"

"0" "0" "0" "0" Selector1 0

"0 0 0 0""1 0 0 1"

Q Q Q Q03 2 1


Load

"0"

(a) BCD up−counter (b) BCD up/down−counter

Figure 7: BCD counters [Gajski].

Asynchronous Counter

✯ An asynchronous countercounts without an incrementer or decrementer—itsFFs are not clocked by the same signal.

☞ Counting without an incrementer/decrementer is achieved bytoggling eachFF at half the frequency of the preceding FF.

✏ FFi changes state only half as often as FFi�1.

✏ FFi changes state only when FFi�1 goes from 1 to 0, but not from 0 to 1.

☞ A T-FF is very convenient for such an asynchronous counter design.

☞ Thecounting frequency(speed) will be limited by the number of FFs due tothe linear growth of the clock-to-output delay.

✏ To speed up the counting process, we can use themixed-mode counter.



(a) Graphic symbol

Q Q Q Q03 2 1

Asyn. Counter

(b) Logic schematic3 012

33 Q

Clk

Q Q Q2 2 1 1 0 0

3 QQ Q Q2 1 0’ ’ ’ ’

1 1 1 1

FF 3 FF 2 FF 1 FF 0

Q Q Q Q

E

T T T T

0t t

1t3

t2

t4

t5

t6

t7

Q

Q

Q

Clk

Q

2

1

0

3

0 1 2 3 4 5 6 7 8

4

2

3

(c) Timing diagram

3

2

E

Clear

Clear

Figure 8: Asynchronous up-counter [Gajski].



(a) Synchronous counter with 4−bit asynchronous slices

(b) Asynchronous counter with 4−bit synchronous slices

Q Q Q Q03 2 1Q Q Q Q03 2 1

Enable

ClkReset

Syn. CounterSyn. Counter

Q Q Q Q03 2 1

Asyn. Counter

Q Q Q Q03 2 1

Asyn. Counter

Enable

ClkReset

E

Clear

E

Clear

E

Clear

E

Clear

Figure 9: Mixed-mode up-counter [Gajski].

Register Files

✯ A register filehas2n registers ofm FFs each.

✩ The registers are arranged as a 2-dimensional array ofregister-file cells(RFCs).

✩ In addition, it has read/write decoders and output driving logic.

✩ Writing is controlled by theWrite-Enable (WE)signal.

➣ At any time, we can write into only one register (row), unless it hasmultiple write ports.

✩ Reading is controlled by theRead-Enable (RE)signal.

➣ At any time, we can read from only one register, unless it has multi-ple read ports.

✩ Reading from and writing into the same register at the same time nor-mally is not allowed.



☞ The primary advantage of a register file isregularity, which reduces routing(wiring) complexity.

(b) Graphic symbol

(c) Logic Schematic

RFC

RFC

RFC

RFC

3I 2I 1I 0I

3O 2O 1O 0O

0WA

WA1

WE

2−to−4 writedecoder

0

3

2

1

0

1RA

RA

RE

0

3

2

1

2−to−4 readdecoderRFC

RFC

RFC

RFC

RFC

RFC

RFC

RFC

RFC

RFC

RFC

RFC

WA

WE

RARFn

O

RE

n n

m

m

I

Clk

X2 m

QD

Clk

RFC

Input Output

Read select

Write select

(a) Register file cell

Figure 10: Register file with 1 write port and 1 read port [Gajski].



(a) Register−file cell (b) Graphic symbol

(c) Logic Schematic

RFC

RFC

RFC

RFC

3I 2I 1I 0I

3 2 1 0

0WAWA1 WE

2−to−4 writedecoder

0

3

2

1

0

3

2

1

2−to−4 readdecoderRFC

RFC

RFC

RFC

RFC

RFC

RFC

RFC

RFC

RFC

RFC

RFC

0

3

2

1

2−to−4 readdecoder

1RAB 0RAB

REB

1 0RAA RAA

REA

3 2 1 0A B A B A B A B

WA RFn

nn

m

m

I

n

m

A B

RAA

REA

RAB

REB

WE

Clk

2 mx

QD

Clk

RFC

Input

Write select

OutA

OutB

Readselect(port A)

Readselect(port B)

Figure 11: Register file with 1 write port and 2 read port [Gajski].



Random Access Memories (RAMs)

✯ A RAM is organized as an array of2n rows withm bits stored in each row.

✏ The size of the RAM is2n�m bits—it hasn addresslines,m input datalines, andm output data lines (see Fig. 12).

✏ The input data lines can be the same with the output data lines, i.e., thedata lines can be bidirectional.

✏ For a commodity RAM,16 � n � 30, andm = 1, 4, 8, 16, 0r 32.

✯ A memory cell(MC) can be considered as a clocked D latch with an ANDgate and an output driver (see Fig. 13(a)).

✩ For astatic RAM (SRAM), MC is constructed by 6 transistors, usingcross-coupled inverters to serve as a latch, and implementing the inputAND gate and the output driver with one transistor each.

✩ For adynamic RAM (DRAM), MC is constructed by only 1 transistor.

✍ The latch is implemented by a capacitor.

✍ It needs to berefreshedperiodically.

✍ It has high density (therefore low cost).

✯ The RAM also has a Chip-Select (CS) input and a Read/Write Select (RWS)input (see Fig. 13(b)).

✩ TheRWS input sometimes is denoted asR0=W .

✯ Both SRAM and DRAM arevolatile memories, i.e., their content is lost ifthe power is shut down.

✩ ROM, PROM, EPROM, EEPROM, and flash memories arenonvolatile.

✯ The delay time from address input to data output (t2 � t0 in Fig. 14) is thememory access time.

✩ The address/datasetup timeandhold timeare shown in Fig. 14.

✯ We can connect several memory chips to get one of longer words (Fig. 15),or connect several memory chips to get one with more words (Fig. 16).



(a) Memory address and content

(b) Graphic symbols

2 −2

2 −1n

n

0 ... 0 0 0

0 ... 0 0 1

0 ... 0 1 0

0 ... 0 1 1

0 ... 1 0 0

0 ... 1 0 1

0 ... 1 1 0

0 ... 1 1 1

1 ... 1 1 0

1 ... 1 1 1

0

1

2

3

4

5

6

7

m bits

0 1 1 ... 0 1 0 0

0 1 1 ... 0 1 0 0

1 0 1 ... 1 1 0 0

1 0 1 ... 0 0 0 1

0 1 1 ... 0 1 0 1

0 1 0 ... 0 1 0 1

1 1 0 ... 0 0 1 1

1 0 1 ... 0 0 0 1

0 0 0 ... 0 0 1 0

1 1 1 ... 0 1 1 0

Memory content

Binary Decimal

Memory address

. . .

. . .

. . .

2 m RAMA1

0

A

A

CS

1 0

n

. . .

. . .

. . .

. . .

RWS

m−1

n−1

I/O I/O I/O

x

. . .

A

I I1

I0

1

0

A

A

CS

1 0O O O

n

. . .

. . .

. . .

. . .

. . .

RWS

m−1

m−1

n−1

x2 m RAM

Figure 12: Random-access memory (RAM) [Gajski].



(b) Memory schematic

QDInput Output

MCC

Row select

Write enable

0

1A

A

12 03

0

3

2

1

2−to−4addressdecoder

MC

MC

MC

MC MC

MC

MC

MC MC

MC

MC

MC MC

MC

MC

MC

RWS

CS

IO IO IO IO

Writeenable

(a) Memory cell

Figure 13: RAM organization [Gajski].



RWS

(b) Write cycle timing

(a) Read cycle timing

0t t

1t3

t2

t4

t5

Access time

Valid data

Valid address

Outputdisable−time

Outputenable−time

Outputhold−time

CS

Address

Data

0t t

1t3

t2

t4

t5

Valid data

Valid address

RWS

CS

Address

Data

Datahold−time

Addresshold−time

Write−pulse width

Addresssetup−time Data setup−time

Figure 14: RAM timing [Gajski].



I

O

M3

I

O

M

I

O

M

I

O

M012

8 8 8 8

32

14

8 8 8 8

32

CS

RWS

A

Input bus

Output bus

A

CS

RWS

A

CS

RWS

A

CS

RWS

A

CS

RWS

Figure 15: A16K � 32 RAM design using16K � 8 RAMs [Gajski].



I

O

M3

I

O

M0

I

O

M1

I

O

M2

14

RWS

2

Input bus

Output bus

A

A

CS

RWS

A

CS

RWS

A

CS

RWS

A

CS

RWS

2−to−4Decoder

3 2 1 0

Figure 16: A64K � 8 RAM design using16K � 8 RAMs [Gajski].



*Push-Down Stacks

✯ A push-down stack(or simply stack) is a memory component with limitedaccess—data can be accessed through only one location (i.e., thetop of thestack).

✩ When data is to be stored, it ispushedon the stack and stays on top ofothers.

✩ When data is to be fetched, it has to be in the top position before it canbepoppedout of the stack.

✯ A stack can be implemented by shift registers, with an up-down counter todetect full/empty stack as shown in Fig. 18.

✯ It can also be implemented by a RAM—less expensive for a large stack, butneed two pointers (implemented by counters) as shown in Fig. 19.

Top

Top − 1

Top − 2

Top − 3

34

23

empty

empty

34

23

empty

empty

45

34

23

empty

(a) Stack content before 45 is pushed down

45 45

(b) Stack content after 45 is pushed down

(c) Stack content after 45 is popped up

Figure 17: Push-down stack operations [Gajski].



Reset

S0

S1

Reset

S0

S1

Up−Down Counter

ResetDESet

Push/Pop

IN

IN

0

m−1

0

m−1OUT

OUT

Empty

Full

Enable

(d) Stack schematic

Reset

03 2 1

I

Q Q Q Q

SRwPLL IR

03 2 1

I

Q Q Q Q

SRwPLL IR

03 2 1Q Q Q Q

. . .

. . .

. . .

"0"

"0"

(a) Operation table (b) Control table

Push/Pop

X

0

1

0

1

1

E

X

0

1

0

1

1

Countercontrols

D

Shiftregistercontrols

0

1

1

0

1

0

S 1 S 0EnableOperationsPush/Pop

X

0

1

0

1

1

No change

Push

Pop

Enable 1 0

Counteroutputs

Q QQ 2

00001

00110

01010

Empty Full

10000

00001

(c) Output table

Control logic

Outputlogic

Figure 18: A 4-word stack implemented by shift registers [Gajski].



(c) Stack schematic

Reset

Push/Pop

Empty

Full

I/O bus

DEReset

Top Top−1

DESet

SelectorS

1K RAM

A

CSRWS

OperationsPush/Pop

X

0

1

0

1

1

No change

Push

Pop

(a) Operation table (b) Control table

Push/Pop

X

0

1

0

1

1

X

0

1

0

1

1

D

0

1

1

0

1

0

S CS RWS

Memorycontrols

Selectorcontrol

Countercontrols

Control logic

Output logic

Enable Enable E

X

1

0

Enable

1 0

Top−1

Topempty

datadata

emptyemptyempty

empty

0 1 2

102110221023

(a) Symbolic design

Figure 19: A 4-word stack implemented by RAM [Gajski].



*First-in-First-out Queue

✯ A first-in-first-out (FIFO) queue(or simplyqueueorFIFO) is a memory com-ponent with limited access—data can be written through only thehead (front)of the queue and read (and removed) through only thetail (back)of the queue.

✯ A queue can be implemented by shift registers, with an up-down counter todetect full/empty queue as shown in Fig. 21.

✯ It can also be implemented by a RAM—less expensive for a large queue, butneed two pointers (implemented by counters) as shown in Fig. 22.

Top

Top − 1

Top − 2

Top − 3

empty

empty

34

23

empty

45

34

23

empty

empty

45

34

23

45

(a) Queue content before 45 is stored

(b) Queue content after 45 is stored

(c) Queue content after 23 is read

Figure 20: FIFO queue operations [Gajski].



. . .

(a) Operation table

Operations

X

0

1

0

1

1

Read/Write

No change

Read

Write

X

0

1

0

1

1

E

0

1

1

DS1 S0Read/Write

0

0

1

0

0

0

X

1

0

(b) Control table

Up−Down Counter

ResetDESet

IN

IN

0

m−1

m−1OUT

0OUT

Empty

Full

Se

lect

or

Se

lect

or

Reset

"0"

(c) Queue schematic

S0

S1

Reset

03 2 1

I

Q Q Q Q

SRwPLL IR

S0

S1

Reset

03 2 1

I

Q Q Q Q

SRwPLL IR

03 2 1Q Q Q Q

Control logic

Output logic

. . .

. . .. .

.

Enable Enable

Enable

S1

S0

S1

S0

3

2

1

0

3

2

1

0

Read/Write

Figure 21: A 4-word queue implemented by shift registers [Gajski].



Operations

X

0

1

0

1

1

Read/Write

No change

Read

Write

X

0

1

0

1

1

X

0

1

0

1

1

0

1

0

S CS RWSRead/Write

X

1

0

0

0

1

emptydatadata ...dataempty

Front

Back

0 1 2

102010211022

(a) Symbolic design (b) Operation table (c) Control table

Reset

Empty

Full

I/O bus

Selector1 0

S

1K RAM

Clk

EReset

Read/Write

EReset

BackFront

1010

(d) Schematic

A

CSRWS

Comparator< = >

1 1

E(Front)

E(Back)EnableEnable

Enable

Figure 22: A 4-word queue implemented by RAM [Gajski].



Simple Datapaths

☞ Datapathsare used in all standard CPU and ASIC implementations to per-form complex numerical computation or data manipulations; a datapath con-sists of temporary storage in addition to arithmetic, logic, and shift units.

Example 1Assume we want to perform the summation of 100 numbers:sum =

P100

i=1xi: We

can use the datapath as shown in Fig. 23 to implement the following algorithm:

sum=0;for(i=1; i


19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ALUoperation

Writeaddress

Readaddress A

Readaddress BIE OE

Shifteroperation

(a) Datapath schematic

ALU

A BMSS0

1

0

1

Clk

Bus BBus A

Result Bus

ShifterSSS

2

WAWE

3

3

3

Selector1 0

S

I L I R

RAAREA

RABREB

"0" "0"

00001111

M S1 S0 ALU Operations

00110011

01010101

S2

00001111

S1 S0

00110011

01010101

Shift Operations

(b) Table of ALU operations

(c) Table of shifter operations

complement A AND EX−OR OR decrement A add subtract inrement A

pass pass not used not used shift left rotate left shift rightrotate right

(d) Control word

Inport

Outport

8 mRegister File

x

7

654

321

0

19

8−1011

12−14

15

16−18

Figure 24: Datapath with 3-port register file [Gajski].



(a) Basic algorithm for one’s count

R1: Data

R2: Mask

R3: Ocount

R4: Temp

(b) Register assignment

IE OEControlWords

Readaddress B

Readaddress A

Writeaddress

ALUoperation

Shifteroperation

1

2

3

4

5

6

7

1

0

0

0

0

0

0

X

0

0

R1

R3

R1

R3

X

0

X

R2

R4

0

0

X

add

increment

AND

add

add

add

0

0

0

0

0

0

1

R1

R3

R2

R4

R3

R1

none

X

pass

pass

pass

pass

shift right

pass

(c) Control words for one’s counter

} Repeated whileData = 0

while repeat

end while

1. Data := Inport2. Ocount := 03. Mask := 1 Data := 0 4. Temp := Data AND Mask 5. Ocount := Ocount + Temp 6. Data := Data >> 1

7. Outport := Ocount

Figure 25: One’s-count algorithm [Gajski].


chapter 7. storage componentscourses.cecs.anu.edu.au/.../datapath/gajski_datapaths.pdf · 2010. 6....

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