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Page 1: Chapter 8: Input and Outputmhtay/CPSC352/Lecture_PDF/... · 8-1 Chapter 8: Input and Output CPSC 352 Computer Organization Chapter 8: Input and Output. 8-2 Chapter 8: Input and Output

Chapter 8: Input and Outpu t8-1

CPSC 352Computer Organization

Chapter 8: Input and Output

Page 2: Chapter 8: Input and Outputmhtay/CPSC352/Lecture_PDF/... · 8-1 Chapter 8: Input and Output CPSC 352 Computer Organization Chapter 8: Input and Output. 8-2 Chapter 8: Input and Output

Chapter 8: Input and Outpu t8-2

Chapter Contents8.1 Simple Bu s Architectures8.2 Bridge-Based Bu s Architectures8.3 Communication Methodologies8.4 Case Study: Communication on the Intel Pentiu m Architecture8.5 Mass Storage8.6 Input Devices8.7 Output Devices

Page 3: Chapter 8: Input and Outputmhtay/CPSC352/Lecture_PDF/... · 8-1 Chapter 8: Input and Output CPSC 352 Computer Organization Chapter 8: Input and Output. 8-2 Chapter 8: Input and Output

Chapter 8: Input and Outpu t8-3

Simple Bu s Architecture• A simplified motherboard of a personal computer (top view):

Motherboard

I/O Bus

Board traces (wires)

Connectors for plug-in cards

Integrated Circuits

Plug-in card

I/O bus connector

Memory

CPU

Page 4: Chapter 8: Input and Outputmhtay/CPSC352/Lecture_PDF/... · 8-1 Chapter 8: Input and Output CPSC 352 Computer Organization Chapter 8: Input and Output. 8-2 Chapter 8: Input and Output

Chapter 8: Input and Outpu t8-4

Simplified Illustration of a Bus

CPU DiskMemory

Control (C0 – C9)Address (A0 – A31)Data (D0 – D31)Power (GND, +5V, –15V)

Page 5: Chapter 8: Input and Outputmhtay/CPSC352/Lecture_PDF/... · 8-1 Chapter 8: Input and Output CPSC 352 Computer Organization Chapter 8: Input and Output. 8-2 Chapter 8: Input and Output

Chapter 8: Input and Outpu t8-5

100 MHz Bus Clock

CrystalOscillator

1 0 1 0 1 0 1 0

Logical 0 (0V)

Logical 1 (+5V)

10 ns

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Chapter 8: Input and Outpu t8-6

The Synchronous Bus• Timing diagram for a synchronous memory read (adapted from

[Tanenbaum, 1999]).

Φ

Address

Data

MREQ

RD

T1 T2 T3Leading edge

Trailing edge

Data valid

Time

Address valid

Page 7: Chapter 8: Input and Outputmhtay/CPSC352/Lecture_PDF/... · 8-1 Chapter 8: Input and Output CPSC 352 Computer Organization Chapter 8: Input and Output. 8-2 Chapter 8: Input and Output

Chapter 8: Input and Outpu t8-7

The Asynchronou s Bus• Timing diagram for asynchronous memory read (adapted from

[Tanenbaum, 1999]).

Address

MSYN

RD

Data

Time

Memory address to be read

MREQ

SSYN

Data valid

Page 8: Chapter 8: Input and Outputmhtay/CPSC352/Lecture_PDF/... · 8-1 Chapter 8: Input and Output CPSC 352 Computer Organization Chapter 8: Input and Output. 8-2 Chapter 8: Input and Output

Chapter 8: Input and Outpu t8-8

Bus Arbitration

• (a)Simplecentralized busarbitration; (b)centralizedarbitration withpriority levels; (c)decentralized busarbitration.(Adapted from[Tanenbaum,1999]).

Arbiter Bus grant

Bus request

0 1 2 n. . .

(a)

Arbiter

Bus grant level 0

Bus request level 0

0 1 2 n. . .

(b)

Bus grant

Bus request

0 1 2 n. . .

(c)Busy+5V

Bus grant level k

Bus request level k...

Page 9: Chapter 8: Input and Outputmhtay/CPSC352/Lecture_PDF/... · 8-1 Chapter 8: Input and Output CPSC 352 Computer Organization Chapter 8: Input and Output. 8-2 Chapter 8: Input and Output

Chapter 8: Input and Outpu t8-9

BridgeBased

Bus Ar-chitecture

• Bridging withdual Pentium IIXeon proces-sors on Slot 2.

(Source: http://www.intel.com.)

3200 MB/sec 3200 MB/sec

800 MB/sec

100-MHz System Bus

533 MB/sec 800 MB/sec

AGP 100 MHz

133 MB/sec 33-MHz PCI Bus

40 M

B/s

ec

16.7 MB/sec

ISA Bus

USB #2IDE Bus #2

USB #1

SC

SI B

us

1.5 MB/sec

33 MB/sec

IDE Bus #133 MB/sec

Intel 440GX AGPset

(Host Bridge)

400-MHz Core

512KB-2MB Cache

400-MHz Core

512KB-2MB Cache

2GB 100-MHz SDRAM

AGP 2X Graphics

PCI to ISA Bridge

Keyboard Audio

CD-ROMMouseSnapshot

Camera

Hard Disk

Hard Disk

SCSI Interface

Ethernet Interface

Page 10: Chapter 8: Input and Outputmhtay/CPSC352/Lecture_PDF/... · 8-1 Chapter 8: Input and Output CPSC 352 Computer Organization Chapter 8: Input and Output. 8-2 Chapter 8: Input and Output

Chapter 8: Input and Outpu t8-10

Programmed I/OFlowchart for aDisk Transfer

Check status of disk

Disk ready?No

Yes

Send data from memory to disk (when writing) or from disk

to memory (when reading).

Done?No

Yes

Continue

Enter

Page 11: Chapter 8: Input and Outputmhtay/CPSC352/Lecture_PDF/... · 8-1 Chapter 8: Input and Output CPSC 352 Computer Organization Chapter 8: Input and Output. 8-2 Chapter 8: Input and Output

Chapter 8: Input and Outpu t8-11

Interrupt DrivenI/O Flowchart

for a DiskTransfer

Transfer data between disk and memory.

Done?No

Yes

Continue

Return from interrupt. Normal processing

resumes.

Do other processing, until disk issues an

interrupt.

Interrupt causes current processing to stop.

Issue read or write request to disk.

Enter

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Chapter 8: Input and Outpu t8-12

DMA Transfer from Disk to MemoryBypasses the CPU

CPU DiskMemory

Without DMA With DMA

Bus

Page 13: Chapter 8: Input and Outputmhtay/CPSC352/Lecture_PDF/... · 8-1 Chapter 8: Input and Output CPSC 352 Computer Organization Chapter 8: Input and Output. 8-2 Chapter 8: Input and Output

Chapter 8: Input and Outpu t8-13

DMA Flowchart for a Disk Transfer

CPU executes another process

Continue

DMA device begins transfer independent of

CPU

DMA device interrupts CPU when finished

CPU sets up disk for DMA transfer

Enter

Page 14: Chapter 8: Input and Outputmhtay/CPSC352/Lecture_PDF/... · 8-1 Chapter 8: Input and Output CPSC 352 Computer Organization Chapter 8: Input and Output. 8-2 Chapter 8: Input and Output

Chapter 8: Input and Outpu t8-14

Intel Memory and I/ O Address Spaces

AddressFFFFFFFF

00000000

AddressFFFF

0000

MemorySpace

I/OSpace

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Chapter 8: Input and Outpu t8-15

Standard Intel Pentium Read andWrite Bus Cycles

T1 T2 Ti T1 T2 Ti T1

Read Write

TO CPU FROM CPU

READ CYCLE IDLE IDLEWRITE CYCLE

ADDR

ADS#

Valid ValidInvalid Invalid

W/R#

BRDY#

CACHE#

DATA

CLK

Page 16: Chapter 8: Input and Outputmhtay/CPSC352/Lecture_PDF/... · 8-1 Chapter 8: Input and Output CPSC 352 Computer Organization Chapter 8: Input and Output. 8-2 Chapter 8: Input and Output

Chapter 8: Input and Outpu t8-16

Intel Pentium Burst Read Bus CycleT1 T2 T2 T2 T2 Ti

Read

TO CPU TO CPU TO CPU TO CPU

READ READ READ READ

ADDR

ADS#

Valid Invalid

W/R#

BRDY#

CACHE#

DATA

CLK

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Chapter 8: Input and Outpu t8-17

Intel PentiumHold-Hold

AcknowledgeBus Cycle

T1 T2 Ti Ti Ti Ti T1

Read

TO CPU

READ CYCLE

BUS REQ.

NEW BUSMASTER

ADDR

ADS#

Valid

W/R#

BRDY#

CACHE#

DATA

HOLD

HLDA

CLK

Page 18: Chapter 8: Input and Outputmhtay/CPSC352/Lecture_PDF/... · 8-1 Chapter 8: Input and Output CPSC 352 Computer Organization Chapter 8: Input and Output. 8-2 Chapter 8: Input and Output

Chapter 8: Input and Outpu t8-18

A Magnetic Disk with Three Platters

Direction ofarm (comb)

motion

Surface 3Surface 2

Surface 1Surface 0

Top surface not used

Bottom surface not used

Spindle

Platter

Head

SurfaceAir cushion

5 µ m

Comb

Read/write head(1 per surface)

Page 19: Chapter 8: Input and Outputmhtay/CPSC352/Lecture_PDF/... · 8-1 Chapter 8: Input and Output CPSC 352 Computer Organization Chapter 8: Input and Output. 8-2 Chapter 8: Input and Output

Chapter 8: Input and Outpu t8-19

Manchester Encoding• (a) Straight amplitude (NRZ) encoding o f ASCII ‘F’; (b) Manchester

encoding o f ASCII ‘F’.

(a)

Time

Vol

tage

1 0 0 0 1 1 0 = ‘F’

(b)

Time

Vol

tage

1 0 0 0 1 1 0 = ‘F’

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Chapter 8: Input and Outpu t8-20

Organization of a Disk Platter with a1:2 Interleave Factor

Sector

.

.

.

Inter-sector gap

Inter-track gap

Interleave factor 1:2

Track

Track 0

.

.

.

0

8

1

9

2

10

3114

12

5

13

6

14

715

Page 21: Chapter 8: Input and Outputmhtay/CPSC352/Lecture_PDF/... · 8-1 Chapter 8: Input and Output CPSC 352 Computer Organization Chapter 8: Input and Output. 8-2 Chapter 8: Input and Output

Chapter 8: Input and Outpu t8-21

MasterControlBlock

No. surfaces on disk = 4No. tracks/surface = 814No. sectors/track = 32No. bytes/sector = 512Interleave factor = 1:3

Filename

xyz.p

Surface Track Sector

Starting sector, or sector list

Prea

mbl

eFi

les

Free

blo

cks

Bad

blo

cks

1 10 51 12 72 23 4

ab.c 1 10 83 95 22 12 0

1 1 01 1 11 2 5

...

...

1 1 32 5 7

...

CreationDate

LastModified

Owner Protec-tions

11/14/93 11/14/93 16 RWX by10:30:57 19:30:57 Owner

8/18/93 1/21/94 20 RX - All16:03:12 14:45:03 W-Owner

R = ReadW = WriteX = Execute

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Chapter 8: Input and Outpu t8-22

Magnetic Tape• A portion of a magnetic tape (adapted from [Hamache r, 1990]).

File mark

Record

Inter-record gap

Record Record

File

Frames

Page 23: Chapter 8: Input and Outputmhtay/CPSC352/Lecture_PDF/... · 8-1 Chapter 8: Input and Output CPSC 352 Computer Organization Chapter 8: Input and Output. 8-2 Chapter 8: Input and Output

Chapter 8: Input and Outpu t8-23

Magnetic Drum

Fixed read/writeheads (1 per track)Tracks

Sector

Page 24: Chapter 8: Input and Outputmhtay/CPSC352/Lecture_PDF/... · 8-1 Chapter 8: Input and Output CPSC 352 Computer Organization Chapter 8: Input and Output. 8-2 Chapter 8: Input and Output

Chapter 8: Input and Outpu t8-24

Spiral Format for Compact Disk

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Chapter 8: Input and Outpu t8-25

ECMA-23 Keyboard Layout• Keyboard layout for the ECMA-23 Standard (2nd ed.). Shift keys

are frequently placed in the B ro w.

99 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18

F

E

D

C

B

A

Z

Q W E R T Y U I O P

A S D F G H J K L

Z X C V B N M

7 8 9

4 5 6

1 2 3

00 . SP

0

1!

2"

3#

4 5%

6&

7'

8(

9)

0 .= ¬̂

¬

@'

[{

;+

:*

/?

,<

.>

]}

\|

Page 26: Chapter 8: Input and Outputmhtay/CPSC352/Lecture_PDF/... · 8-1 Chapter 8: Input and Output CPSC 352 Computer Organization Chapter 8: Input and Output. 8-2 Chapter 8: Input and Output

Chapter 8: Input and Outpu t8-26

The Dvorak Keyboard Layout

P Y F G C R L

A O E U I D H T N S

Q J K X B M W V Z

?/

}{

– -

"'

,,

.

.

:;

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Chapter 8: Input and Outpu t8-27

Bit Pad with Puck

Puck

Cable to host computer

Coil

Buttons

Page 28: Chapter 8: Input and Outputmhtay/CPSC352/Lecture_PDF/... · 8-1 Chapter 8: Input and Output CPSC 352 Computer Organization Chapter 8: Input and Output. 8-2 Chapter 8: Input and Output

Chapter 8: Input and Outpu t8-28

Mouse and Trackball• A three-button mouse (left) and a three-button trackball (right).

To host

Mousepad (improves traction) Trackball

Mouse

Buttons

To host

Buttons

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Chapter 8: Input and Outpu t8-29

Lightpen• A user selects an object with a lightpen.

Page 30: Chapter 8: Input and Outputmhtay/CPSC352/Lecture_PDF/... · 8-1 Chapter 8: Input and Output CPSC 352 Computer Organization Chapter 8: Input and Output. 8-2 Chapter 8: Input and Output

Chapter 8: Input and Outpu t8-30

Touchscreen• A user selects an object on a touchscreen.

LEDs (sources)

Detector

User breaks beams

Page 31: Chapter 8: Input and Outputmhtay/CPSC352/Lecture_PDF/... · 8-1 Chapter 8: Input and Output CPSC 352 Computer Organization Chapter 8: Input and Output. 8-2 Chapter 8: Input and Output

Chapter 8: Input and Outpu t8-31

Joystick• A joystick with a selection button and a rotatable rod:

Page 32: Chapter 8: Input and Outputmhtay/CPSC352/Lecture_PDF/... · 8-1 Chapter 8: Input and Output CPSC 352 Computer Organization Chapter 8: Input and Output. 8-2 Chapter 8: Input and Output

Chapter 8: Input and Outpu t8-32

Laser Printer• Schematic of a laser printer (adapted from [ Tanenbaum, 1999]).

Paper input

Paper output

The quick brown fox jumps

Heated rollers

Toner cartridge

Cleaner and discharger

Stationary laser source

Page composing

circuitry

Page description from host computer

Charged pattern

Rotating mirror

Page 33: Chapter 8: Input and Outputmhtay/CPSC352/Lecture_PDF/... · 8-1 Chapter 8: Input and Output CPSC 352 Computer Organization Chapter 8: Input and Output. 8-2 Chapter 8: Input and Output

Chapter 8: Input and Outpu t8-33

Cathode Ray Tube• A CRT with a single electron gun:

Horizontal control

Vertical control

Intensity control

Electron gun

Vertical deflection plate

Vacuum

GridHorizontal deflection plate

Phosphor coated screen

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Chapter 8: Input and Outpu t8-34

Display Controller• Display con-

troller for a640×480 colormonitor(adapted from[Hamacher etal., 1990]).

To horizontal deflection plate control

To vertical deflection plate control

10 9

To

elec

tron

gun

(g

rid)

con

trol Red

Green

Blue8

LUT loaded from computer

Screen image

loaded by computer

Clock Column counter

(mod 640)

Row counter

(mod 480)

Address

Out

put

Inpu

t

Out

put

Add

ress

8Input

RAM frame buffer

RAM LUT

8

8

One output pulse per 640 columns