chapter06 cpu design

8/7/2019 Chapter06 CPU Design

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2011/3/22 2

Specifying a CPU

� Fetch cycle± Fetch an instruction from memory, then go to the

decode cycle.� Decode cycle

± Decode the instruction-that is, determine whichinstruction has been fetched, then go to the

execute cycle fit that instruction.

� Execute cycle± Execute the instruction, then go to fetch the next

instruction.



2011/3/22 3

Generic CPU state diagram



2011/3/22 4

Specifications for a very simple CPU

� To illustrate the CPU design process,

consider this small and somewhat impractical

CPU. It can access 64 bytes of memory, eachbyte being 8 bits wide.

� The CPU does this by outputting 6-bit

address on its output pins A[5..0] and reading

in the 8-bit value from memory on its inputsD[7..0].



2011/3/22 5

Specifications for a very simple CPU

� AC (same as in SAP-1)± An 8-bit accumulator labeled AC

� AR (MAR in SAP-1)± A 6-bit address register

� PC (same as in SAP-1)± A 6-bit program counter

� DR (B in SAP-1 & MBR in SAP-2)± A 8-bit data register

� IR (same as in SAP-1)± A 2-bit instruction register



2011/3/22 6

Instruction set for the very simple CPU

Instruction Instruction Code Operation

ADD 00AAAAAA ACnAC+M[AAAAAA]

AND 01AAAAAA ACnAC^M[AAAAAA]

JMP 10AAAAAA GOTO AAAAAA

INC 11AAAAAA ACnAC+1



2011/3/22 7

Fetching Instructions From Memory

� FETCH1� ARnPC

� FETCH 2� DRnM, PCnPC+1

� FETCH 3� IRnDR[7..6], ARnDR[5..0]



2011/3/22 8

Fetch cycle for the very simple CPU



2011/3/22 10

Fetch and decode cycles for the very

simple CPU



2011/3/22 12

Executing Instruction

� JMP

± JMP1: PCn DR[5..0]

� INC± INC1: ACn AC + 1



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Complete state diagram for the very

simple CPU



2011/3/22 14

Establishing Required Data Paths

� The operations associated with each state for

this CPU are

� FETCH1: ARnPC

� FETCH 2: DRnM, PCnPC+1

� FETCH 3: IRnDR[7..6], ARnDR[5..0]

� ADD1: DRnM

� ADD2: ACnAC+DR

� JMP1: PCn DR[5..0]

� INC1: ACn AC + 1



2011/3/22 15

Establishing Required Data Paths

� To design the data paths, we can take one of

two approaches.

± Direct path� Between each pair of components that transfer data.

± Bus

� Within the CPU and route data between components via

the bus.



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Preliminary register section for the very

simple CPU



2011/3/22 18

Final register section for the very simple

CPU



2011/3/22 19

Design a very simple ALU

� The ALU for this CPU performs only twofunctions

± ADDs its two inputs or � Using a standard 8-bit parallel adder

± Logically ANDs its two inputs� Using eight 2-input AND gates

� The outputs of the adder and AND gates areinput to an 8-bit 2 to1 multiplexer.

� The control input of the MUX is called S (for select)



2011/3/22 20

A very simple ALU



2011/3/22 21

Designing The Control Unit Using

Hardwired Control

� There are two primary methodologies for

designing control.

± Hardwired control� Uses sequential and combinatorial logic to generate

control signals

± Microsequenced control

� Uses a lookup memory to output the control signals



2011/3/22 22

Designing The Control Unit Using

Hardwired Control

� The simplest control unit has threecomponents

± Counter � Contains the current state

± Decoder � Takes the current states and generates individual signals

for each state

± Logic� Take the individual state signals and generate the control

signals for each component, as well as the signals tocontrol the counter



2011/3/22 23

Generic hardwired control unit



2011/3/22 24

Generic hardwired control unit

� For this CPU, there are a total of 9 states.

� 4-bit counter needed.



2011/3/22 25

Control signals for Counter

� INC

± Asserted when the control unit is traversing sequential states,

during FETCH1, FETCH2, ADD1, and AND1

� CLR

± Asserted at the end of each execute cycle to return to the

fetch cycle; this happens during ADD2, AND2, JMP1, and

INC1

� LD± Asserted at the end of fetch cycle during state FETCH3



2011/3/22 26

Hardwired control unit for the Very Simple

CPU



2011/3/22 27

Control signal generation for the Very

Simple CPU



2011/3/22 28

Design Verification

� 0: ADD 4

� 1: AND 5

� 2: INC

� 3: JMP 0

� 4: 27H

� 5: 39H



2011/3/22 29

Execution Trace



2011/3/22 30

Design And Implementation Of A

Relatively Simple CPU

� Specifications for relatively simple CPU

� Fetching and decoding instruction

� Executing instruction

� Establishing data paths

� Design of a relatively simple ALU

� Designing the control unit using hardwiredcontrol

� Design verification



2011/3/22 31

Design And Implementation Of A

Relatively Simple CPU

� 16-bit address register, AR

� 16-bit program counter, PC

� 8-bit data register, DR

� 8-bit instruction register, IR

� 8-bit temporary register, TR � 64K bytes of memory (16-bit address)



2011/3/22 32

Specifications for relatively simple CPU



2011/3/22 33

Fetching and decoding instruction



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Instruction format� 25 : JUMP 1234H

� The instruction would be stored in memory as

25 : 0000 0101 (JUMP) ± OP Code

26 : 0011 0100 (34H) ± low-order 8 bits of address

27 : 0001 0010 (12H) ± high-order 8 bits of address

� Save memory !



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� NOP± NOP1 : (No operation)

� LDAC± LDAC1 : DRnM, PCnPC+1, ARnAR+1 (high-order half

address)

± LDAC2 : TRnDR, DRnM, PCnPC+1 (TR ± low-order)

± LDAC3 : ARnDR, TR (DR ± high-order)

± LDAC4 : DRnM

± LDAC5 : ACnDR

�FETCH1: ARnPC

�FETCH 2: DRnM, PCnPC+1

�FETCH 3: IRnDR, ARnPC (low-order half address)



2011/3/22 36

Executing instruction

� STAC

± STAC1 : DRnM, PCnPC+1, ARnAR+1

± STAC2 : TRnDR, DRnM, PCnPC+1± STAC3 : ARnDR, TR

± STAC4 : DRnAC

± STAC5 : MnDR

� MVAC and MOVR

± MVAC1 : RnAC

± MOVR1 : ACnR



2011/3/22 37

� JMPZ and JPNZ± JMPZY1 : DRnM, ARnAR+1

± JMPZY2 : TRnDR, DRnM

± JMPZY3 : PCnDR, TR

± JMPZN1 : PCnPC+1

± JMPZN2 : PCnPC+1

± JPNZY1 : DRnM, ARnAR+1± JPNZY2 : TRnDR, DRnM

± JPNZY3 : PCnDR, TR

± JPNZN1 : PCnPC+1

± JPNZN2 : PCnPC+1

�FETCH1: ARnPC

�FETCH 2: DRnM, PCnPC+1

�FETCH 3: IRnDR, ARnPC (low-order half address)



2011/3/22 38

Executing instruction

� The remaining instruction



2011/3/22 39

Complete state diagram for the Relatively

Simple CPU



2011/3/22 40

Establishing data paths

� Refer to page 242

� AR and PC must be able to perform a parallel

load and increment� DR, IR, R, and TR must be able to load data

in parallel

� AC will require a lot of work, as will Z



2011/3/22 42

Generic bidirectional data pin



2011/3/22 43

Final register section for the Relatively

Simple CPU



2011/3/22 44

Design of a relatively simple ALU

�� All transfers that modify the contents of ACAll transfers that modify the contents of AC

� Indicate the source of their operands ± arith sec

� Rewriting each operation as the sum of twovalues and a carry ± implemented by adder



2011/3/22 45

A relatively Simple ALU

Arith secLogic sec



2011/3/22 46

Designing the the control unit using

hardwired controlState generation for a Relatively Simple CPU Input to CU



2011/3/22 47

control signal values for a Relatively

Simple CPU - part� Reference table 6.6 =ILDAC^T5



2011/3/22 49

Register section for he relatively Simple

CPU using multiple buses



2011/3/22 50

Exercise

� 2, 6, 7, 10, 19



2011/3/22 51

Real World Example: internal architecture

of the 8085 microprocessor ± Self study

� ALU

� Register section

� Address buffer and address/data buffer

� Interrupt control block

� Control section

� Instruction decoder and machine cycleencoding block

� Serial I/O control block



2011/3/22 52

Internal organization of the 8085

microprocessor

chapter06 cpu design

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