chapter5 (1)

Pulse and Digital Circuits Venkata Rao K., Rama Sudha K. and Manmadha Rao G.

Chapter-5 Non-linear Waveshaping: Clamping Circuits

1. Design a diode clamper shown in Fig. 5p.1 to restore the positive peaks of the

input signal to a voltage level to 5 V. Assume the diode cut-in voltage is 0.5 V, f = 1 kHz, Rf = 1 kΩ , Rr = 200 kΩ and RC = 20 T.

Fig. 5p.1 The given clamping circuit with reference voltage VR

Solution:

We know, rf RRR = 3 31 10 200 10 14.14 kΩ

We have, RC = 20 T 20 T

CR

= 3

3

20 1 101.414 F

14.14 10

As the positive peak is required to be clamped to + 5 V, the reference voltage source is chosen as vo = VR + VD 5= VR + 0.5 VR = 4.5 V

2. For the excitation as in Fig.5p.2 and the clamping circuit [Fig. 2.1], calculate and plot to scale the steady-state output. Rf = Rs =100 , R= 100 K, C = 0.1 F T1 = 100 s T2 =

1000 s.

(a) (b)

Fig.5p.2 (a)The given input and the clamping circuit Solution: When the unsymmetrical square wave shown in Fig. 5p.2(b) is transmitted through the clamping circuit, the output voltage takes the form shown in Fig. 2.1 in the steady-state.

© Dorling Kindersley India Pvt. Ltd 2010

1


Fig.2.1 Steady-state output

This waveform can be plotted by evaluating V1, ' , V1V 2 and '2 . V

We have from Eq. (5.6)

(i) V = f

sf

R

RR V1 –

R

RR s ' 2V

100 = 1)100

100100( V

– ')

100000

100100000( 2V

100 = 2V1 – 1.001 ' 2V (1)

From Eq. (5.9),

V = f

sf

R

RR '1V –

R

RR sV2

100 = 2 – 1.001V'1V 2 (2)

From Eq. (5.10)

'1V = V1

CRR

T

sfe )(1

= V1

6

6

101.0)100100(

)10100(

e '

1V = V1e-5 = (6.738 10 -3)V1 (3) From Eq. (5.11)

' = V2V 2 CRR

T

se )(2

= V2 6

6

101.0)100100000(

)101000(

e = V2 e–0.0999

'2V = 0.905V2 (4)

From Eqs. (1)–(4), we get V1, , V'1V 2 and '

2 as: V'

1V = (6.738 10-3)V1 (5) ' = 0.905V2V 2 (6)

100 = 2V1 – 1.001 '2 (7) V

100 = 2 – 1.001V'1V 2 (8)

Solving Eqs. (5)–(8), we get: V1 = 4.83 V, = 0.03258 V '

1V


2


V2 = –99.823 V, ' = –90.894 V 2V

Note: (V1 – '2 ) and ( ' –VV 1V 2) should, in fact, be V which is 100 V here. But due to

approximation in calculations, V is not exactly 100 V.

3. Sketch the steady-state output voltage for the clamper circuit shown in Fig. 5p.3

and locate the output dc level and the zero level. The diode used has Rf = 100 , Rr = 500 k , . C is arbitrarily large and R = 20 k 0V . The input is a +20 V

square wave with 50 per cent duty cycle.

Fig. 5p.3 The given clamping circuit for Problem 3

Solution:

Duty cycle = 0.5 = 21

1

TT

T

T1 = T2

We know clamping theorem, R

R

TV

TV f22

11 ,

where V2 = V – V1

R

R

TVV

TV f 21

11

)(

31

1

1020

100

)40(

V

V

V1 = 0.199V As per given data, C is large, hence there is no tilt in forward and reverse directions.


3


4. For the circuit shown in Fig. 5p.4(a), Rs = Rf = 50 , R=10 k , Rr= , C=2.0 F ,the

input varies as shown in Fig.5p.4(b). Plot the output waveform.

(a) (b)

Fig. 5p.4 (a) The given input, (b) and the clamping circuit Solution: D conducts from t = 0.1 ms to 0.2 ms as in Fig.4.1. (i) At t = 0.1 ms

vo = 100

505= 2.5 V

During the period 0.1 to 0.2 ms, D is ON and as the input is constant the output decays and at t = 0.2 ms

vo = 2.5e)102)(5050(

101.06

3

=2.5e–0.5=1.516 V

Fig. 4.1 Equivalent circuit when D is ON

The voltage across the capacitor = 5 – 2Av 1.516 = 1.968 V. (ii) At t = 0.2 ms, D is OFF as in Fig. 4.2.


4


Fig. 4.2 Equivalent circuit when D is OFF vo = –10 – 1.968 = –11.968 V. During 0.2 to 0.3 ms, output decays and at t = 0.3 ms

vo = –11.968e)102)(1000050(

101.06

3

= –11.90 V

Av = –10 + 11.90 = 1.90 V

Av = 1.90 V (v) vo at t = 0.3 ms, D is ON. The equivalent to be considered is in Fig. 4.3.

Fig. 4.3 Circuit to calculate the output

vo = 2

90.110 = 4.05 V

During 0.3–0.4 ms, the output decays and at t = 0.4 ms: vo = 4.05e–0.5 = 2.45 V. The output voltage now varies as in Fig. 4.4.

Fig. 4.4 Steady-state output waveform

5. The input as shown in Fig. 5p.5(a) is applied to the clamping circuit shown in Fig. 5p.5(b) with Rs = Rf = 100 , R = 10 k , Rr = , C = 1.0F; = 0. Draw the output

waveform and label all the voltages.

V


5


(a) (b) Fig. 5p.5 (a) The given input; and (b) the given clamping circuit Solution: (i) At t = 0 ms, the input is –10 V, the diode conducts as shown in Fig. 5.1.

vo = vs

sf

f

RR

R

= –10

200

100 = –5 V

Fig. 5.1 Equivalent circuit when D is ON

(ii) During the period from 0 to 0.1 ms, as the input remains constant, the output decays exponentially with the time constant.

f = (Rs + Rf)C = (100+100)1 = 200 610 s = 0.2 ms

vo (t = 0.1 ms) = 5 2.0

1.0

e = –3.032 V. The voltage across the capacitor = = –10 + 2Av 3.032 = –3.936 V. At t = 0.1 ms, input rises to 10 V and the diode is OFF. The equivalent circuit is as shown in Fig. 5.2.


6


Fig. 5.2 Equivalent circuit when D is OFF

vo = (10 + 3.936) 1.010

10

= 13.798 V

As the input remains constant from 0.1 to 0.3 ms, the output decays as:

vo(t = 0.3 ms) = 13.7983

3

101.10

102.0

e = 13.52 V The voltage across the capacitor = = 10 – 13.52 = –3.52 V AvAt t = 0.3 ms, vs abruptly falls to –5 V

vo(t = 0.3 ms) = (–5 + 3.52) 100100

100

= –1.48

2

1 = –0.74 V

As the input remains constant from 0.3 to 0.4 ms, the output decays:

vo(t = 0.4 ms) = –0.74 2.0

1.0

e = –0.448 V. The output waveform is shown in Fig. 5.3 .

Fig. 5.3 Steady-state output waveform

6. A clamping circuit and input applied to it are shown in Fig. 5p.6. Assume that C is quite large. Find at which voltage level the positive peak is clamped in the output if


7


T1 = 1 ms, T2 = 1 s, Rf = 100 and R = 100 k .

Fig. 5p.6 The given input and clamping circuit for Problem 6 (Hint: Use clamping theorem) Solution:

We know clamping theorem, R

R

TV

TV f22

11

R

R

TVV

TV f 21

11

)(

361

31

10100

100

101)10(

101

V

V

611 10)10( VV

V10

10)101(5

1

561

V

V

101010 512 VVV V

7. Calculate and draw the steady-state output waveform of the circuit in Fig. 5p.7. Assume Rf = 50 , R r = 500 k and T 1 = T2 = 1 ms.

Fig. 5p.7 The given clamping circuit with large VYY


8


Solution: At t = 0+, D ON and vo = 0 V. Then capacitor charges during ON period is VA = vs – vo = 40 – 0 = 40 V At t = T1+, D OFF and vo = vs – VA = 0 – 40 = –40 V.

At t = T2–,

31

3 6

1 10( )

500 10 0.1 10o 40 40 40 0.98 39.2

T T

v e e

V

VA = vs – vo = 0 +39.2 = 39.2 V At t = T2+, vo = vs – VA = 40 – 39.2 = 0.8 V

At t = T3–,

3

6

1 10

50 0.1 10o 0.8 0.8 0 0v e

V

VA = vs – vo = 40 – 0 = 40 V

Fig. 7.1 The output waveform

8. Design a biased clamping circuit to derive the output voltage as shown in Fig. 5p.8(b), given the input as shown in Fig.5p.8(a): f = 1000 Hz, Rf = 100 , Rr = 1 M and

10T

RC. D is ideal.

(a) (b) Fig.5p.8 (a) The given input to the clamping circuit; and (b) the required output Solution:

We know rf RRR = 3100 1 10 10 kΩ

We have, RC = 10T


9



10

R

TC

10 =

3

3

10 1 101 F

10 10

As the negative peak is required to be clamped to – 5 V, the reference voltage source is chosen as vo = VR + VD –5= VR + 0 VR = –5V

Fig. 8.1The biased clamping circuit

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