characterization of integrated circuit packaging materials

v

Contents

Foreword xi

Preface to the Reissue of the Materials Characterization Series xiii

Preface to Series xiv

Preface to the Reissue of Integrated Circuit Packaging Materials xv

Preface xvi

Contributors xix

IC PACKAGE RELIABILITY TESTING

1.1 Introduction 1

1.2 In-Process Quality Measurements 2Wire Bond Quality 3, Die Attach Quality 4, Other Process Control Measurements 8

1.3 Package-Oriented Reliability Testing of Finished Devices: Moisture Testing 10Failure Analysis of Moisture-Related Failures 11, Root Causes of Corrosion Failures 12

1.4 Package-Oriented Reliability Testing of Finished Devices: Thermal Cycle Testing 14Bond Failures: Bond Pad Contamination 16, Intermetallic Formation and Other Elements of Bond Formation 18

1.5 Reliability Test Preconditioning: A New Direction 23

1.6 Summary 25

MOLD COMPOUND ADHESION AND STRENGTH

2.1 Introduction 27

2.2 Thermodynamic Consideration of Adhesion 28Work of Adhesion 28, The Work of Adhesion from Contact Angle Measurements 30, Work of Adhesion in the Presence of Moisture and Lubricants 30

2.3 Adhesive Strength for Various Mold Compound Types 31Adhesive Strength Measurements 31, Mold Compound Types 31, Adhesive Strength of Various Mold Compounds 32

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vi Contents

2.4 Various Factors Which Infl uence Adhesion Strength 33Effects of Lead Frame Oxides 34, Effects of Different Lead Frame Materials 38, Effects of Adhesion Promoters 40, Effects of Various Mold Release and Processing Aids 41, Effects of Mold Compound Rheology 42

2.5 Role of Adhesion in Surface Mount Operations 43Moisture Absorption and Its Effect on Adhesion 45, Package Delamination and Cracking in VPR and SDIP 45

2.6 Role of Adhesion in Package Reliability 48Metal Line Movement 48, Highly Accelerated Stress Test (HAST) 49

2.7 Physical Characterization of Mold Compounds 49Physical Properties of Various Mold Compounds 49, Cure Kinetics 51

2.8 Outlook for Future Mold Compounds 53

2.9 Summary 54

MECHANICAL STRESS IN IC PACKAGES

3.1 Introduction 57

3.2 Stress and Strain Relations: An Overview 58

3.3 Stress Generation in IC Packages 61

3.4 Tools for Stress Determination in IC Packages 63Finite Element Analysis 64, Strain Gauges for Stress Analysis 64, Moire Interferometry 64, Indirect Stress Determination 64

3.5 Application of Techniques to IC Packaging Problems 64Eutectic Die Attach 65, Passivation Damage at Chip Corners 66, Ball Bond Stresses 68, Solder Refl ow Damage 69, Tape Automated Bonding Inner Lead Stresses 72, Filler Particle-Induced Damage 73, Mechanical Warpage 73, Mechanical Damage 74, Parametric Shifts Related to Package Stresses 74

3.6 Solder Joint Stress and the Coffi n–Manson Relation 75

3.7 Summary 76

MOISTURE SENSITIVITY AND DELAMINATION

4.1 Introduction 79

4.2 Moisture/Refl ow Sensitivity Evaluations 81Moisture Sensitivity Classifi cation 81, Moisture Absorption: Preconditioning 83, Solder Refl ow Damage 85

4.3 Impact on Temperature-Cycle Performance 91

4.4 Impact on THB Performance 92

4.5 Moisture Desorption: Bake-Out 93

4.6 Summary 94

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Contents vii

THERMAL MANAGEMENT

5.1 Introduction 97

5.2 IC Package Thermal Characteristics 99

5.3 Factors Affecting Package Thermal Resistance 105Package Design 105, Package Material Thermal Conductivity 107, Die Attach Material 111, Package Size and Die Size Effects 111, Package Defects 112, PCB Effect on Thermal Performance 113, The Effect of Neighboring Components 114, Heat Fins 115

5.4 Thermal Design Challenges of Multi-Chip Modules 115

5.5 Summary 116

ELECTRICAL PERFORMANCE OF IC PACKAGES

6.1 Introduction 121

6.2 Designing for Performance 123

6.3 Electrical Models for Packages and Interconnects 125Low Frequency Models 125

6.4 Propagation Delay and Packaging 127Clock Frequency, Bandwidth, and Rise Time 127, Propagation Delay 128, RC Delay 128, Time of Flight 128

6.5 Switching Noise 130

6.6 Signal Integrity 134

6.7 Crosstalk 135

6.8 Materials and Design Trends for High-Performance Packaging 138

6.9 Summary 143

SOLDERABILITY OF INTEGRATED CIRCUITS


7.2 Electronic Soldering Basics 146Soldering Defi nitions 146, Solder Joints for Electronic Packages 147, Solderability Defect Classifi cations 147

7.3 IC Package Designs, Materials, and Solderability Test Methods 148Through-Hole Package Designs and Materials 148, Surface Mount Package Designs and Materials 150, Tape Automated Bonding Package Design and Materials 152

7.4 IC Solderability Defects 152Through-Hole Solderability Problems 152, SMT Solder Electroplating Process Defects 155, SMT Lead Finish Defects 158, SMT Solderability Problems Due to Mechanical Damage 159, TAB Solderability Problems 161

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viii Contents

7.5 Solderability of IC Packages to PCBs 162Printed Circuit Boards 162, Electronic Solders, Fluxes, and Pastes 163

7.6 Summary 165

HERMETICITY AND JOINING IN CERAMIC IC PACKAGES


8.2 Materials for Hermetic IC Packaging 169

8.3 Hermeticity Testing—History 173

8.4 Theory of Hermeticity Testing 174

8.5 Gross-Leak Testing Methodology 177

8.6 Hermeticity Failure Analysis 178

8.7 Alternatives to Hermetic Packaging 182

8.8 Summary 183

ADVANCED INTERCONNECT TECHNOLOGY


9.2 MCM Technology Classifi cations 188

9.3 MCM Materials Selection 190Substrate Materials and Design 191, Polyimide Dielectrics 194, Test Substrates 195, Power Density 196

9.4 Die Mounting and Stress 198Die Bond Adhesive Strength 199, Flip-Chip Technology 200

9.5 Die Interconnection 201Wire Bond Technology 201, Bond Optimization 203

9.6 MCM Packages 204Substrate-Based Packages 204

9.7 Summary 205

APPENDIX: TECHNIQUE SUMMARIES

1 Acoustic Microscopy (C-AM) 209

2 Atomic Absorption Spectrometry (AAS) 213

3 Auger Electron Spectroscopy (AES) 214

4 Ceramic Plate Test (CPT) for Evaluating Solderability of IC Devices 215

5 Coulometric Method for Solderability Evaluation 218

6 Decapsulation Techniques 222

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Contents ix

7 Differential Scanning Calorimetry (DSC) 225

8 Dynamic Mechanical Analysis 227

9 Dynamic Secondary Ion Mass Spectrometry (Dynamic SIMS) 229

10 Electron Probe X-Ray Microanalysis (EPMA) 230

11 Energy-Dispersive X-Ray Spectroscopy (EDS) 231

12 Finite Element Analysis (FEA) 232

13 Fourier Transform Infrared Spectroscopy (FTIR) 235

14 Inductively Coupled Plasma Mass Spectrometry (ICPMS) 236

15 Inductively Coupled Plasma-Optical Emission Spectroscopy (ICP-OES) 237

16 In Situ Strain Gauges 238

17 Ion Chromatography 240

18 Mechanical Testing in IC Packaging 243

19 Scanning Electron Microscopy (SEM) 247

20 Scanning Tunneling Microscopy (STM) and Scanning Force Microscopy (SFM) 248

21 Static Secondary Ion Mass Spectrometry (Static SIMS) 249

22 Thermogravimetric Analysis (TGA) 250

23 Thermomechanical Analysis (TMA) 252

24 Torsional Braid Analysis (TBA) 255

25 Wetting Balance Method to Evaluate the Solderability of IC Devices 258

26 X-Ray Laminography 260

27 X-Ray Photoelectron Spectroscopy (XPS) 263

28 X-Ray Radiographic Inspection 264

Index 267

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xi

Foreword

What do we mean by the term “packaging” of semiconductor integrated circuits? If we adopt the recently formulated viewpoint that “packaging bridges the gap between silicon and systems,” then it is evident that packaging is much more than the tra-ditional encapsulation of the silicon chip. It not only offers opportunities for major advances in microsystem performance, but also it presents serious challanges for choosing product-conforming designs and interconnections, low-cost materials and processes, and for building in reliability for cost-effective ownership.

With this new defi nition of “packaging” in mind, we can clearly see two major driving forces for the development of IC packages which are active today and are expected to continue to be active far into the next century in a considerably enhanced and more vigorous manner. The fi rst driver is the pulling force of commercial and military markets. They demand better power management, low-noise operation, and reliability under even extreme environmental conditions—all of this at equal or preferably lower cost than today. This market pull is projected to accelerate due to higher levels of integration and wider penetration of commercial and military product segments. Eventually, this will drive semiconductor electronics to have a dominant share of the overall world economy—and packaging will increasingly be the enabler.

The second driver is an intensive technology push, nourished by an increase in the stream of industrial, university, and government laboratory investigations. Empha-sis is placed on developing computer simulations of the electrical, thermal, and mechanical stress performance of interconnections and packages. Also, materials characterization of package components, reliability prediction, and simulation of failure mechanisms of IC components and systems are receiving increased attention. This technology push continues unabated today and, because of its fundamental nature, it is anticipated to increase in importance in the future, with prime emphasis placed on knowledge of materials and processes. After all, they not only determine the electrical and thermal performance of packages, but to a great extent the reli-ability characteristics as well. With a solid data base of materials and process char-acteristics, there is hope that processes can be controlled so tightly that building in reliability (as opposed to testing in) will become a reality, making testing of IC systems more manageable.

In view of this, this volume, Characterization of Integrated Circuit Packaging Materials, is a most welcome addition to the book series on Materials Character-ization. It covers a wide spectrum of materials employed in the packaging of IC components and systems and familiarizes the reader with generic aspects of select-ing, measuring, and processing these materials. The scope stretches from computer

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xii Foreword

simulation of mechanical stress in these materials to the reliability assessment of fi nished semiconductor subsystems; also, adhesion between diverse materials, her-meticity and moisture sensitivity, molding compounds and solderability aspects, and thermal and electrical performance are discussed.

This book will be especially welcomed by those readers—even non-specialists—who need to understand the essentials of characterization techniques so that they can intelligently identify the key materials features important to their specifi c packaging application. Most often this will require an appreciation of the trade-offs between seemingly confl icting materials characteristics and an appreciation of the manner in which carefully selected processes can be used to enhance the desired materials char-acteristics. The importance of the knowledge of packaging materials and process data cannot be overemphasized for high reliability IC systems. In addition, this goal must be accomplished through cost-effective manufacturing.

It is hoped that this book, grown out of many years of experience and written by experts in their respective fi elds, will stimulate readers to get involved in (and even to get enchanted by) the complexities and possibilities of materials and process charac-teristics so that they may contribute to the promising potential of IC systems.

Dr. Walter H. SchroenTI Fellow

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xiii

Preface to the Reissue of the Materials Characterization Series

The 11 volumes in the Materials Characterization Series were originally published between 1993 and 1996. They were intended to be complemented by the Encyclopedia of Materials Characterization, which provided a description of the analytical tech-niques most widely referred to in the individual volumes of the series. The individual materials characterization volumes are no longer in print, so we are reissuing them under this new imprint.

The idea of approaching materials characterization from the material user’s per-spective rather than the analytical expert’s perspective still has great value, and though there have been advances in the materials discussed in each volume, the basic issues involved in their characterization have remained largely the same. The intent with this reissue is, fi rst, to make the original information available once more, and then to gradually update each volume, releasing the changes as they occur by on-line subscription.

C. R. Brundle and C. A. Evans, October 2009

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xiv

Preface to Series

This Materials Characterization Series attempts to address the needs of the practical materials user, with an emphasis on the newer areas of surface, interface, and thin fi lm microcharacterization. The Series is composed of the leading volume, Encyclope-dia of Materials Characterization, and a set of about 10 subsequent volumes concen-trating on characterization of individual materials classes.

In the Encyclopedia, 50 brief articles (each 10 to 18 pages in length) are presented in a standard format designed for ease of reader access, with straightforward tech-nique descriptions and examples of their practical use. In addition to the articles, there are one-page summaries for every technique, introductory summaries to group-ings of related techniques, a complete glossary of acronyms, and a tabular compari-son of the major features of all 50 techniques.

The 10 volumes in the Series on characterization of particular materials classes include volumes on silicon processing, metals and alloys, catalytic materials, inte-grated circuit packaging, etc. Characterization is approached from the materials user’s point of view. Thus, in general, the format is based on properties, processing steps, materials classifi cation, etc., rather than on a technique. The emphasis of all vol-umes is on surfaces, interfaces, and thin fi lms, but the emphasis varies depending on the relative importance of these areas for the materials class concerned. Appendixes in each volume reproduce the relevant one-page summaries from the Encyclopedia and provide longer summaries for any techniques referred to that are not covered in the Encyclopedia.

The concept for the Series came from discussion with Marjan Bace of Manning Publications Company. A gap exists between the way materials characterization is often presented and the needs of a large segment of the audience—the materials user, process engineer, manager, or student. In our experience, when, at the end of talks or courses on analytical techniques, a question is asked on how a particular material (or processing) characterization problem can be addressed the answer often is that the speaker is “an expert on the technique, not the materials aspects, and does not have experience with that particular situation.” This Series is an attempt to bridge this gap by approaching characterization problems from the side of the materials user rather than from that of the analytical techniques expert.

We would like to thank Marjan Bace for putting forward the original concept, Shaun Wilson of Charles Evans and Associates and Yale Strausser of Surface Science Laboratories for help in further defi ning the Series, and the Editors of all the indi-vidual volumes for their efforts to produce practical, materials user based volumes.

C. R. Brundle C. A. Evans, Jr.

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xv

Preface to the Reissue of Characterization of Integrated Circuit Packaging Materials

Eighteen authors (ten of them from Texas Instruments) were involved in originally putting this comprehensive volume together. There have been signifi cant advances in IC packaging since the original publication, but the basic functions of the packaging remain the same, and the approaches discussed here towards the analysis and charac-terization of the wide range of materials involved remain valid, with the underlying principles unchanged. Following the reissue of the volume in close to its original form, it is our intention to release updates and new material as on-line downloads, as they become available.

C. R. Brundle and C. A. Evans, December 2009

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xvi

Preface

Market opportunities have driven a dramatic increase in the functionality of inte-grated circuits (ICs), placing greater demands on the performance and reliability of the IC package. The IC package serves several functions, including

• mechanical protection for the die during assembly and use

• electrical interconnection between the die and the surrounding system

• a thermal path for heat removal from the die

• a geometric form compatible with the system design.

Over the past decade there have been increases in die sizes from 1 mm2 to over 400 mm2, in leads on a package from 8 to over 500, and in power dissipation from 10 mW to over 35 W, with power densities approaching 100 W/cm2. The encapsulation of very large die in plastic packages produces interfacial shear stresses that can lead to failure during temperature cycling. Also, surface mount technology exposes the body of the plastic package to such high temperatures during assembly that moisture-re-lated mechanical failure of the package can occur. When one considers the demands now placed on the IC package and the relatively high reliability of the IC die, one realizes that the package has become the primary factor limiting the performance and reliability of the fi nished IC product.

The selection of materials for both hermetic and non-hermetic packages is infl u-enced by the mechanical, electrical, and thermal requirements of the device and its surrounding electrical system and by the environment to which the device will be exposed. The reliability of the fi nished device will depend not only on the character-istics of the individual materials but also on the interaction of package materials at interfaces during exposure to such stresses as thermal gradients, temperature cycling, moisture, and contamination. In the development of improved IC packages, the matching of mechanical properties at interfaces has become an important factor.

This volume addresses the characteristics of IC packages and materials-related problems in the industry. It is unlike most other volumes in the Materials Char-acterization series in that it does not deal with a distinct class of materials, or even a group of materials related by characteristics. Instead, it discusses a group of materials that are, in many cases, related only because they are used together in IC packages. The materials included in this group may also be discussed in other volumes in this series—Characterization of Metals and Alloys, Characterization of Polymers, and Characterization of Ceramics, for example. It is the purpose of this volume to concentrate on the characteristics of these materials that impact the

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Preface xvii

performance and reliability of IC packages and the techniques for measuring these characteristics.

The conventional approach for a text on the characterization of IC packaging mate-rials would describe the techniques in detail and provide packaging examples. This volume takes a different perspective. It is designed to help the reader understand the important characteristics of IC packaging materials and the various techniques available for measuring them. It will enable the characterization non-specialist to select and communicate with the appropriate characterization lab. It is intended as a practical guide for engineers working in IC packaging, assembly, and reliability, as well as an application-specifi c reference for a graduate-level course in materi-als science. The chapters of this volume are based on the key characteristics and critical technological problems of IC packaging. Characterization techniques are described through examples in which the benefi ts and trade-offs of the techniques are demonstrated. The reader is referred to the appendix for more information on the characterization techniques. The appendix includes one-page summaries of techniques discussed in more detail in the lead volume of this series, Encyclopedia of Materials Characterization, and longer summaries of techniques that are unique to this volume.

Chapter 1, IC Package Reliability Testing, describes the methods for evaluating the reliability of IC packages through in-process measurements and through accel-erated stress tests on fi nished packages. The integrity of critical internal interfaces is demonstrated to be the key factor in package reliability. Factors which affect the adhesion of the mold compound to the lead frame and die are covered in Chapter 2, Mold Compound Adhesion and Strength. These factors are diffi cult to measure, but some properties of the materials’ surfaces, such as the wetting angle and the work of adhesion, can be measured to indirectly predict adhesion performance. The impact of mold compound adhesion on assembly operations and reliability is discussed, and future directions in mold compound development are reviewed.

Chapter 3, Mechanical Stress in IC Packages, demonstrates how the different mechanical properties of the materials within the package can lead to internal stresses during temperature cycling. Finite element modeling is used to predict these stresses, and in situ strain gauges directly measure stresses at the die sur-face. Chapter 4, Moisture Sensitivity and Delamination, describes how moisture absorbed from the atmosphere by the mold compound during shipping or storage can produce high stresses and severe damage to the plastic package during surface mount assembly. Acoustic microscopy is shown to be effective in detecting package cracks and delaminations nondestructively. Acoustic microscope studies indicate that delamination at the surface of the die is the primary cause of electrical failure during temperature cycling.

Chapter 5, Thermal Management, describes how the exponential rise in power densities over the past 20 years has turned thermal management into a critical design issue. Techniques for measuring the thermal properties of packaging materi-als are demonstrated. Chapter 6, Electrical Performance of IC Packages, discusses

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xviii Preface

the modeling techniques and test methods for predicting high-frequency IC package performance. Most IC package electrical characteristics are very dependent upon package design, as well as material properties, and can be defi ned only for the com-plete IC package confi guration. Chapter 7, Solderability of Integrated Circuits, covers the various lead fi nishes used on IC packages and the test methods for determining solderability and for analyzing solder defects. Chapter 8, Hermeticity and Joining in Ceramic IC Packages, reviews ceramic package sealing, methods for testing hermetic-ity, and residual gas analysis of the package cavity. Chapter 9, Advanced Interconnect Technology, deals with solutions to performance issues that often dictate replacing discrete IC device packages with the direct interconnection of die on multi-chip module (MCM) substrates. The properties of the materials used for interconnect substrates take on a new level of importance when these materials must also perform the function of IC package.

The completion of this volume would not have been possible without the encour-agement and support of the Materials Science Laboratories (MSL), which are a part of the Central Research Laboratories of Texas Instruments, Inc., in Dallas. The editors especially recognize the support of Dr. Thomas J. Shaffner, Acting Director of MSL, and Dr. Don W. Shaw, Director of MSL and Founding Director of the Texas Instru-ments Tsukuba Research and Development Center in Tsukuba, Japan. Throughout the completion of this volume we have enjoyed the patience and professionalism of Lee E. Fitzpatrick, the managing editor at Manning Publications. Many of the fi g-ures were created by Brett Geddes and Larry Norton, two of the computer graphics specialists in the Graphics Services group of the TI Central Research Laboratories. We greatly appreciate the contributions from our technical readers: William Sonia of Annam, Mike Lampson and Gail Heinen of Texas Instruments, and Michael Chan and Joe Stoddard of Compaq Computer Corporation. We also appreciate the expert support in library research of Marcia Schemper-Carlock of Texas Instruments.

Thomas M. MooreRobert G. McKenna

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xix

Contributors

John Adams Four Pi Systems San Diego, CA

X-Ray Laminography

Mostafa Aghazedeh Intel Corporation Chandler, AZ

Thermal Management

Eric Bogatin Sun Microsystems Computer Corporation Mountain View, CA

Electrical Performance of IC Packages

Joseph Colangelo Texas Instruments Dallas, TX

X-Ray Radiographic Inspection

Darvin R. Edwards Texas Instruments Dallas, TX

Mechanical Stress in IC Packages; Finite Element Analysis (FEA); In Situ Strain Gauges

Steven K. Groothuis Texas Instruments Dallas, TX

Mechanical Stress in IC Packages; Finite Element Analysis (FEA); In Situ Strain Gauges

James A. Kargol Compaq Computer Corporation Houston, TX

Solderability of Integrated Circuits

Shawn J. Kelsall Texas Instruments Houston, TX

Moisture Sensitivity and Delamination

Samuel S. Kim Rohm and Haas Company Research Laboratories Spring House, PA

Mold Compound Adhesion and Strength; Differential Scanning Calorimetry (DSC); Torsional Braid Analysis (TBA)

Kuan-Shaur Lei Compaq Computer Corporation Houston, TX

Coulometric Method for Solderability Evaluation

Stephen R. Martin Texas Instruments Midland, TX

Hermeticity and Joining in Ceramic IC Packages

Timothy M. McGuiggan Compaq Computer Corporation Houston, TX

Solderability of Integrated Circuits; Ceramic Plate Test (CPT) for Evaluating Solderability of IC Devices; Wetting Balance Method to Evaluate the Solderability of IC Devices

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xx Contributors

Robert G. McKenna McKenna and Associates Houston, TX

Moisture Sensitivity and Delamination; Advanced Interconnect Technologies

Herbert J. Moltzan Texas Instruments Dallas, TX

Dynamic Mechanical Analysis; Thermogravimetric Analysis (TGA); Thermomechanical Analysis (TMA)

Thomas M. Moore Texas Instruments Dallas, TX

Moisture Sensitivity and Delamination; Advanced Interconnect Technologies; Acoustic Microscopy (C-AM)

Anthony M. Petrucci Compaq Computer Corporation Houston, TX

Solderability of Integrated Circuits

Tom Talasek Texas Instruments Dallas, TX

Ion Chromatography

Lawrence C. Wagner Texas Instruments Dallas, TX

IC Package Reliability Testing; Decapsulation Techniques; Mechanical Testing in IC Packaging

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1

1

IC Package Reliability Testing

lawrence c. wagner

Contents

1.1 Introduction1.2 In-Process Quality Measurements1.3 Package-Oriented Reliability Testing of Finished Devices:

Moisture Testing1.4 Package-Oriented Reliability Testing of Finished Devices:

Thermal Cycle Testing1.5 Reliability Test Preconditioning: A New Direction1.6 Summary

1.1 Introduction

A critical factor in the rapid development of the electronics industry has been the dramatic increase in the quality and reliability of semiconductor products. Although much of the focus for this improvement has been on the wafer fabrication processes, these improvements could not have had such a dramatic impact on the electronics industry without corresponding improvements in packaging quality and reliability.

The reliability of integrated circuit (IC) packaging has historically been evalu-ated using in-process tests such as process measurement or process control tools as well as a series of accelerated stress tests on the fi nished IC packages. In-process testing is used to measure the mechanical strength of the critical interfaces cre-ated during the assembly process. These include the interface between the bond wire and die metallization and the interface between the bond wire and the lead frame or header. Additionally, the interfaces between the mold compound and die and between the mold compound and lead frame are signifi cant for plastic pack-age reliability, whereas lid seal and die attach interfaces are important for hermetic

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2 IC PACKAGE RELIABILITY TESTING Chapter 1

packages. Failure mechanisms such as bond failure, corrosion, and shear stress dam-age can arise from defects or delaminations at these interfaces in the IC package. The strength and quality of interfaces formed during the assembly process are typically the most critical elements of package reliability.

Reliability testing is performed on completed packages to assess their ability to survive thermal and moisture-related stresses encountered during actual use con-ditions. In order for a long device lifetime and for tests to be performed during a realistic elapsed time, these reliability tests are accelerated through the use of stresses signifi cantly in excess of those actually encountered during use conditions. Tempera-ture and moisture levels well outside the ranges normally encountered by a device are used to stress the device package. Device lifetime under these extreme conditions can then be used to estimate device lifetime for typical use conditions.

As the electronics industry migrates to surface mount devices, preconditioning of devices prior to reliability testing has become an issue. The board assembly processes for surface mount devices (infrared (IR) and vapor phase reflow (VPR)) put a thermal stress on devices which can have a significant impact on device lifetime. This stress is much greater than that associated with typical through-hole assembly processes (wave solder). Both the ultimate package temperature and the rate of heating are increased in the surface mount techniques. In order for reliability testing to estimate device lifetime more accurately, a simulation of the printed circuit board (PCB) assembly process is performed. In this way, device lifetime predictions can more accurately reflect the time-zero condition of the device in the field. In addition to the expected impact of preconditioning on moisture-accelerated and temperature-accelerated stress results, preconditioning may impact the high-temperature oper-ating lifetime of the device. Delamination at package interfaces during precondi-tioning or board level assembly can reduce the effectiveness of thermal dissipation paths, resulting in higher junction temperatures and shorter device lifetime.

1.2 In-Process Quality Measurements

In-process testing during the packaging or assembly process occurs at many steps. The most signifi cant in-process tests are performed on a sample basis to assess the mechanical strength of the interfaces formed during the various package assembly operations. The quality of these interfaces will, to a great extent, indicate the reli-ability of the fi nal product. These tests are performed to assess both the quality and the consistency of the assembly process being evaluated. In the past, these tests were used only as tools to evaluate proposed process changes and as process monitors. Corrections were made to the process only when the process failed test criteria. These sample measurement techniques are now used as process-control tools to reduce vari-ability in the assembly process. These tests include bond pull, bond shear, die shear, stud pull, and die attach voiding inspections.


1.2 IN-PROCESS QUALITY MEASUREMENTS 3

Wire Bond Quality

Regardless of the type of assembly process used, electrical interconnections between the die and the lead frame or header are critical to the reliability of the packaged IC. Wire bonding remains the predominant interconnection method. In most plastic packages, Au wire ball and stitch bonding are used. In hermetic packages, Al wire wedge bonding is commonly used. Other forms of interconnections such as tape automated bonding (TAB) and solder bump are also used in some applications.

Historically, wire bonding has been evaluated with wire-pulling techniques (refer to Technique Summary 18 in the Appendix). As with many of the other tests described, the specifi cations for this test are derived from the military standards (MIL-STD-883 Method 2011.7). A miniature hook is positioned under the wire and pulled up until a failure occurs. In the case of Al wedge wire bonding, the normal break site is either at the heel of the fi rst bond formed or at mid-wire. The heel of the fi rst bond formed is normally weaker than that of the second bond since the fi rst bond is mechanically stressed as the bonding tool pulls up from the bond and the tool is moved to the loca-tion of the second bond. In the case of Au wire ball bond, the failure should occur in the wire span between the ball and stitch bonds. Failures occurring at other locations may indicate a bonding problem. Hence location of the break as well as the force required for break are important in the evaluation process. This is particularly the case for Au wire bonding, where a ball lift during bond pull would indicate a serious reliability risk for a plastic IC. Screening of all of the units in a lot (100% screening) is possible with nondestructive bond pull testing in which a low preset upward force is applied to the wire (MIL-STD-883 Method 2023.4). All bonds must remain intact for a device to pass.

Since the ball bond (normally placed on the die) is in an area of very high stress concentration in plastic ICs, it is desirable to establish a better measure of its resis-tance to mechanical stresses. Bond shear testing has been established to fi ll this bond evaluation void1 (refer to Technique Summary 18 in the Appendix). A tool is located against the side of a ball bond and force is applied until the bond is dislodged. The desired result is shearing within the gold of the ball (Figure 1.1). Because interme-tallic formation continues during the assembly, temperature exposure equivalent to that encountered during assembly should be applied to bonds to assess fi nal bond strength. This shear test gives a better indication of the reliability of an Au ball bond in a plastic IC since the bond pull approach is limited by the maximum value of the wire strength, which is not adequate to assure a reliable bond. Actual values for bond pull strength depend heavily on bond wire diameter and the selected mechanical properties of the wire. For a 1 mil (25 μm) diameter Au wire, a value of 6–10 g might be anticipated with slightly lower values than anticipated for a comparable Al wire. Ball shear strengths depend heavily on the area bonded and hence the ball diameter. Values in the range of 60–120 g might be typically observed on good 1 mil (25 μm) diameter Au wire bonding with typical ball diameters of 2.5–4 mils (63–102 μm).



These mechanical bond tests can expose a number of failure mechanisms which can be latent reliability problems. Such failures can largely be categorized as non-sticking bonds or mechanical failures associated with the bond process or with inter-metallic formation. These failure mechanisms are accelerated by thermal stress testing and are discussed in more detail in Section 1.4.

Evaluation of alternative bonding approaches such as TAB is typically performed by mechanical tests similar to bond pull or bond shear. In the cases of solder ball and TAB bonding, the mechanical strength of the individual bond is typically very high, and the strength of an individual bond can be more diffi cult to evaluate (refer to Chapter 9). Tools such as C-mode acoustic microscopy (C-AM) or X-ray radi-ography may be employed to better evaluate bond uniformity (refer to Technique Summaries 1 and 28 in the Appendix). These bond techniques may also raise other reliability concerns which may require evaluation. For example, in TAB bonding, damage in the dielectrics surrounding the “bump” and under the “bump” on the die and extraneous plating from the bump process are concerns.2

Die Attach Quality

Attaching the die to the lead frame or header can be accomplished with one of sev-eral materials. The die attach performs several critical functions for the device. In addition to fi xing the location of the die mechanically, the die attach provides a critical thermal path for power dissipation. Nonuniform die attach can also enhance packaging stresses, negatively impacting device reliability. In some devices, the die attach may also provide an electrical connection to the device substrate. In the case of hermetic packages and some plastic packages, Au–Si eutectic die attach is employed although both Ag-fi lled and insulating glass die attaches may also be

Figure 1.1 Optical micrographs of the results of bond shear testing showing (left) shear predominantly within Au and (right) sheer within intermetallics. Shearing with-in the Au is desirable.



used for hermetic packages. Au–Si eutectic die attach provides excellent electrical and thermal conductivity. The eutectic die attach is formed by scrubbing the die into the Au plating of a heated header. The melting process can be assisted through the use of a thin Au or Au alloy preform slightly smaller than the die. The low melting point of Au–Si eutectic (363 °C) allows processing at temperatures consistent with other package materials (see Figure 1.2). For small die in hermetic packages, eutectic die attach is the predominant method for die attach except where an insulating die attach is required. For large die, it becomes diffi cult to control the uniform formation of the eutectic die attach. Voids and nonuniform thickness can result in severe mechanical stress and, ultimately, die cracking. Hence Ag-fi lled glass die attaches have become the die attach of choice for very large die.

The primary method of die attach in the plastic IC is the Ag-fi lled polymer (typi-cally epoxy or polyimide). Eutectic die attaches are also used. However, the cost of eutectic die attach is higher. Solder die attaches may be used where improved con-duction or thermal dissipation is required.

In most cases, four in-process techniques can be used to evaluate die attach qual-ity: die shear testing, stud pull, X-ray radiography, and C-AM (refer to Technique Summary 18 in the Appendix). The fi rst two techniques are employed to assess the gross mechanical strength of the die attach. The latter two are used to assess the uni-formity and effective area of adhesion of the die attach.

Die shear is a tool commonly used to determine the shear strength of the die attach (MIL-STD-883 Method 2019.5). A tool is applied to the side of the die and force is applied until the die shears from the header or lead frame. The force re-quired to separate the die from the header or lead frame as well as the nature of the

Figure 1.2 Au–Si binary phase diagram.



fracture determine the strength of the die attach. Normally, the preferred fracture is within the Si. Typically, the force required for shear of a 10 Kmil2 (6.45 mm2) die would be on the order of 30 kg. In other words, the test assures that the die attach is more resistant to the imposed shear stress than the die itself, thus setting a lower limit on the die attach strength.

The forces required to shear larger die exceed the capability of die shear testers, resulting in development of the die stud approach (MIL-STD-883 Method 2027.2). A stud is attached to the top of the die with quick-set adhesive and pulled vertically. The force required for stud pull on a 100 Kmil2 (64.5 mm2) die would be on the order of 50 lb (roughly 23 kg). Both of the above techniques provide a gross test of the mechanical strength of the die attach. However, die attach uniformity and cover-age can be more critical to IC reliability than mechanical strength. Nonuniformity can result in high stress gradients that in turn can result in die fracture.

X-ray radiography is effective in the characterization of the uniformity of die attach even though the die attach itself is quite thin. This is the case because the common die attach materials contain elements of relatively high atomic number. The Au content of eutectic die attaches and Ag fi llers in epoxy and glass attaches are examples. Even insulating glass die attaches typically have a high Pb content, which makes X-ray radiography easily applicable as shown in Figure 1.3. Hence the pres-ence or absence of the die attach material can be readily determined. Although X-ray radiography is effective in detecting voids or nonuniformities in the die attach, it is not particularly useful in assessing the adhesion resulting from the die attach process. The use of X-ray radiography can also be limited in the inspection of die attach in thick packages composed of materials with high atomic number.

The detection of cracking and delamination in the die attach is most read-ily accomplished by C-AM. The C-AM can also be used to detect voids in the die

Figure 1.3 X-ray radiography of different die attach materials: (left) voided nonconduct-ing glass attach in hermetic package and (right) Ag-filled polymer die attach in plastic package



attach and hence possesses a broader range of application than X-ray radiography (Figure 1.4). Acoustic microscopy is, however, somewhat more time-consuming. X-ray radiography inspection systems that operate in real time are available. A C-AM, however, can take several minutes to scan a single device. (Some timesavings are achieved in loading and inspecting larger groups of devices in both approaches.) Additionally, C-AM is not limited by high-density materials, as is X-ray radi-ography. Figure 1.5 shows the acoustic image of the die attach of a cavity-down pin grid array (PGA) with a large heat sink. The use of X-ray radiography would

Figure 1.4 Acoustic microscope images of Au–Si eutectic die attach showing (left ) 20% and (right ) 45% good die attach by area. Dark areas are well bonded, whereas light areas are unbonded.

Figure 1.5 Acoustic microscope image of die attach in cavity-down pin grid array with a large heat sink. Bonded areas appear dark due to par-tial acoustic transmission. Nonbonded areas appear bright (upper left) due to total acoustic reflection



be impractical in this inspection due to the material density, but C-AM provided detailed information about the die attach except at the heat sink. A comparison of X-ray radiography and C-AM for die attach evaluation is given in Table 1.1. This indicates that X-ray radiography is a valuable general evaluation tool particularly useful for wire dress issues (e.g., wires swept by mold compound injection) and that C-AM provides a better tool for die attach evaluation.

Defects and nonuniformity in the die attach can result in cracking of the die or die attach and degraded power dissipation (refer to Chapter 3). Failures of this type are usually associated with the large differences in coeffi cients of thermal expansion (CTE) of the materials in the package and are accelerated by thermal cycling.

Other Process Control Measurements

Other in-process tests are employed depending on the type of package used. Lead bend, symbolization permanency, and solderability (refer to Chapter 7) are typical of the tests applicable to all types of packages. Other tests are specifi c to package types. For hermetic packages, mechanical tests such as lid torque test for cer-dip packages (ceramic package with ceramic lid and the leads imbedded in the seal-ing glass between the lid and package body), centrifuge, and vibration testing are employed. These mechanical tests provide excellent gross assessments of the process quality. However, they generally suffer from the limitation that they are not as sensi-tive to point defects as to failures related to gross mechanical strength. For example, lid torque would readily detect a failure of the seal glass to wet the lid but would not likely detect a small crack which could propagate later. Other hermetic pack-age tests such as particle impact noise detection (PIND) and leak tests are oriented towards detecting point defects. PIND testing detects loose particles inside the cavity of a package by vibrating the package on an acoustic detector capable of picking up sounds from the impact of the particle on the inside surfaces of the package.

A wide variety of physical and analytical techniques are required in the analysis of failures from these in-process tests. Analysis of solderability failures, for example,

X-ray Acoustic Microscopy

Detection of voids Requires proper contrast;M ay not be possible in

high-density packages

Easily detected

Detection of dewet Poor Easily detected

Detection of cracks/delamination Typically not possible Easily detected

Time per device Minutes 10 min

Table 1.1 A comparison of the X-ray and C-mode acoustic microscopy for die attach evaluation.



involves the detection of contamination on the surface that prevents solder wetting. Auger electron spectroscopy (AES) analysis is more appropriate for thin-fi lm con-tamination, whereas energy dispersive X-ray spectroscopy (EDS) may be used for thicker contamination (refer to Technique Summaries 3 and 11 in the Appendix). Analysis of PIND rejects relies on a variety of particle capture techniques and EDS analysis of the particles.3 EDS analysis provides a “fi ngerprint” of the source of the particle (Figure 1.6).

IC manufacturers’ testing of incoming material such as lead frames, headers, bond wire, and mold compounds is generally being reduced. More emphasis is being placed on vendor process control of their outgoing material. The focus of testing for each type of incoming material is different, requiring a broad range of analytical tech-niques. Header and lead frame tests are largely oriented toward items such as plating thickness, plating adhesion, surface cleanliness, and dimensional analysis.

Bond wire analysis focuses on mechanical properties and chemical purity. Histori-cally, atomic absorption (AA) has been used for the analysis of impurities in bond wire, but inductively coupled plasma (ICP) is the current method of choice (refer to Technique Summaries 2, 14, and 15 in the Appendix). ICP provides a higher temperature, reducing molecular formation. This reduces matrix effects. With ICP-optical emission spectroscopy (ICP-OES), simultaneous measurement of multiple wavelengths is possible for rapid multielement analysis.4 The primary concern is metallic impurities. Determination of levels of metals include those intentionally added to the wire to control hardness, tensile strength, or other mechanical proper-ties. For example, metals such as Be, Cu, Tl, or Pd may be added to Au bond wire. Si and Mg are typical Al bond wire additives.

Mold compound tests5 are extremely diverse and focus on, for example, ther-momechanical properties, composition, stability, purity, and fl ammability (refer to

Figure 1.6 SEM micrographs of particles from hermetic packages: (left ) Au–Si eutectic die attach particle shorting bond wires and (right ) Au–Sn lid seal PIND reject particle captured on tape.



Chapter 3). Thermomechanical analysis (TMA) is used to measure the CTEs and glass transition temperature of the cured mold compound (refer to Technique Sum-mary 23 in the Appendix). The CTEs are a critical factor in the thermal cycling reliability of the plastic IC package. Another important element of the mechanical properties is elastic modulus data, which can be acquired using a dynamic mechani-cal analyzer (DMA) (refer to Technique Summary 8 in the Appendix). The elastic modulus of the mold compound, for example, impacts the shear stress exerted on the die surface during thermal cycling. Several characteristics of the composition of the mold compound are measured. The resin material is commonly evaluated by Fou-rier transform infrared spectroscopy (FTIR) (refer to Technique Summary 13 in the Appendix). Filler material content, typically Si oxide or Al oxide, can be measured by ashing the mold compound in a muffl e furnace and weighing. Br, an element present in fl ame retardants, can be measured by combustion, water extraction of the resultant bromide, and titration. The presence of Sb, another component in fl ame retardants, is commonly determined by ICP. Metallic ionic contamination will also be determined by ICP. Soluble anionic contamination is measured by boiling water extraction of a sample of cured mold compound followed by ion chromatography (refer to Technique Summary 17 in the Appendix). Halide and alkali metal ions are of primary concern for device reliability. Halide ions can contribute to corro-sion, whereas alkali metal ions can result in electrical inversion failure mechanisms. Thermogravimetric techniques can be used to assess the stability and outgassing of the mold compound (refer to Technique Summary 22 in the Appendix). Flam-mability is determined based on cured sample sticks. The sample sticks are ignited with a laboratory burner fl ame and the results are evaluated per UL 94V-0 or IEC Standard 695-2-2.

Polymer die attach materials will be tested by many of the same techniques. Some added items of interest are bulk resistivity of a cured sample and rheology. Since elec-trical contact is provided through the back of the die in some cases, bulk resistivity is an issue for die attach material. Rheology is also critical to control of the application of die material.

1.3 Package-Oriented Reliability Testing of Finished Devices: Moisture Testing

Accelerated stress testing of ICs generally targets specifi c failure mechanisms or groups of failure mechanisms. Several of these tests are oriented towards detecting package-related failure mechanisms. Thermal and moisture stresses are primary con-cerns for plastic IC packages. Moisture testing is directed largely at corrosion of the die metallization or delaminations of the thin fi lm layers on the die. Corrosion occurs due to ionic contamination and moisture attack on Al metallization on the die. Delamination between thin fi lm layers typically occurs due to dissolution of thin fi lm SiO2 dielectrics which contain P oxide. In addition to failures in the die, moisture-induced delamination of the mold compound from the die surface can


1.3 PACKAGE-ORIENTED RELIABILITY TESTING: MOISTURE TESTING 11

result in increased shear stress on the ball bonds and bond separation. Such mold compound delamination is an important factor in metallization corrosion because it allows the accumulation of moisture.

Moisture resistance testing for hermetic packages is not as typical since the die is protected from moisture by the package. Hermetic packages are, however, susceptible to moisture degradation, which manifests itself largely as low-level electrical leakages on the surface of the package.

Moisture-related stresses are performed in both biased and unbiased forms on plastic ICs. The prevalent unbiased humidity resistance test is autoclave, which is typically defi ned as exposure to saturated moisture at 121 °C (2 atm water vapor). Biased tests are run under a variety of conditions, normally specifi ed in terms of the temperature and relative humidity. Hence the most common test, 85 °C/85% RH, is a reliability test run at 85 °C and 85% relative humidity. The bias voltage is normally set at a fi xed level. However, conditions must be selected which minimize power dissipation since heating could drive moisture from the die surface, invalidating the test. Since this test is typically run to 1000 h or more, the need for a shorter duration has led to the increased use of highly accelerated stress testing (HAST). Tests at 120 °C/85% RH and 130 °C/85% RH are most commonly employed in HAST.6 Bias conditions are similar to those employed for 85 °C/85% RH testing. Even more highly accelerated stresses tend to induce failure mechanisms which do not occur at normal operating conditions.

Failure Analysis of Moisture-Related Failures

The end result of moisture attack on ICs is relatively straightforward to identify. Simple wet chemical decapsulation (refer to Technique Summary 6 in the Appendix) and optical microscopy are adequate to observe the results. As the moisture resistance of plastic ICs and mold compound purity have improved, it has become more criti-cal to understand the underlying factors associated with corrosion. A more detailed understanding of the root causes of corrosion is required.

Moisture-induced delamination failure mechanisms (Figure 1.7) most often occur due to dissolution of P-doped oxide at high water vapor pressure. Typical contribu-tors to delamination include higher-than-normal P levels and mechanical defects in moisture barrier layers, particularly SiN layers. Failure analysis efforts focus largely on evaluation of these factors. The level of P in SiO2 is commonly measured by EDS or wavelength dispersive X-ray analysis (WDX) (refer to Technique Sum-mary 10 in the Appendix). Some deconvolution of the P and Si peaks is required if EDS is employed. WDX is easily capable of resolving the Si and P peaks. These techniques are ideal for homogeneous, relatively thick P-doped oxide such as inter-level oxides. However, for oxides whose thickness is less than the sampling depth of the X-ray technique, only a relative level of P can be determined. If accurate concentrations and concentration profi les are required, secondary ion mass spec-trometry (SIMS) is the method of choice (refer to Technique Summaries 9 and 21 in the Appendix). Passivation defect levels are commonly evaluated by exposure of



the die to acid followed by optical microscope inspection for areas where the under-lying metallization has been etched through passivation defects (MIL-STD-883 2021.3).

One problem commonly observed on moisture test failures is contamination of the outside of the package in the moisture chamber. This contamination can arise on the outside of a package being tested or another package in the same chamber. Verifi cation of external package leakage is usually performed by mechanical removal of material between device pins and electrical retesting.

Root Causes of Corrosion Failures

The analysis of failures from corrosion requires special analysis techniques since identifi cation of root causes depends on identifi cation of the ionic contamination source and the migration path of the ionic contamination.7 One of the key fac-tors required for corrosion of IC metallization is ionic contamination. In fact, this is probably the limiting factor for corrosion during moisture resistance tests since the plastic package becomes saturated with moisture in a relatively short time. As contamination levels from wafer fabrication processing have diminished, corrosion has become largely a package-related issue. Improved mold compound adhesion to the die and lead frame, reduced stresses applied at the lead forming operation, and lower levels of external package contamination from sources such as solder fl ux have become key issues in preventing metallization corrosion. These precautions help to eliminate contamination sources and reduce paths for ionic migration from the out-side of the package. The most common ionic contaminant which results in cor-rosion of aluminum metallization is the chloride ion. Although identifi cation of the presence of chloride ions can be straightforward (Figure 1.8), identifi cation of

Figure 1.7 Typical example of delamination of the die by attack of the P-doped SiO2: (left ) SEM and (right ) optical micrograph.


1.3 PACKAGE-ORIENTED RELIABILITY TESTING: MOISTURE TESTING 13

the sources of ionic contamination is extremely diffi cult. The chloride ion can fre-quently be identifi ed by EDS analysis.8 More important are minor contaminants which identify, or “fi ngerprint,” the source of the contamination. For example, the Zn ion is frequently a “fi ngerprint” of activated solder fl uxes. AES provides a second method of analysis. Although AES is lacking in bulk sensitivity, analysis of corrosion products on the surface of die can provide added clues to the source of the ionic contamination. When a likely source of the contaminants is the exterior of the pack-age, boiling water extraction of a sample group of packages can provide insight into package cleanliness. Ion chromatography of the extract provides an excellent method to identify excessive ionic contamination from the IC assembly or board assembly operation (refer to Technique Summary 17 in the Appendix).

Figure 1.8 (a) Corrosion of bad pad areas due to chloride ion contamina-tion identified by (b) EDS analysis. (c ) Delamination of the mold compound from the corner of the die and lead frame identified by acoustic microscopy contributed to the autoclave failure. The black areas are delaminated.



One additional problem in identifying sources of contamination is that wet chem-ical decapsulation procedures typically remove corrosion products essential to the failure analysis process. Thermomechanical techniques have been devised to break open the IC package without removing these corrosion products (refer to Technique Summary 6 in the Appendix).

In addition to identifi cation of the source of ionic contamination, identifi cation of the migration path is also important. C-AM, supported by X-ray radiography and metallurgical cross sectioning, usually provides an insight into the migration paths which occur due to package delamination.9, 10 Additionally, chemical analy-sis of surfaces along the suspected migration paths is helpful. Thus, analysis of lead frame segments from a thermomechanically decapsulated device may assist in identifying the migration path of contamination. These thermomechanical decap-sulation techniques are extremely varied. They generally include one or more of three elements: some reduction of package size by grinding, heating the mold com-pound, and the exertion of a mechanical force to crack the package or separate materials.

1.4 Package-Oriented Reliability Testing of Finished Devices: Thermal Cycle Testing

Thermal cycling is intended predominantly to accelerate those failure mechanisms associated with the differences in CTEs in an IC package. Thermal stresses may be in the form of temperature cycling or thermal shock testing. These tests differ pri-marily in the time of transition between extreme temperatures. The basic procedures are defi ned in MIL-STD-883 Methods 1010.7 and 1011.9. Thermal shock testing provides the more rapid transition between extremes. The length of the transition time is determined primarily by the ambient environment. Temperature cycling is performed between hot air and cold air environments; thermal shock is performed between hot and cold liquids. Typically, the devices to be stressed are loaded into a basket which is transferred between high- and low-temperature media. Typical high temperatures range between 125 and 155 °C, and low temperatures range between –55 and 0 °C.

For hermetic packages, stresses are imposed on the bonding system and die attach of the package by temperature cycling. Typical failure mechanisms are die cracking or lifting (Figure 1.9) due to nonuniform or inadequate die attach or bond problems. For plastic ICs, accelerated thermal stress testing targets fail-ure mechanisms which result from mechanical stresses. These mechanical stresses result from the differences in CTEs of the different materials in the IC (refer to Chapter 3). The minimum stress temperature from a CTE perspective is normally established at some elevated processing temperature, such as the temperature at which a mold compound is cured. Hence the low-temperature portion of the ther-mal stress is normally the more critical. Failures typically occur at the ball bond or


1.4 PACKAGE-ORIENTED RELIABILITY TESTING: THERMAL CYCLE TESTING 15

surface of the die. Many factors can contribute to ball bond failures. One factor outside of the bonding process is the adhesion of the mold compound to the die surface. If delamination occurs, the shear stress force resulting from CTE mismatches is focused on the ball bond, resulting in shearing of the ball bond. The relatively low level of stitch bond fractures which occur can usually be traced to some delamination of the mold compound from the lead tip. Finite element modeling of the devices can be used both to identify high mechanical stress areas or to evaluate stresses in areas prone to thermal cycling failures (refer to Chapter 3). In general, failure anal-ysis of thermal stress failures involves straightforward wet chemical decapsulation and optical microscope or scanning electron microscope (SEM) inspection (refer to Technique Summary 19 in the Appendix). Metallurgical cross sections are frequently used to better defi ne the microscopic observations. Failure due to thermal stress and particularly shear stress on the die surface is discussed in detail in Chapter 4.

Figure 1.9 Optical micrographs of (upper) cracked die and (lower) delami-nated die attach after the die was mechanically removed.



Bond Failures: Bond Pad Contamination

Failures which occur at in-process bond tests, after thermal stressing, or in use are analyzed in much the same fashion. Nonsticking bond problems can occur with either Au or Al wire bonding. When a bond lift occurs due to a lack of metallurgi-cal interaction of bond wire with the bond pad, it is necessary to determine the root cause of the failure. This can be related either to the bonder parameters or to contamination of the bond pad. The use of proper bonding parameters can normally be assessed through SEM evaluation of the bond shape, as discussed in the next sec-tion. Once the bonder parameters can be eliminated as a root cause of failure, the most critical factor in reliable bond formation is the cleanliness of the bonded areas. Of primary concern is the cleanliness of the bond pad. When bond lifting occurs, analysis of the bonding area can be performed in several ways.

AES is typically the fi rst choice for analysis of potentially contaminated bond pads or bond pads from which bonds have lifted.11 Two contaminants can typically occur on bond pads from the wafer fabrication process: unremoved passivation or polymers, which form during the plasma etching of bond pad openings in the pas-sivation. AES is ideally suited for such a case since the contaminant fi lms are typically very thin, hence an analysis technique which samples only the surface is required (AES typically samples the top 2–5 nm).

In addition, AES can easily be performed with sputtering to indicate the depth dis-tribution of any contaminants on the bond pads. This is important since adsorbed gases typically form a signifi cant part of the material detected on the initial surface of bond pad by surface analysis techniques (Figure 1.10). Thus the AES spectrum acquired after sputtering away this adsorbed material is the most signifi cant for determining bond cleanliness. Since most bonding processes include a scrubbing motion, they are capable of bonding through some thickness of contaminant. Hence any evaluation of bond pad cleanliness should include an estimate of the contaminant thickness.

AES is also well-suited for identifying residual passivation. Residues of SiN or SiO2 are readily detected and identifi ed. Also, excessive oxidation of the Al surface can be well-identifi ed due to the good sensitivity of AES to light elements such as O, and due to the differences in the energies of Al peaks for metal and oxide in the AES spectrum. In the case of polymer formation during the passivation etch, AES will identify F and C.

The primary limitation in the use of AES for bonds is that, in the case of organic contamination, no chemical bonding detail occurs. A second limitation is that AES is time-consuming and therefore is not usually performed on-line. Several on-line alternative approaches have been explored, including micro-hardness testing, fl uo-rescence, and optical refl ectivity. Micro-hardness testing has potential for bond pad evaluation since indentation will be affected by a thin surface fi lm. In general, sur-face fi lms reduce the indentation in the metallization, causing the metallization to appear to be harder. Since many organic materials and SiN fl uoresce with UV irra-diation, fl uorescence has potential for contamination detection. Although surface



roughness is the primary factor affecting bond pad optical refl ectivity, the refl ectivity of the bond may also be altered by thin-fi lm contamination of the bond pad.

When an organic material is indicated, AES is limited in that it gives only elemental composition. Microspot FTIR allows the identifi cation of the precise compound inhibiting bonding. When organic materials other than polymers from

Figure 1.10 Typical (upper) Auger spectrum and (lower) depth profile of bond pad. The bond pad surface shows adsorbed gases and some polymer contamination from the wafer fabrication area.



the passivation etch occur, a matching or “fi ngerprinting” process is required to identify the source of the contaminant. Suspect materials must also be analyzed by Microspot FTIR to determine the root cause of the bonding problem. In some cases, it may be necessary to differentiate various components of a likely contamination source. For example, Figure 1.11 shows contamination on a bond pad which matched the plasticizer in a wafer storage bag. In order for the match to be confi rmed, the plasticizer must be separated from the remaining elements of the plastic bag. In this case, a matching spectrum was obtained by collecting the outgassing material from a heated plastic bag in a gas chromatograph.

Reliable wire bonding to the lead frame or header can also be a problem if clean-liness of the incoming material is not adequate. For examination of small areas of nonsticking, the microanalysis techniques used on bond pads—AES and microspot FTIR—are also applicable. In addition, liquid extraction techniques may also be employed where extensive contamination is suspected. Examination oriented towards inorganic contamination would typically employ a boiling water extraction followed by ion chromatography. Organic contaminants would be evaluated by extractions with both polar and nonpolar solvents, followed by FTIR spectroscopy of the extract. Since some extractable material is likely to be present, comparison with “good” material is essential in evaluating the results of such an analysis. A summary of the advantages and disadvantages of the primary analytical techniques discussed above is presented in Table 1.2.

Intermetallic Formation and Other Elements of Bond Formation

Mechanical failures of bonding can occur due to variations in the bonding param-eters. The most critical factors include bond temperature, downward bond force,

Figure 1.11 Microspot FTIR spectrum of bond pad contamination identified as plasticizer.



and ultrasonic or scrubbing parameters. Mechanical bond evaluation typically con-sists of evaluation of bond shape, although specifi c problems may require alternative approaches. For example, one approach to detecting latent cracking of the dielectric under the bond pad is described below.

Mechanical failures for aluminum wire bonding typically result in fractures at the bond heel. Bond fracture occurs primarily due to the bonding parameters employed, although the mechanical properties of the wire can also play a role. The primary technique for the evaluation of bond fracture is SEM inspection of unpulled bonds (Figure 1.12). The high depth of focus makes SEM an ideal technique for bond evaluation. The high resolution of the SEM can also be useful for obtaining more detailed physical information. Similarly, the bond shape of ball and stitch bonds can be best evaluated in the SEM.

Technique Advantages Disadvantages

EDS Quick, easy interpretation;Moderate sensitivity (0.1%);Imaging

Elemental data only

AES Ideal for very thin fi lms;Good spatial resolution;Sputtering for depth profi les;Imaging

Elemental data only;Low sensitivity, especially for

high atomic number;Qualitative results

FTIR Precise indentifi cation of organic contaminants;

Microspot gives adequate spatial resolution for semiconductor problems

Poor for inorganics;Can be time-consuming for very

thin fi lms;Non-imaging

Table 1.2 Advantages and disadvantages of the three most commonly used analytical techniques for IC package problems.

Figure 1.12 SEM micrographs of typical Al wedge bonds, showing (left) minor cracking at the heel and (right ) mechanical tool damage.



Latent mechanical damage to the dielectric under the bond pad metallization poses a unique reliability threat that is diffi cult to detect by standard bond evaluation techniques. The most effective method for detecting this damage, commonly referred to as “chip-out” (Figure 1.13), is chemical removal of the bond pad metallization with aqua regia, for example, and subsequent optical inspection. A slightly more time-consuming method is the use of the IR microscope in a similar manner to the technique described later in this section.

When dissimilar materials are used in the bond wire and bonded area, the chem-ical interaction of the materials can also be a signifi cant factor in the bond reli-ability. The interaction of gold with Al is particularly of concern since a number of intermetallic compounds are formed at the interface. This is in contrast to the simple welding which occurs in the bonding of an Al bond wire to an Al bond pad or solid state solution which occurs at a Au bond to Ag plating. The interac-tion of Au and Al results in a complex set of fi ve intermetallic compounds. The compounds AuAl2, AuAl, Au2Al, Au5Al2, and Au4Al are formed. The phase dia-gram for the Al–Au binary system is shown in Figure 1.14 for reference. Initially, Au5Al2 is formed. The Al-rich compounds will be formed where Al remains. How-ever, the Al under the ball bond will ultimately be totally consumed except at the bond periphery because Au is in excess and the thermodynamic equilibrium will favor the Au-rich phases. Since the Au4Al phase has a slow growth rate, Au5Al2 will normally predominate. The chemical kinetics involved in these reactions are deter-mined by the rates of interdiffusion of Au and Al. Formation of the intermetallic phases is an important aspect of the bonding process. The intermetallics formed have a higher shear strength than the Al or Au. However, since the rate of diffu-sion of Au in Al is not equal to the rate of diffusion of Al in Au, void formation and ultimately void accumulation can result in separation between phases (typically between the Au5Al2 and Au4Al phases). The time-to-failure is based on temperature

Figure 1.13 Bond pad chip-out failures after temperature cycling shown by (left) SEM and (right) optical micrographs. This type of defect initiated as a small crack in the dielectric at bonding.



exposure and the diffusion kinetics. Voids are not normally observed without long-term high-temperature exposure of the bond. A signifi cant rate of diffusion occurs in the range of 175–200 °C in hermetic packages and in a somewhat lower range in plastic packages.12

Temperature is one of the most critical bonding parameters for proper intermetallic formation. Ideally, intermetallic formation is only initiated during the bond process, and further intermetallic reaction then occurs during subsequent thermal exposure in the assembly process. For this reason, bond pull and bond shear tests should be run after bonding and after a thermal exposure equivalent to the remainder of the assembly process. Equivalent temperature exposure is preferred to decapsulation of the plastic IC and subsequent bond evaluation. The chemical decapsulation process can impose an unintended stress on the ball bond and result in misleading bond pull or shear results. If bond pull or bond shear must be performed after decapsulation, it is imperative that the tests be run as soon as possible after decapsulation, since traces of decapsulating acid left on the device will degrade the bond results. One added problem with decapsulation for bond pull is chemical attack of the lead frame, which can occur if the stitch bonds are exposed. Thus, it is recommended that the stitch bonds not be exposed unless there is a specifi c concern about the stitch bonds.

In addition to ball shear, further information about Au ball bond quality can be obtained through metallographic cross sections and IR microscope evaluation. As

Figure 1.14 Au–Al binary phase diagram.



indicated above, for a well-formed ball bond, shear will occur within the Au. If, however, the area of intermetallic formation is smaller relative to the area of bond, the ball may shear at the intermetallics and the bond shear strength will provide a measure of the area of intermetallic formation. Another method for determining the area of intermetallic formation is IR microscope inspection from the backside.13 In this approach, the back of the package is ground and lightly polished to expose the Si die. Since Si is IR-transparent, the bottom of the bond pads can be inspected. The area of intermetallic formation is dark relative to the Al bond (Figure 1.15). Obvi-ously, this approach will be successful only for devices with single-level metallization and without a barrier or adhesion layer. As suggested above, one problem with the Al–Au system is that excessive exposure to temperature/time will result in void for-mation and bond lift. Although both of the above techniques provide a good insight into intermetallic formation area, they provide no insight regarding the potential problem of excessive intermetallic formation. Metallurgical cross sections best pro-vide this information (Figure 1.16). Sections such as that illustrated in Figure 1.16 best show the extent of intermetallic formation. In the past, excessive intermetallic and void formation has been referred to as “purple plague” (a reference to the purple color of AuAl2 which is not directly tied to the actual failure mechanism). Excessive intermetallics and voiding are now commonly seen only on devices which have been overheated. For example, devices with high operating temperatures and exposed to a high temperature operating life test (HTOL) can exhibit this failure mechanism due to the temperature/time exposure. The physical analysis tools discussed above are summarized in Table 1.3.

Figure 1.15 IR microscope images of bond pad bottoms as viewed through the Si: (left) in-complete intermetallic formation and (right ) uniform intermetallic formation.


1.5 RELIABILITY TEST PRECONDITIONING: A NEW DIRECTION 23

1.5 Reliability Test Preconditioning: A New Direction

Preconditioning to simulate board level assembly has become a major issue for package-related reliability issues. Emphasis on preconditioning has arisen largely because of issues associated with surface mount package assembly. Surface mount devices are the primary concern because of the soldering techniques employed to attach these devices to circuit boards. IR refl ow and VPR are the primary soldering techniques employed. Both techniques result in a very rapid increase in tempera-ture of both the device leads and the package. The heating of the package body is a signifi cant departure from the wave solder techniques typically used for through-hole devices. In wave soldering, the heating is predominantly applied to the device leads with minimum heating of the body of the package. Additionally, the ultimate temperature achieved is well above 200 °C in surface mount techniques.

Figure 1.16 SEM micrographs of cross sections of ball bonds with (a and c ) various levels of excessive intermetallic formation and views of (b) the ball bond bottom and (d ) the bond pad after ball bond lifting due to excessive intermetallic formation.



These differences have resulted in unique package-related failure mechanisms such as the “popcorn” effect. The rapid expansion of moisture trapped in a surface mount device results in package delamination. The evolved steam pushes the mold compound away from the lead frame, forming a bulge which ultimately cracks. The phenomenon is similar to popping corn in several ways: the processes both involve the rapid thermal evolution of trapped moisture, both result in bulging of the pack-age or kernel, and both result in similar audible pops (refer to Chapter 4).

The special interest in preconditioning prior to reliability testing can be briefl y summarized. The reliability testing of through-hole devices without precondition-ing reasonably refl ects the fi eld reliability because the impact of wave solder tech-niques on the through-hole packages is minimal. However, an accurate assessment of the reliability of surface mount devices in the fi eld must refl ect the deleteri-ous effects of IR refl ow or VPR on the plastic package. Preconditioning is expected to include the introduction of moisture into the package followed by one or more cycles of exposure to refl ow soldering conditions. Moisture is introduced into the package because the vaporization and rapid expansion of water vapor is a known source of damage to surface mount packages. Also, the mold compound will adsorb some level of moisture dependent on the relative humidity of storage. After some level of moisture absorption, several solder cycles are performed in order to simulate

Technique Advantages Disadvantages

Optical microscope

Easy to useGood resolutionEasily interpreted

Limited depth of fi eld

IR microscope Silicon IR transparent Moderate resolution

SEM High resolutionLarge depth of fi eldEnergy dispersive analysis is

attachment

Surface topography only: no transparency in bulk materials

X-ray radiography

Good spatial resolutionQuick, easy interpretation

Limited to observation of anom-alies with signifi cant changes in mass density

Acoustic microscope

Will detect any defect which results in air gap: ideal for cracks, delaminations, and voids

Spatial resolution moderate but well-suited to packages

Moderate time to operateCorrelation to metallographic

cross sections may be required to establish accurate interpretation

Metallography Provides detailed section of anomalies

Time-consumingLimited to single plane

Table 1.3 A comparison of the physical analysis tools used in package inspection.


1.6 SUMMARY 25

the board level assembly process. For two-sided boards, at least two exposures to sol-dering will be required. The possibility of rework on the circuit boards may dictate an additional solder cycle.

1.6 Summary

The reliability of the IC package has been signifi cantly improved during the last decade. Predictors of fi eld reliability include in-process testing and accelerated stress testing of completed devices. Many of the determining factors for device reliability are related to the adhesion between the various interfaces in the IC package. For this reason, most of the analytical tools required to analyze package-related failures are surface-oriented approaches such as AES, EDS, and microspot FTIR. Although AES and EDS may lack the sensitivity sometimes desired, they provide the small spot size frequently required for microanalysis and simultaneous imaging of the surface. Microspot FTIR provides an excellent complementary technique for analysis of organic contaminants. A range of physical analysis tools is also employed in analysis of IC packages. These include opti-cal, IR, and SEM. C-AM, X-ray radiography, and metallography provide the tools for physical probing inside the package.

References

1 M. Shell-De Guzman and M. Mahaney. 30th International Reliability Physics Sym. 1992, p. 251.

2 R. Milburn and K. Rackley. “New Technology in Electronic Packaging,” ASM International. 11, 1990.

3 C. M. Vicroy, J. H. Linn, and R. W. Belcher. International Sym. for Testing and Failure Analysis. 1990, p. 149.

4 T. A. Anderson and K. L. Evans. International Sym. for Testing and Failure Analysis. 1986, p. 17.

5 H. Moltzan and G. Bednarz. Texas Instruments Technical Journal. 177, Sept./Oct. 1988.

6 D. Danielson, G. Marcyk, E. Babb, and S. Kudva. 27th International Reliability Physics Sym. 1989, p. 114.

7 L. C. Wagner, S. Boddicker, P. D. Ngo, D. H. Morgan, and T. Myers. “New Technology in Electronic Packaging,” ASM International. 1990, p. 353.

8 S. M. Kudva and E. Knudson. International Sym. for Testing and Failure Analysis. 1986, p. 1.

9 T. M. Moore, R. McKenna, and S. Kelsall. 29th International Reliability Physics Sym. 1991, p. 160.

10 L. Wagner. ASM Metals Congress. Doc. No. 8305-002, ASM International, Metals Park, OH, 1983.



11 R. K. Lowry and J. H. Linn. Semiconductor International. 174, May 1991.

12 A. A. Gallo. 28th International Reliability Physics Sym. 1990, p. 244.

13 M. K. Shell and S. Golwalkar. 29th International Reliability Physics Sym. 1991, p. 152.


characterization of integrated circuit packaging materials

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