Charge-Balanced SiC FETs for

Breakthrough Power Conversion

Presented at SWITCHES Annual Meeting, Philadelphia, PA

P. Losee, A. Bolotnikov, R. Ghandi, D. Lilienfeld, S. Kennerly, R. Datta, R. Chokhawala, T. P. Chow, G. Pandey, J. Sun

General Electric Global Research, Niskayuna, NY

March 28, 2017

The information, data, or work presented herein was funded in part by the Advanced Research Projects

Agency-Energy (ARPA-E), U.S. Department of Energy, under Award Number DE-AR0000674. The

views and opinions of authors expressed herein do not necessarily state or reflect those of the United

States Government or any agency thereof.

SiC Device Options Scaling to Medium Voltage……

1

RDrift ~ BV2.4

Conventional Unipolar Devices:

Large conduction losses limit them to low current

densities….. ~20A/cm2

Vknee 3V and VF > 4V

Conventional Bipolar Devices:

Wide bandgap and resulting knee voltage gives

large conduction losses that limit them to low

current densities….. ~20A/cm2

Exploiting SiC HV benefits requires high-

frequency applications….

What SiC device offers the best performance at

LF and HF in MV space?

Project Objectives

2

Overall goals of the project:

- Demonstrate HV (4.5 kV) SiC Charge-Balanced FETs that break the conventional

1D ROn,sp vs. BV limit with scalable process

- Enable highly efficient Medium-Voltage, Multi-MW power conversion with SiC

devices that offer low conduction losses, low switching losses and simple

topologies

- Enhance US technological leadership and manufacturing of SiC devices and

resultant power conversion systems

Team’s approach:

- Use SiC process and design expertise, to demonstrate prototype SiC CB devices

- Utilize novel multi-level process with mixed implantations and novel junction

termination

- Leverage epitaxial layers with doping and thickness ranges in common with most

volume SiC needs (600 V - 1.7 kV class); can be offered by many vendors globally

Project Objectives

3

Challenges/risks:

-Activation and control of implanted dopants

-Quality of epitaxial regrown layers and ability to support high E-field

-High Energy Implant masking to fabricate deep/fine doped regions

-Impact of residual damage from High Energy Implants: leakage, activation, blocking

Key performance metrics :

-Design specifications for scalable CB devices with ROn,sp < 1-D BVPP Limit

-Process Flow for CB devices

Key outcomes:

-Demo world’s first 3 kV SiC CB diode with ROn,sp < 7 mOhm-cm2

-Demo world’s first 4.5kV SiC CB FET with ROn,sp < 12 mOhm-cm2

-Define design constraints & performance targets for scalable CB devices to ~15 kV

Helpful additional team resources:

More (domestic) SiC Epitaxy Regrowth / HE Implantation vendors/partners

Project Team

4

~20 years SiC design& fabrication experience, benchmark

SiC MOSFETs, HV SiC diodes, HV SiC Thyristors, TVS

>20 years power device design and

characterization, and modeling

GE Global Research (GE GR)

Device Characterization and

Model Development

Dr. J. Sun

Dr. T. P. Chow

Device Design, Process Development

Prototype Fabrication, Wafer Test

Dr. P. Losee (PI), Dr. A. Bolotnikov, Dr. R. Ghandi,

Dr. D. Lilienfeld, S. Kennerly

GE GR SiC Commercialization

Technology-to-Market

Dr. R. Datta, Technology Leader, SiC

GE Energy Connections

GE Transportation

U.S. based SiC foundry

service suppliers

Device Design, Simulation

5

Design & Modeling: Impact of SiC CB on 3.3kV+ Diodes & MOSFETs

1st Year

Accomplishments

3.3kV Diode Simulated

Forward characteristics

• Rdiff (25oC) = 3.2mOhm-cm2

• Rdiff (175oC) = 8.4mOhm-cm2

Consider HV standard modules:

3.3kV / 400A Dual-Switch

Si diode Vf @ 150oC, 400A = 2.25V (@ 100A/cm2)

Is there a case to be made for SiC

CB devices as low as 3.3kV?

To match Vf of Si diode with:3.3kV SiC SBD @ 150oC, 6.15cm2 Area required

N = 7 (1cm die) or 30 (0.5cm die)

3.3kV SiC-CB SBD @ 150oC, 2.6cm2 Area required

N = 3 (1cm die) or 13 (0.5cm die)

1.4x - 2x Module Current Possible!

Process Development

6

Epitaxial Overgrowth Challenges - Alignment

1st Year

Accomplishments

Measured Misalignment through

Epi Overgrowth process

Alignment strategy through 10um SiC epitaxial overgrowth demonstrated with l < 0.4um

II-Flat -Flat

Objective: Assess the quality of High-Energy Implanted P/N Junctions &

optimize process conditions

PiN diodes w/ HEI Anodes used to assess leakage current under High E-field required in SiC CB Devices

E-field under

HV bias (2.4kV)

JTE

P

PiN Diodes with HEI

P+

N- drift

Cathode

Anode

High Energy Implant PiN Diodes1st Year

Accomplishments

Leakage C

urr

ent

Density (A

/cm

2)

Al_HEI

B HEI

8

Reverse Biased P/N Junctions formed with HEI (Die Size=0.1cm2):

Al High Energy Implanted PiN Diode

BV=2400

B High Energy Implanted PiN Diode

BV=2540

Leakage Density @ 200oC and 80% BV Al: 10-100uA/cm2

B: 1-10uA/cm2

Sharp, Stable Avalanche

High Energy Implant PiN Diodes1st Year

Accomplishments

9

Y2: Demo Prototype CB Devices 2nd Year Goals

‣ Circuit Model of Simulated 3kV SiC CB JBS diode

available for feedback from applications team and user

community

‣ Demonstrate world’s first 3 kV SiC CB JBS diode with

ROn,sp < 7 mOhm-cm2

‣ Design and Process Flow for 4.5kV SiC CB MOSFET

defined, prototype fabrication begins

‣ SiC CB Device Cost Model

Technology-to-Market

‣ The commercial objectives of this project will be to manufacture in a

foundry and license this technology to partners

‣ The target market segments for SiC Charge-Balanced devices are

industrial and transportation power conversion markets

‣ Suitable applications where SiC CB FETs will differentiate are expected

to be MV drives, MV UPS, MV PV, MV Wind and Traction converters

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Technology-to-Market

Technology-to-Market

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Technology-to-

Market

‣ Key potential customers include GE Energy Connections, GE

Transportation, GE Healthcare, GE Grid Solutions

‣ The key supply chain challenges are the High-Energy Implants and

Epitaxial Overgrowth processes. The epitaxial growth process should

ultimately be co-located at foundry for high throughput, US based High-

Energy implant vendors should be established by the end of this

program. Infrastructure exists but will need configuration….

Wind converter:> 50% lower losses

Electric loco: 5% lower weight

MRI: better image quality, free-up equipment room

Oil and gas: New capability in hot & harsh conditions

Ship electric power distribution: 10x lower transformer weight

MV drive: >25% smaller footprint

Conclusions

‣ SiC CB devices offer disruptive performance benefits for >3.3kV+

‣ Offering conduction loss advantage over Si bipolar in MV, impact of HV

SiC Power Conversion applications can be realized even at low

switching frequency

‣ Offers lowest chip-size per Amp compared to all SiC options for 3.3kV-

10kV applications -> Higher Rated Modules

‣ Critical process building blocks for fabricating SiC CB devices have been

established in Year 1 including:

– HEI, Epitaxial Overgrowth, Alignment & Masking..

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