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CHARGE PUMP NMOS LDO USING SPLIT-TRANSISTOR

COMPENSATION

BY

Z M Saifullah, B.Sc

A dissertation submitted to the Graduate School

in partial fulfillment of the requirements

for the degree

Master of Sciences, Engineering

Specialization in: Electrical Engineering

New Mexico State University

Las Cruces, New Mexico

March 2015

“CHARGE PUMP NMOS LDO USING SPLIT-TRANSISTOR COMPENSA-

TION,” a dissertation prepared by Z M Saifullah in partial fulfillment of the

requirements for the degree, Master of Sciences has been approved and accepted

by the following:

Dr. Loui ReyesDean of the Graduate School

Chair of the Examining Committee

Date

Committee in charge:

Dr. Paul M. Furth, Associate Professor, Chair.

Dr. Wei Tang, Assistant Professor.

Dr. Abbas Ghassemi, Professor.

ii

DEDICATION

Dedicated to my mother Tahmin Ara Begum, father Md. Liakat Ali, wife

Kamrun Nahar, daughter Jemima Saifullah, sister Nusrat Zunaid and her family,

And my grand parents

iii

ACKNOWLEDGMENTS

I would like to thank my parents Tahmin Ara Begum and Md. Liakat

Ali for their support and their decision to let me have my Master’s in USA. My

wife Kamrun Nahar who supported me in my endeavor. Without her love and

encouragement, i could not have completed my degree. My daughter Jemima

Saifullah who gave me new meanings of life. And my sister Nusrat Zunaid, her

husband Muhammed Zunaid, their children Navid Zunaid and Nuzhat Zunaid who

encouraged me to complete my Master’s in USA.

I would like to thank Dr. Paul M. Furth for advising me throughout my

Master’s degree. I learned a great deal from his teaching through courses like

digital VLSI and Integrated Power Management; learned how to do research and

research philosophy through his research. His kind and supportive behaviour

encouraged me to do a competitive research. I thank his wife, Carol and family

with whom we spent time on Thanksgiving day every year. They made me feel

like home when i am thousands miles away from it.

Great appreciation and thanks to Dr. Wei Tang and Dr. Abbas Ghassemi

for accepting my request to be member of my thesis committee , managing time

from their busy schedule.

I would also like to thank Dr. Jaime Ramirez for developing my analog

VLSI concept.

iv

I would like to thank my friends, Muhammed Junayet Hossain, Md. Atiqul

Haque, Md. Adnan Sarker, Alejandro Romn Loera, Sri Harsh Pakala, Bala Ke-

sava, Yeshwanth Puppala, Venkat Harish Nammi, Anurag Veerabathini. They

inspired and helped me whenever needed.

v

VITA

April 7, 1984 Born in Bangladesh.

Education

2002- 2006 B.Sc. in Electrical and Electronic Engineering,Khulna University of Engineering and Technology, Bangladesh

2012 - 2015 MSEE. in Electrical Engineering,New Mexico State University, USA - GPA 3.88/4.0

Experience

Teaching Assistant, Electrical Engineering, NMSU, Fall-2013, Spring 2014

vi

ABSTRACT

CHARGE PUMP NMOS LDO USING SPLIT-TRANSISTOR

COMPENSATION

BY

Z M Saifullah, B.Sc

Master of Sciences, Engineering

Specialization in Electrical Engineering

New Mexico State University

Las Cruces, New Mexico, 2015

Dr. Paul M. Furth, Chair

Two NMOS Low-Dropout Voltage Regulators (LDO) are designed in IBM

180 nm CMOS process for an output of 1.2 VDC with load current that can vary

from 3 µA to 100 mA. Dropout voltages for the LDOs are 177 mV and 82 mV at

maximum load current. There is no resistors divider in the designs as the output

voltage and reference voltage is the same. A charge pump circuit is implemented

in the IC to increase the gate voltage of the NMOS pass transistor so that the

dropout is low. Charge pump is so designed that when there is no reference

voltage, the charge pump will not work, making the LDOs more efficient. A two-

phase non-overlapping clock generator is used to avoid the charge sharing of the

capacitors in the charge pump. A clock input is required in the clock generator to

vii

have non-overlapping two-phase outputs. Split-length transistor with varied width

is implemented in these designs. Both circuits have low quiescent current of 3.5 µA

without charge pump and non-overlapping clock generator. With charge pump

and non-overlapping clock generator circuits the quiescent current still below 4 µA.

LDOs are also tested for line transisent, load transient, PSR and ripple. Ripple

is caused by the input clock to the clock generator. When there is no clock, the

ripple goes away. All tests are performed in hardware and simulation, and results

are compared with each other.

viii

TABLE OF CONTENTS

LIST OF TABLES xiii

LIST OF FIGURES xv

1 INTRODUCTION 1

1.1 Power Management of Cell Phone Architecture . . . . . . . . . . . 1

1.2 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.3 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.4 Unique Contributions . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.5 Organization of This Thesis . . . . . . . . . . . . . . . . . . . . . 3

2 LITERATURE REVIEW 5

2.1 Basics of LDOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2 Conventional Design of PMOS LDO . . . . . . . . . . . . . . . . . 6

2.3 Conventional Design of NMOS LDO . . . . . . . . . . . . . . . . 8

2.4 Performance Parameters of LDOs . . . . . . . . . . . . . . . . . . 10

2.4.1 Dropout Voltage . . . . . . . . . . . . . . . . . . . . . . . 10

2.4.2 Line Transient and Line Regulation . . . . . . . . . . . . . 11

2.4.3 Load Transient and Load Regulation . . . . . . . . . . . . 12

2.4.4 Power Supply Rejection . . . . . . . . . . . . . . . . . . . 13

2.4.5 Recovery Time . . . . . . . . . . . . . . . . . . . . . . . . 14

ix

2.4.6 Gain Margin and Phase Margin . . . . . . . . . . . . . . . 15

2.5 Compensation Techniques . . . . . . . . . . . . . . . . . . . . . . 16

2.5.1 Miller Compensation . . . . . . . . . . . . . . . . . . . . . 17

2.5.2 Nested Miller Compensation . . . . . . . . . . . . . . . . . 18

2.5.3 Reverse-Nested Miller Compensation with Nulling Resistor 20

2.6 Split-Length Transistors . . . . . . . . . . . . . . . . . . . . . . . 21

2.7 Split-Length Compensation . . . . . . . . . . . . . . . . . . . . . 22

2.8 Non-Overlapping Clock Generator Circuit . . . . . . . . . . . . . 24

3 DESIGN AND SIMULATIONS 27

3.1 Proposed Low-Dropout Voltage Regulators . . . . . . . . . . . . . 27

3.2 Proposed LDO Regulator Architecture and Design . . . . . . . . . 28

3.3 Small Signal Analysis . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.3.1 First Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.3.2 Second Stage . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.3.3 Gain in Level Shifter . . . . . . . . . . . . . . . . . . . . . 34

3.3.4 Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.3.5 Charge Pump Operation . . . . . . . . . . . . . . . . . . . 36

3.3.6 Non-overlapping Clock Genarator Design . . . . . . . . . . 38

3.3.7 Poles and Zeros . . . . . . . . . . . . . . . . . . . . . . . . 40

3.4 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.4.1 AC Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.4.2 Dropout Voltage Measurement . . . . . . . . . . . . . . . . 43

3.4.3 Line Transient . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.4.4 Load Transient . . . . . . . . . . . . . . . . . . . . . . . . 51

3.4.5 Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

x

3.4.6 Power Supply Rejection . . . . . . . . . . . . . . . . . . . 56

4 EXPERIMENTAL RESULTS 61

4.1 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

4.1.1 Passive Elements Layout . . . . . . . . . . . . . . . . . . . 61

4.1.2 Pass Element Layout . . . . . . . . . . . . . . . . . . . . . 62

4.1.3 Layout of Other Circuits . . . . . . . . . . . . . . . . . . . 63

4.2 Hardware Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

4.2.1 Dropout Voltage . . . . . . . . . . . . . . . . . . . . . . . 67

4.2.2 Ripple Measurement . . . . . . . . . . . . . . . . . . . . . 68

4.2.3 Line Transient Response . . . . . . . . . . . . . . . . . . . 69

4.2.4 Load Transient Response . . . . . . . . . . . . . . . . . . . 76

4.2.5 PSR Measurements . . . . . . . . . . . . . . . . . . . . . . 76

5 DISCUSSION AND CONCLUSION 81

5.1 Result Comparison : Simulated vs. Measured . . . . . . . . . . . 81

5.2 Comparison with Existing Designs . . . . . . . . . . . . . . . . . . 85

5.3 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

APPENDICES 91

A. Test Document 92

A.1 With PCB: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

A.1.1 Procedure to Measure Dropout Voltage VDO . . . . . . . . 93

A.1.2 Line Transient Test Procedure . . . . . . . . . . . . . . . . 94

A.1.3 Load Transient Test Procedure . . . . . . . . . . . . . . . 97

A.2 With Bread Board . . . . . . . . . . . . . . . . . . . . . . . . . . 97

xi

B. Maple 98

REFERENCES 100

xii

LIST OF TABLES

3.1 Device dimensions in µm for the LDO1 and LDO2. . . . . . . . . 29

3.2 Component’s values used in both LDOs. . . . . . . . . . . . . . . 29

3.3 Device dimensions in µm for Charge Pump. . . . . . . . . . . . . 38

3.4 Device dimensions in µm for Non-overlapping Clock Generator. . 40

3.5 AC analysis for LDO1 and LDO2 Regulator at IL,min = 3µA andIL,max = 100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.6 Simulated dropout voltage for LDO1 and LDO2 at maximum loadwith and without the charge pump and the capacitor CBATT . . . 46

3.7 Line transient simulation results for LDO1 and LDO2 regulators. 47

3.8 Load transient simulation results for LDO1 and LDO2 regulator. 52

4.1 Layout Area for LDO1 and LDO2 regulators and Components. . . 63

4.2 Experimental dropout voltage for LDO1 and LDO2 at maximumload. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

4.3 Line transient experimental results for proposed LDOs. . . . . . 71

4.4 Load transient experimental result for proposed LDOs. . . . . . . 77

5.1 Results Comparison for LDO1. . . . . . . . . . . . . . . . . . . . 83

5.2 Results Comparison for LDO2. . . . . . . . . . . . . . . . . . . . 84

5.3 Simulated dropout voltage for LDO1 and LDO2 at maximum load. 84

5.4 Comparison table with existing NMOS LDO. . . . . . . . . . . . . 88

5.5 Comparison table with existing PMOS LDO. . . . . . . . . . . . . 89

xiii

1 Dropout Voltage Measurement Table . . . . . . . . . . . . . . . . 95

xiv

LIST OF FIGURES

1.1 Block diagram of typical cell phone architecture [1]. . . . . . . . 2

2.1 Block diagram of low drop-out (LDO) regulator. . . . . . . . . . . 6

2.2 Block diagram of PMOS low drop-out (LDO) regulator. . . . . . . 7

2.3 Block diagram of NMOS low drop-out (LDO) regulator. . . . . . . 9

2.4 Typical Dropout Voltage Measuring Waveform. . . . . . . . . . . 10

2.5 Typical Line Transient Waveform. . . . . . . . . . . . . . . . . . . 11

2.6 Typical Load Transient Waveform. . . . . . . . . . . . . . . . . . 13

2.7 Waveforms showing typical PSR response [7] . . . . . . . . . . . 14

2.8 Waveforms describing recovery times in case of a line transient event 15

2.9 Illustration on measuring gain margin and phase margin [9] . . . 16

2.10 Two-stage miller compensated op-amp with nulling resistor . . . 17

2.11 Simplified AC characteristic for Miller Compensation without NullingResistor [12] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.12 Simplified AC characteristic for Miller Compensation with NullingResistor [12] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.13 Nested Miller compensation. . . . . . . . . . . . . . . . . . . . . . 20

2.14 Reverse-nested Miller compensation. . . . . . . . . . . . . . . . . 21

2.15 Illustration of split-length transistors. . . . . . . . . . . . . . . . . 22

2.16 Illustration of split-length compensation for NMOS. . . . . . . . . 23

2.17 Small signal model for split-length compensation for NMOS. . . . 23

xv

2.18 Schematic of a typical Non-overlapping clock generator [17]. . . . 25

2.19 Output waveforms phase 1 and phase 2 of the non-overlapping clockgenerator [17]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.1 Schematic for the proposed LDO. . . . . . . . . . . . . . . . . . . 28

3.2 Schematic of the Proposed LDO1 with Compensation Capacitor. . 30

3.3 Schematic of the Proposed LDO2 with Compensation Capacitor. . 31

3.4 Small-signal architecture of LDO1. . . . . . . . . . . . . . . . . . 32

3.5 Small-signal architecture of LDO2. . . . . . . . . . . . . . . . . . 33

3.6 Schematic of the designed Charge Pump. . . . . . . . . . . . . . . 38

3.7 Charge Pump operation. . . . . . . . . . . . . . . . . . . . . . . . 39

3.8 Schematic of the designed non-overlapping clock generator, whichuses 7 delay cells in each path. . . . . . . . . . . . . . . . . . . . . 41

3.9 Testbench for AC analysis. . . . . . . . . . . . . . . . . . . . . . . 43

3.10 LDO1 AC analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.11 LDO2 AC analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.12 Test bench for dropout voltage simulation. . . . . . . . . . . . . . 46

3.13 Test bench for line transient simulation. . . . . . . . . . . . . . . 48

3.14 Line Transient Response for LDO1. . . . . . . . . . . . . . . . . . 49


3.16 Testbench for load transient simulation. . . . . . . . . . . . . . . . 52

3.17 LDO1 load transient response. . . . . . . . . . . . . . . . . . . . . 53

3.18 LDO2 load transient response. . . . . . . . . . . . . . . . . . . . . 54

3.19 Test Bench for Ripple measurement. . . . . . . . . . . . . . . . . 55

3.20 Ripple measurement for LDO1 at Load Current = 1 mA. . . . . . 56

3.21 Ripple measurement for LDO2 at Load Current = 1 mA.. . . . . . 57

3.22 Test Bench for PSR measurement. . . . . . . . . . . . . . . . . . . 58

xvi

3.23 PSR waveform for LDO1. . . . . . . . . . . . . . . . . . . . . . . 59


4.1 Microscopic view of LDO1 (Die measure 1.5 mm x 1.5 mm). . . . 62

4.2 Layout of LDO1 (Dimension 275 µm x 437 µm). . . . . . . . . . . 64

4.3 Layout of LDO2 (Dimension 424 µm x 437 µm). . . . . . . . . . . 65

4.4 Layout of LDO1 with 40-pin pad frame (1.5 mm x 1.5 mm). . . . 66

4.5 Layout of 10 pF Capacitor. . . . . . . . . . . . . . . . . . . . . . . 67

4.6 Layout of 200 kΩ resistor. . . . . . . . . . . . . . . . . . . . . . . 68

4.7 Layout of NMOS Pass Element (Dimensions 44.65 µm x 127.97 µm). 69

4.8 LDO1 Dropout Voltage Measurement. . . . . . . . . . . . . . . . 70

4.9 LDO2 Dropout Voltage Measurement. . . . . . . . . . . . . . . . 71

4.10 Waveform for measuring Ripple for LDO1. . . . . . . . . . . . . . 72

4.11 Waveform for measuring Ripple for LDO2. . . . . . . . . . . . . . 73



4.14 Load Transient Response for LDO1. . . . . . . . . . . . . . . . . . 76

4.15 Load Transient Response for LDO2. . . . . . . . . . . . . . . . . . 77



5.1 Charge Pump operation. . . . . . . . . . . . . . . . . . . . . . . . 85

5.2 Measured and Simulated PSR values for LDO1. . . . . . . . . . . 86

5.3 Measured and Simulated PSR values for LDO2. . . . . . . . . . . 87

A.4 Jumper Configuration for Dropout measurement. . . . . . . . . . 93

xvii

Chapter 1

INTRODUCTION

This is the age of mobility, accessibility and dependability. We are always on the

run and want to gain immediate access to information that we need. And for this,

we are dependent on mobile devices such as the smart phones, tablets, laptops,

etc. All of these portable devices that we use in our day-to-day life can be made

functional only when we have power. And batteries are the only source of power

for these devices, hence a critical component.

1.1 Power Management of Cell Phone Architecture

Fig. 1.1 shows the block diagram of a typical cell phone architecture. The

major functional blocks are the power amplifier, RF section, analog base band and

digital base band units. One or more voltage regulators supply power to all of

those blocks. The supply voltage and current requirements of the different blocks,

which correspond to the output requirements of the regulators, depend on the

phone generation, the technology used and the system design of the phone [1].

Mobile devices impose power savings as much as possible to extend the

time between charging of the battery. This is where linear regulators come in

handy. A linear regulator is a system that can deliver a constant output voltage.

An LDO (Low Dropout Voltage Regulator) is one kind of linear regulator. It is

a device that can produce regulated (constant) output for different load currents.

The reason behind LDOs popularity is because it can produce a low-noise output,

consumes low power, and requires small area. Simplicity in design is an added

1

Figure 1.1: Block diagram of typical cell phone architecture [1].

advantage. Due to their low quiescent current and low noise contribution, LDOs

are preferred to use in some blocks of cellular and portable devices. They are very

suitable for powering the baseband, RF, TCXO, RTC, and audio sections of the

typical handset [2]. LDO’s can also be used to reduce the output ripple of other

converters. Hence LDOs are considered an integral part of power management

systems. Fig. 1.1 shows that LDOs are used to power up digital and analog base

band, display, flash, SRAM, VCOs and power amplifier.

1.2 Motivation

The wide usage and popularity of low drop-out regulators made us inter-

ested to work on them. The PMOS LDO is the most widely-used LDO. Because of

higher ripple cancellation property of NMOS along with higher mobility, we chose

to study the NMOS LDO. We assume NMOS LDO have higher power supply

rejection and require less area in comparison with PMOS LDO. Our goal was to

study an NMOS LDO and compare its performance parameters with other NMOS

and PMOS LDOs in literature.

2

1.3 Specifications

The goal is to generate a regulated output of 1.2 Volts for load currents

varying from 3 µA to 100 mA. The total quiescent current is meant to be less than

5 µA. The work will be done in a 0.18 µm IBM process. The load capacitance is

100 pF. Our goal is to achieve a maximum drop-out voltage of 100 mV. We also

want to keep the clock ripple as low as 0.5% of output voltage.

1.4 Unique Contributions

1. Designed and fabricated an NMOS LDO.

2. Used split-transistor compensation technique.

3. Designed a working charge pump to drive the NMOS pass transistor.

1.5 Organization of This Thesis

The report is organized in the following way. In Chapter 2, we discuss

the basics of both PMOS and NMOS LDOs. Chapter 2 includes the operation of

conventional LDOs. We define some important parameters and also discuss some

basics of compensation techniques.

In Chapter 3, design parameters, simulations and simulation results are

discussed along with the design procedure and criteria. We also include AC anal-

ysis of the designed LDOs in this chapter.

In Chapter 4, the layout is described. It also includes hardware measure-

ment results, PCB design and the test setup for testing different parameters.

Chapter 5 compares the simulated results and the measured results. We

find comments and conclusions regarding our work.

In the appendix, we have a detailed description of test procedures and the

layout of our PCB. The latter part of the appendix includes Maple work which is

used to estimate the poles and zeros of the LDOs. Matlab code to plot simulation

3

and experimental results is also included here. Last but not the least, we find the

list of references that are used to complete our work and can be very influential

for the future work.

4

Chapter 2

LITERATURE REVIEW

DC-DC converters transform one DC level to another DC level. The low dropout

voltage regulator is a type of DC-DC converter that is a buck converter. The LDO

is a linear voltage regulator and is usually used as a low-noise voltage source. In

this chapter, we will discuss the basics of LDOs and their operation. A few

compensation techniques will also be discussed in this chapter.

2.1 Basics of LDOs

An LDO consists of several working blocks including an error amplifier,

pass element and feedback network, as shown in Fig. 2.1. The pass element can

be either a PMOS or NMOS transistor and is usually very large in size so that

it can accommodate high output current. The pass element is a critical part of

the LDO. A PMOS pass element in an LDO is configured as a common-source

amplifier, whereas an NMOS pass element is configured as a source-follower. The

function of the feedback network is to provide a comparable negative feedback

value for the negative input terminal of the error amplifier. A voltage divider is

also a part of the feedback network. A voltage divider network is not necessary

for the LDO if the output voltage is equal to the reference voltage. The positive

input terminal of the error amplifier is always attached to a reference voltage. The

output voltage of the LDO can be expressed as a function of the reference voltage

5

using:

VOUT = VREF ·(

1 +R2

R1

)(2.1)

The function of the amplifier is to compare the two values. For a small

change in the output voltage, through the feedback network, this change appears

at the negative input terminal of the error amplifier. The small difference between

the two input terminals gets amplified by the error amplifier and controls the gate

terminal of the pass element to eventually stabilize the output voltage.

VREF

VBATT

Pass Element

R1

R2

Feedback

Network

Error_Amplifier

VOUT

CL

OA

D

Figure 2.1: Block diagram of low drop-out (LDO) regulator.

2.2 Conventional Design of PMOS LDO

Most of the commercially-available LDOs use PMOS pass elements. Fig. 2.2

shows the block diagram of a typical PMOS LDO. We find from the schematic

that the open loop gain of the LDO is the product of the gain of the error amplifier

and the gain of pass element which is in a common-source configuration. Note

6

that the input terminals are reversed because the PMOS pass element configured

as a common-source amplifier is inverting. The output voltage is fed back to the

positive input terminal of the error amplifier.

VREF

VBATT

MPPASS

R1

R2

Negative

Feedback

Error_Amplifier

VOUT

RL

OA

D

CL

OA

D

G

D

S

Figure 2.2: Block diagram of PMOS low drop-out (LDO) regulator.

Basically, a three-stage LDO forms at least a two-pole transfer function

[3]. One pole is the contribution of the load capacitor and pass element and is

usually the dominant one when there is a large off-chip capacitor. Another one is

from the output of the error amplifier driving the large pass element. In the case

of a two-pole system, we can express the transfer function as:

AOL(s) =AEA.APE

(s+ ωPA).(s+ ωPO)(2.2)

where

AOL(s) is the open-loop gain of the LDO

7

AEA is the gain of the error amplifier

APE is the gain of the pass element

ωPA is the pole at the output of the error amplifier

ωPO is the pole at the output of the pass element

Other poles and zeros may exist inside the error amplifier.

The conditions for a stable two-pole system are that the poles are far apart

and, moreover, the second pole is two or three times the Unity Gain Frequency

(UGF) of the LDO [3]. The UGF is determined by the capacitor that sets the

dominant pole along with the transconductance of the error amplifier that sets the

gain [4]. Noise that may occur in the LDO can primarily be removed by placing a

large capacitor at the output node. We need to design the system in such a way

that we have proper gain margin and phase margin, which will be discussed in

more detail later.

Because of electron mobility is generally two to three times higher than

hole mobility, the effective resistance of an NMOS pass element is two to three

times smaller than a PMOS pass element, which can be calculated using

reffective =1

(WL

)µCox(V gs− V t)(2.3)

So to get the same dropout performance, the NMOS LDO occupies less area

because of the smaller pass element size than a PMOS LDO. Hence for the same

dropout performance, the cost is lower for an NMOS LDO than for a PMOS LDO.

2.3 Conventional Design of NMOS LDO

LDOs not only provide the required voltages, they also provide the neces-

sary current to the circuit. When designing an NMOS LDO, we need to consider

8

that the gate voltage of the NMOS pass element needs to be higher than the

source voltage of the pass element so that it can accommodate high current. As

such, we need to boost the voltage of the system at the gate of the pass element.

In Fig. 2.3 we see a level shifter in series with the gate of the pass element. The

function of the level shifter is to increase the DC voltage that it receives from the

output of the error amplifier. The level shifter could be a battery or a capaci-

tor. If a capacitor is used, an additional high voltage supply or a charge pump is

required.

VREF

VBATT

Level Shifter

MNPASS

R1

R2

Negative

Feedback

Error_Amplifier

VOUT

RL

OA

D

CL

OA

D

G

S

D

Figure 2.3: Block diagram of NMOS low drop-out (LDO) regulator.

All other blocks are the same for both types of LDOs. The NMOS LDO

has an error amplifier which converts the difference between the feedback signal

and the reference signal to an output voltage that is applied to one terminal of

the level shifter. The level shifter then adds the additional DC voltage from an

9

outside source and applies the voltage to the gate of the pass transistor. The pass

transistor then controls the output based on the signal applied at the gate.

2.4 Performance Parameters of LDOs

The performance of an LDO can depend on the needs of the customers or

the circuit where it will be used. The most important parameters that we consider

during our design are discussed in this section.

2.4.1 Dropout Voltage

The dropout voltage VDO can be defined as the input-to-output differential

voltage where the circuit can no longer regulate its output voltage (VOUT ). In our

work, we adopted a more specific definition of the dropout voltage as the difference

between the input and output voltages when the output voltage is 5% below the

regulated output voltage VOUT,MAX . A typical figure that shows the process of

measuring dropout voltage is shown in Fig. 2.4 where rise and fall times are very

slow. Dropout voltage VDO is measured by the formula:

VDO = (VIN − VOUT ) |VOUT=VOUT,MAX−VOUT,MAX∗5% (2.4)

Time (s)

Volt

age

(V)

VIN

VOUTVDO=VIN-VOUT|VOUT,MAX-VOUT,MAX*5%

VOUT,MAX

VDOVOUT,MAX*5%

Figure 2.4: Typical Dropout Voltage Measuring Waveform.

10

2.4.2 Line Transient and Line Regulation

VIN

VOUT

trise tfall

Overshoot

Undershoot

VOUT,SS

VIN

VIN

VOUT

trise tfall

Overshoot

Undershoot

VOUT,SS

VIN

Figure 2.5: Typical Line Transient Waveform.

Fig. 2.5 shows a typical line transient response. The input signal has sharp

rise and fall times, trise and tfall, respectively. When the input signal rises, we

observe a fast rise in the output voltage, which eventually diminishes to a steady-

state value due to the controlling properties of the LDO. This fast rise in the

output is known as overshoot. Similarly, during the falling edge of the input

signal, there is an undershoot in the output waveform. In other words, the output

voltage tends to fall below the specified voltage. Line transient performance is

summarized by

∆VOUT,LINE = Overshoot + Undershoot + ∆VOUT,SS (2.5)

where ∆VOUT,SS is the the difference between the stable output voltages after an

overshoot and an undershoot.

Line regulation can be defined as the ability to maintain a steady-state

output voltage with variation in the supplied input voltage. Line regulation is

11

measured as the ratio of the steady-state change in VOUT (∆VOUT,SS) to the steady-

state change in VIN (∆VIN).

Line Regulation =∆VOUT,SS

∆VIN

(2.6)

Units for expressing line regulation are generally mV/V.

2.4.3 Load Transient and Load Regulation

Like line regulation, load regulation is also a measure of maintaining a

steady output, but this time the variation occurs in the load current. So, load

regulation can be defined as the ability to maintain a steady state output with

the variation in the load current. When there is a sharp rise in the load current,

the output voltage tends to go down, causing undershoot, and then climb back

near to the desired output. Similarly, when the load current goes from high to

low, we can observe a peak in the output voltage which eventually settles down to

the desired output. This peak is known as overshoot. And the voltage where the

output settles is known as the steady state output voltage. Fig. 2.6 shows a sample

output waveform for load transient measurement. Load transient is summarized

using

∆VOUT,LOAD = Overshoot + Undershoot + ∆VOUT,SS (2.7)

Load Regulation is measured as the ratio of the steady-state change in VOUT

(∆VOUT,SS) to the change in IL (∆IL).

Load Regulation =∆VOUT,SS

∆IL(2.8)

The units useful expressing load regulation are typically mV/mA.

12

VOUT

IL

Undershoot

OvershootVOUT,SS

IL

trisetfall

Figure 2.6: Typical Load Transient Waveform.

2.4.4 Power Supply Rejection

Power Supply Rejection (or ripple rejection) is a measure of the AC cou-

pling between the input supply voltage and the output voltage [5]. There are

contradictory statements regarding PSR relating to NMOS and PMOS LDOs. A

PMOS pass element generally has better PSR than an NMOS pass element ac-

cording to [5]. On the other hand, [6] states that an NMOS pass element has

better PSR over a PMOS pass element.

Supply voltage ripple affects analog and RF blocks. An LDO with good

PSR can overcome this problem. Ripple can be introduced into the system from

the reference generator voltage and the error amplifier at low frequencies. At high

frequencies, noise is introduced through the pass element. PSR depends mainly

on the loop gain. The higher the loop gain is, the higher the PSR is. That is

the reason that at low frequency, the LDO has better PSR than it does at high-

frequency. Fig. 2.7 shows a typical response of PSR measurement waveform for

an operational amplifier [7].

13

Figure 2.7: Waveforms showing typical PSR response [7]

2.4.5 Recovery Time

Recovery time is the time taken by the LDO to settle back within a specified

tolerance band of its steady-state output voltage VOUT,SS after an overshoot or

undershoot event [8]. In Fig. 2.8, tRH is the recovery time after an overshoot

event and tRL is defined as the recovery time after an undershoot event, where

the specified tolerance band is 1% of the output voltage. The average recovery

time tR is given by

tR ≡tRH + tRL

2(2.9)

.

14

Figure 2.8: Waveforms describing recovery times in case of a line transient event

2.4.6 Gain Margin and Phase Margin

Phase margin (PM) is defined as the difference between the phase and -

180o at the unity gain frequency. It is usually measured in degrees. The gain

margin (GM) is the amount of gain increase required to make the loop gain unity

at the frequency where the phase angle is -180o. The unit for GM is dB. Fig. 2.9

shows typical measurement techniques for gain margin and phase margin using

an AC analysis.

For a negative feedback network, if the feedback signal has the same mag-

nitude and phase as the input signal, the output signal will be unstable. To make

the system stable, we need to have a gain margin of at least 10 dB and a minimum

required phase margin of 45 degrees. Anything below these values is marginally

stable or unstable [10].

15

Figure 2.9: Illustration on measuring gain margin and phase margin [9]

The higher the phase margin is, the more stable the system is. At a phase

margin of 45 degrees, the output will have some ringing. A phase margin of 60

degrees usually does not show any ringing, hence the recovery time is quicker.

A system with 90 degrees phase margin is more stable, but the recovery time

increases. A 60 degrees phase margin is considered the optimum value.

2.5 Compensation Techniques

The more stages in an amplifier, the more complex its compensation net-

work becomes in order to maintain a stable system. Compensation techniques

depend on the number and types of stages used in the amplifier. Several compen-

sation techniques are discussed in this section.

16

2.5.1 Miller Compensation

-GM1VIN VOUT-GM2

CC RC

ROUTCOUT

V1

R1C1

Figure 2.10: Two-stage miller compensated op-amp with nulling resistor

The Fig. 2.10 shows a two-stage amplifier with Miller compensation. This

is probably the most widely used compensation technique [11]. Capacitor CC

is the compensation capacitor, and resistor RC is the called the nulling resistor.

Miller compensation can also be used without the nulling resistor. Basically, Miller

compensation is a series capacitor and resistance from the output of the second

stage to the output node of the previous stage. At high frequencies it creates

a feed forward path, which may be undesireable. In the figure, GM1 and GM2

are the transconductance of stage one and stage two, respectively. The Miller

capacitance causes the dominant pole at the output of the first stage to move to

a lower frequency. The dominant pole equation is:

ωP1 =1

AV 2 ·R1 · CC

(2.10)

17

And for the non-dominant pole at the output node, it moves towards high

frequencies. The second pole equation is:

ωP2 =GM2 · CC

CC · CL + CC · C1 + C1 · CL

(2.11)

Capacitor CC also creates a right hand zero, which can be expressed with-

out the nulling resistance as:

ωZ =GM2

CC

(2.12)

With the nulling resistance in, the poles remain the same, only the zero

moves from the right half plane to the left half plane as followe:

ωZ1 =1

CC · ( 1RC− gm2)

(2.13)

With a properly chosen value of RC , we can shift the zero to any suitable

position. In fact, the value of ωZ1 can help improve the performance of the

amplifier. Figs. 2.11 and 2.12 show the AC characteristics of an amplifier before

and after adding Miller compensation.

2.5.2 Nested Miller Compensation

Fig. 2.13 shows a graphical depiction of the nested Miller compensation

technique, which is an extension of Miller compensation which we use for multi-

stage amplifier, and only the Miller compensation is not good enough to stabilize

the circuit. Here we can see a capacitor, CC1 is connected from the final output

node to the first stage output node and also another capacitor CC2 is connected

from the same final output node to the output node of the second stage. Most

18

Figure 2.11: Simplified AC characteristic for Miller Compensation without NullingResistor [12]

Figure 2.12: Simplified AC characteristic for Miller Compensation with NullingResistor [12]

interestingly, both capacitors, CC1 and CC2, are generally connected through a

single resistor, RC .

So, can we just connect the output of one stage to the output of another

stage? The answer is NO. We need to keep in mind that the feedback must always

be negative. Now, if we look at the final stage, it is an inverting stage; hence the

feedback through CC2 is negative [13]. Since the second stage is non-inverting but

final stage is inverting, the feedback through CC1 is again negative [13]. Nested

Miller Compensation does not affect the overall gain of the amplifier, but rather

helps to improve the stability by creating two left half plane zeros.

For the configuration shown, the dominant left half pole equation is:

19

+GM2-GM1VIN VOUT-GM3

CC1

CC2

RC

R2C2

ROUTCOUT

V1 V2

R1C1

Figure 2.13: Nested Miller compensation.

ωP1 =1

AV 2 · Aout ·R1 · CC1

(2.14)

where, AV 2 = R2 ·GM2, and Aout = ROut ·GM3, and the dominant left half plane

zero equation is:

ωZ1 =1

−CC2

gM3+RC2 · CC2 +RC1 · CC1

(2.15)

2.5.3 Reverse-Nested Miller Compensation with Nulling Resistor

In Fig. 2.13, nested Miller compensation was possible because the middle

stage was non-inverting and the final stage was inverting. Now, consider a three-

stage amplifier with the stages as non-inverting, inverting and non-inverting, re-

spectively, for stages one to three. How can we compensate this amplifier? Nested

Miller will definitely not work here because of the positive feedback from the fi-

20

-GM1VIN VOUT-GM2 +GM3

CC1

CC2

RC

R2C2 RO

UT

COUT

V1 V2

R1C1

Figure 2.14: Reverse-nested Miller compensation.

nal stage to the output of the second stage. Reverse nested Miller compensation

was introduced to avoid this problem. Here, a capacitor CC1 is connected from

the output stage to the output of stage one and capacitor CC2 is connected from

the output of second stage to the output of the firstl stage. Like nested Miller

compensation, this compensation can also have a common resistor RC known as

a nulling resistor, as shown in Fig. 2.14. Both capacitors have negative feedback

paths. With the proper value of the compensation components, we can generate

two left half plane zeros which can help to create a stable system [14, 15].

2.6 Split-Length Transistors

The Figure 2.15 shows an illustration of split length transistors for both

NMOS and PMOS transistors. This technique was first introduced by Saxena [16].

Though this is not a widely used technique yet, we have designed an LDO keeping

the split length compensation technique in mind. In Fig. 2.15(a) we can see an

NMOS transistor M1 of dimension WL

is split into two series transistors, M1A and

M1B of size WL1

and WL2

respectively, where L = L1 +L2. The intermediate node X

is a low impedance node. The drain of the bottom transistor is connected to the

21

source of the top transistor while both gates are tied with each other. Now, while

in operation, the top transistor always operates in saturation and the bottom

one operates in triode. Similarly for the PMOS, the configuration is shown in

Fig. 2.15(b). The only significant difference is now the bottom transistor M2A is

in saturation and the top one, M2B is in triode.

NMOS Configuration PMOS Configuration

M1B NMOS operates in triodeM1B NMOS operates in triode M2B PMOS operates in triode

X is a low-impedance node Y is a low-impedance node(a) (b)

NMOS Configuration PMOS Configuration

L=L1+L2

Figure 2.15: Illustration of split-length transistors.

Now, personal communication with Furth lead to an interesting technique,

which improves the LDO performance. In this technique, we not only vary the

length of the transistors, but also the width of the transistors keeping the dimen-

sion as WL2

and mWL1

for the transistor in triode and saturation, respectively, where

L2 > L1. This is the main compensation technique that we used in our design

with some additional compensation techniques to have a stable system.

2.7 Split-Length Compensation

As discussed in the previous section, split-length transistors form an in-

termidiate low-impedence node. If any current is fed to this node through com-

pensation capacitors, than this path works as split-length compensation network.

Fig. 2.16 shows split-length compensation for NMOS transistor. The small signal

model for this compensation network is shown in Fig. 2.17

22

G

D

S

W/L

G

D

S

M1

M1A

M1B

CC

Ifb

X

mW/L1

W/L2

Figure 2.16: Illustration of split-length compensation for NMOS.

VX

Figure 2.17: Small signal model for split-length compensation for NMOS.

23

The transconductance, gm of a transistor of size WL

in strong inversion is

given by the equation

gm =

√µn · COX ·

W

L· ID (2.16)

For split-length compensation with varied width, transistor M1A is in sat-

uration and M1B is in deep triode. The transconductance gm1A and gm1B can be

found by the equations

gm1A =

√µn · COX ·

mW

L1· ID (2.17)

gm1B =

√µn · COX ·

W

L2· ID (2.18)

The input resistance at node X is given by

Rin =1

gm1A

|| 1

gm1B

(2.19)

2.8 Non-Overlapping Clock Generator Circuit

A clock generator input is a single clock but it produces two-phase non-

overlapping clocks. The schematic of the clock generator circuit is shown in

Fig. 2.18. A non-overlapping clock generator has a common turn OFF time be-

tween two transitions known as dead time and is shown in Fig. 2.19. Dead time

24

is created by incorporating the same number of delay cells between the input

and output clocks. The function of NAND gates is to make the signals non-

overlapping. To drive large capacitive load, a driver circuit is needed.

CLOCK

Phase 2 (φ2)

`

Delay cells

Figure 2.18: Schematic of a typical Non-overlapping clock generator [17].

25

Dead time Dead time Dead time Dead time

Ph

ase

1P

has

e 2

Time

Time

Figure 2.19: Output waveforms phase 1 and phase 2 of the non-overlapping clockgenerator [17].

26

Chapter 3

DESIGN AND SIMULATIONS

In this chapter, we discuss the detailed explanations of the proposed LDO. In the

beginning, we show the schematic of the proposed LDO. Discussion of its operation

follows. We also show other circuits that we make up to design the LDO. The

working principle of the charge pump and the non-overlapping clock generator are

also discussed in this chapter. An AC small signal model is also included here.

This chapter is concluded with load and line transient, PSR, Ripple and dropout

voltage measurement test benches and discussions of the simulation results.

3.1 Proposed Low-Dropout Voltage Regulators

We proposed two LDOs that are identical, except for the compensation.

The schematic is shown in Fig. 3.1. The two propsed designs are named LDO1

and LDO2. Device dimensions values are given in Table. 3.1.

As we can see from the schematic, it has an NMOS differential pair as the

first stage. Split-length transistors are used instead of single NMOS transistor.

The intermediate low impedence node of this configuration is used for compen-

sations. The second stage uses a single PMOS transistor as a common source

amplifier. This configuration helps to improve the output swing. At the output

stage, an NMOS pass element is in source follower configuration. The most inter-

esting part of this LDO is in between stage two and the output stage. A capacitor

CBATT that is fed by a charge pump is there. The charge pump actually works as

27

VREF

MBIAS M5

M1A

M1B

M2A

M2B

M3 M4 M6

M7

IBIAS

VDD

VSS

CHARGE

PUMP

VFB

VOUT

COUT

IL

MNPASS

V1

V02 VI3

VX

VY

VBIAS

FIRST STAGE SECOND STAGE OUTPUT STAGE

VFB

CBATT

Figure 3.1: Schematic for the proposed LDO.

a DC source to boost the gate voltage of the pass element. The main reason why

we used it is to get lower dropout voltage for the regulator.

3.2 Proposed LDO Regulator Architecture and Design

The schematics of the proposed LDOs showing compensation networks are

shown in Figs. 3.2 and 3.3. The first-stage has a split-length NMOS differential

pair, as discussed in Chapter 2. Both first and second stages are inverting. Miller

compensation RC and CC from the second stage output to the first stage output is

introduced. Another compensation network from the output of the second stage

is connected to the mid-point of the split-length differential pair through CC1.

Another capacitor CC2 was added from the output of the LDO to the mid-point

of the split-length differential pair. All the above statements hold true for both

28

Table 3.1: Device dimensions in µm for the LDO1 and LDO2.

LDO1 LDO2Transistors W

Lµm

M1A, M2A2

0.270, m=2

M1B,M2B1

0.450, m=2

M3,M43

0.540, m=2

M51

0.540, m=4

Mbias1

0.540, m=1

M63

0.540, m=10

M71

0.540, m=10

MPass30

0.180, m=200

CBATT 10 pF

LDOs except that RC1 was added in series to CC1 in LDO2. Also for LDO2, an

additional capacitor CC3 was added in the gate of the NMOS pass element. The

other end of the capacitor was grounded.

The dimensions for all devices in the compensation networks are shown in

Table 3.2.

Table 3.2: Component’s values used in both LDOs.

LDO1 LDO2

RC 200 kΩ

CC 500 fF

RC1 N/A 100 kΩ

CC1 3 pF

CC2 1.5 pF

CC3 N/A 10 pF

While designing, first step was to design a simple two-stage amplifier with

good gain. The amplifier was tested for stability. After tweeking the compensation

when the system was stable, the pass element was added to the design. A capacitor

CBATT was added in between the output of the second stage and input of the

29

output stage. This capacitor is used to boost the DC voltage with the help of a

charge pump.

It is assumed that the charge pump that will be designed to be capable

of boosting the DC voltage by approximately 800 mV. So, during simulations,

the capacitor has the condition that its initial voltage is 800 mV. The System is

also tested for stability. Compensations network is tweeked to make the system

stable. Upon finding the system to be stable, it is tested for dropout voltage.

The size of the pass element is kept as a variable. Tests are performed until the

desired dropout voltage is achieved. After fixing the pass element size, the LDO

is again tested for stability. If needed, compensation values are tweeked more to

achieve a stable system. Finally it is tested for all other performance parameter

like recovery time, line transient, load transient, PSR and dropout etc. And the

results are found to be closer to specifications.

VREF

MBIAS M5

M1A

M1B

M2A

M2B

M3 M4 M6

M7

IBIAS

VDD

VSS

CHARGE

PUMP

VFB

VOUT

COUT IL

MNPASS

RC CC

CC1

CC2

V1

V02 VI3

V11

VX

VY

VBIAS


VFB

CBATT

Figure 3.2: Schematic of the Proposed LDO1 with Compensation Capacitor.

30

VREF

MBIAS M5

M1A

M1B

M2A

M2B

M3 M4 M6

M7

IBIAS

VDD

VSS

CHARGE

PUMP

VFB

VOUT

COUT

IL

MNPASS

RC CC

CC1

CC2

RC1

CC3

V1 VO2 VI3

V11

VX

VY


VFB

CBATT

Figure 3.3: Schematic of the Proposed LDO2 with Compensation Capacitor.

3.3 Small Signal Analysis

The small signal architectures of LDO1 and LDO2 are shown in Figs. 3.4

and 3.5, respectively. The motivation for using this model is to analyze the DC

gain of each individual stage of the proposed LDOs and to conduct a thorough

pole-zero analysis.

3.3.1 First Stage

The first stage of the proposed LDO is a spilt-length NMOS differential

amplifer. The first stage provides a fair portion of the overall gain of the amplifier.

In this stage, we see a conversion from diffential input to single-ended output which

is achieved by current mirror M3 and M4. Current from M1A is mirrored by M3

to M4. This current is substracted from the current of M2A to create the single-

ended output. Now, with an increase in the feedback voltage VFB, the voltage at

the gate of the PMOS current mirror VY starts decreasing, resulting in an increase

31

-GM1 -GM2 +GMPASS

R1 C1 R2 C2 ROUT COUT

VIN VOUT

RC CC

+gM2A

1/g

M2A

1/g

M2B

CC1CC2

CBATT

V1 V2 V3

Figure 3.4: Small-signal architecture of LDO1.

of the voltage V1. On the other hand, if the feedback voltage VFB decreases the

voltage VY increases and then the voltage V1 decreases.

The first stage transconductance GM1 is given by,

GM1 =gM2A · gM2B

gM2A + gM2B

(3.1)

32

-GM1 -GM2

+GMPASS

R1 C1 R2 C2 ROUT COUT

VIN VOUT

RC CC

+gM2A

1/g

M2A

1/g

M2B

CC1CC2

RC

1

CBATT

C3

V1 V2V3

Figure 3.5: Small-signal architecture of LDO2.

where gM2A and gM2B are transconductances of the transistors M2A and M2B,

respectively. The output resistance R1 of the first stage is given by,

R1 = ro4 ‖(gM2A · ro2A ·

1

gM2B

)(3.2)

where ro4 is the output resistance of transistor M4 from node V1 to ground.(gM2A·

ro2A · 1gM2B

)is the output resistance of the split-length transistors M2A and M2B

33

looking from the drain of M2A to ground. Thus, the first stage gain AV 1 is given

by

AV 1 = GM1 ·R1 =

(gM2A · gM2B

gM2A + gM2B

)·(ro4 ‖ gM2A · ro2A ·

1

gM2B

)(3.3)

3.3.2 Second Stage

This stage has a PMOS transistor with an active load NMOS current

source. The PMOS transistor in this stage is configured in common source mode.

This configuration helps improve the output swing of stage two. This stage is an

inverting stage. The output V1 of the first stage is the input to the second stage

here. The output of this second stage is applied to the input of the charge pump.

The gain of the second stage is:

AV 2 = gM6 ·(ro6 ‖ ro7

)(3.4)

where gM6 is the transconductance of transistor M6 and r06 and r07 are the output

resistances looking into the drains of transistors M6 and M7, respectively. The

biasing circuit ensures a proper operating point so that the transistors are in

saturation region.

3.3.3 Gain in Level Shifter

The capacitor CBATT which is connected with a charge pump has a DC

gain. This gain is basically a voltage divider in capacitors. The gain formula is

AV 3 =CBATT

CBATT + C3

(3.5)

34

where for LDO1 C3 is the gate to source parasitic capacitance of pass transistor.

This capacitance is negligible in comparison with CBATT , hence the gain is unity.

For LDO2, this parasitic capacitance is negligible with respect to actual C3.

3.3.4 Output Stage

The output stage of the proposed LDO is a common drain amplifier, also

known as a source follower. This transistor is called the pass element and con-

sidered the most important part of the LDO. The gate or the input of the pass

element is connected to the high voltage side of the capacitor CBATT . The drain

of the pass element is connected to the supply voltage. The source of the NMOS

pass element is the output node.

To achieve a low dropout value, the gate voltage of the pass element needs

to be higher than the supply voltage. The charge pump does the job. The input

resistance of the output stage is very high, therefore, no current passes through

the input. And the output resistance of the source follower is very low which

means it can be driven at high loads. All the load current comes from the supply

voltage through the drain to the source. This drain current or load current is

a direct function of VGS along with some transistor parameter. Therefore, for

a fixed load current, if the gate voltage increases, and the load current cannot

be changed, then the source voltage must increase. This is the trick we pick for

designing low drop out. If we can increase the gate voltage of the pass element

to a high value, we can easily get a very low dropout from this regulator. As this

stage is basically a buffer stage, it does not contribute in voltage gain.

Ignoring the body effect, the gain equation of this stage can be written as:

AV O =

(gMPASS

gMPASS + 1rOPASS

)≈ 1 (3.6)

35

If we include the body effect, the gain equation can be written as:

AV O =

(gMPASS

gMPASS + gmb + 1rOPASS

)< 1 (3.7)

where gmb is the backgate transconductance, and is defined as the change in drain

current due to change in backgate bias voltage [18].

Typically, under no load conditions, AV O=0.8 V/V [19].

The overall gain of the LDO is

ALDO = AV 1 · AV 2 · AV 3 · AV O (3.8)

3.3.5 Charge Pump Operation

A charge pump is a type of DC-DC converter. It can increase or decrease

a DC voltage using capacitors and switches. Because the NMOS pass element

needs a voltage higher than the supply voltage for proper functioning, a charge

pump is introduced to the LDO cuicuit. One of the design constraints is that, no

current can be drawn from VREF . In addition, if VREF is held at zero, the charge

pump will not charge.

The charge pump needs one capacitor, four NMOS and one PMOS tran-

sistor. The schematic of the proposed charge pump is shown in Fig. 3.6. One

of the NMOS transistors MC5 is used as switch. Capacitor CF is a flying ca-

pacitor. CBATT is the reservoir capacitor. One of the NMOS transistors MC2 is

connected such that it forms a diode. The final PMOS MC3 and NMOS MC4 are

used as transmission gate switch. Reason we use transmission gate switch here is

beacause, VO2 range is wide, and transmission gate allows both strong and weak

signals to pass through it undegraded. Sizes used for all the MOSes were mini-

mum size. Typically the flying capacitor CF , is 10 times smaller than the reservoir

36

CBATT . The flying capacitor is used for charging up the reservoir capacitor, which

works as a battery in the amplifier.

Designing transistor MC1 is tricky. It behaves as a diode-connected tran-

sistor attached to VREF . The drain terminal however, is attached to VDD so that

no current is drawn from VREF . We could have connected VDD instead of VREF

to the gate terminal. We would have gotten a higher voltage from the charge

pump. But the system would have shown poor noise rejection from VDD. We also

could have connected the drain terminal to VREF , but the design would not only

produce lower output voltage but also draw current from VREF . So, our trade-off

is to connect the drain terminal to VDD.

During phase one, as shown in Fig. 3.7(a), when φ1 is high, the lower

terminal of the flying capacitor CF is pulled down to zero. Because VREF is

connected to the gate of the NMOS MC1, it will be ON and the source of this

transistor will charge to the voltage of VTHN below VREF . Now during phase two,

as shown in Fig. 3.7(b), when φ2 is high and φ1 is low, MC5, will be OFF. The

charge pump input VO2 will be applied to the lower terminal of the CF through

transmisson gate switch. Due to the property of the capacitor, the other end

of capacitor CF will change drastically to maintain the same potential difference

between the terminals, resulting in a higher voltage at the upper terminal of the

flying capacitor. Now, NMOS MC2 is configured as a diode. The higher voltage

at the capacitor terminal will make MC2 forward biased and current will flow

through the diode to charge the reservoir capacitor CBATT . Then again, when

we return to phase φ1, the higher voltage at the upper terminal of the reservoir

cannot be discharged because of the reverse biased diode MC2. So the capacitor

holds charge until it finds an external discharging path.

The dimensions used for the charge pump are given in Table. 3.3

37

MC1

VSS

VDD

VREF

VO2

VI3

MC2MC3MC4

MC5

CF

CBATTMNPASS

VDD

CHARGE PUMP

PHI1PHI2 PHI2B

Figure 3.6: Schematic of the designed Charge Pump.

Table 3.3: Device dimensions in µm for Charge Pump.

Transistors WLµm

MC1, MC20.6000.180

MC4, MC50.6000.180

M31.2

0.180

CF 500 fF

3.3.6 Non-overlapping Clock Genarator Design

To avoid charge sharing of the capacitors in the charge pump, two non-

overlapping clock signal Φ1 and Φ2 are required. These two signals Φ1 and Φ2 are

generated with a dead time of 8 ns. The schematic of the clock generator circuit

38

(a) (b)

Figure 3.7: Charge Pump operation.

is shown in Fig. 3.8. Eight inverters and seven resistors are needed in each path

of the clock generator to achieve the required dead time. Two more inverters are

used in each path as the driver circuit. There is one more inverter at the clock

input. This inverter adds additional delay in the respective path of the clock

generator. To compensate for this delay, a transmissation gate of the same size is

introduced into the other path of the circuit.

Series inverters and resistors contribute to the desired delay in the output

because of the RC time constant of the circuit. The RC time constant can be

tuned by changing C or R values. In this design, we increase R more rather than

C to get our required delay. The reason to use a higher resistance is that dynamic

power consumption is a function of capacitance. For any switching circuit, the

dynamic power consumption is a function of frequency given by

39

PDYN = C · V 2 · fop (3.9)

where C is the capacitance, V is the applied voltage and fop is switching frequency.

Inverters used in the design were multiplicity 1 and resistors were 500k Ω.

The clock generator was tested with 10 kHz clock and the result was found to be

very close to the design value.

Ths dimension used for the non-overlapping clock generator is shown in

Table. 3.4

Table 3.4: Device dimensions in µm for Non-overlapping Clock Generator.

Devices WL

RCLK 500 kΩ

INV X11.2

0.180,

PMOS

0.6000.180

,NMOS

TG 1.20.180

,PMOS

0.6000.180

,NMOS

NAND 1.20.180

,PMOS

1.20.180

,NMOS

3.3.7 Poles and Zeros

The LHP dominant pole ωP1 & ωP2 for LDO1 can be found at

ωP1 = − gM2A + gM2B

gM2 · gM2B ·R1 ·R2 · (CC1 + CC2 · AV3)(3.10)

ωP2 = − 1

ωP1 · CC2 ·ROUT · COUT ·R1 · AV2(3.11)

40

VDD

SW1

SW2

SW2B

A

B

NAND

CLK

VSS

TG

SW1B

A

B

NAND

INVX1

500k

Delay Cell Delay Cell

500k

INVX1

Figure 3.8: Schematic of the designed non-overlapping clock generator, which uses7 delay cells in each path.

The LHP dominant zero ωZ1 for LDO1 is found at

ωZ1 = − gM2A+gM2B

CC1·(1+gM2B

gMPASS)+CC2

3.4 Simulation Results

In this section of the chapter, AC analysis, dropout voltage measurement,

line and load transient responses and power supply rejection results are shown

and discussed.

3.4.1 AC Analysis

The AC test bench for the two designs is shown in Fig. 3.9. A current

mirror is used to provide load current IL to the output of the LDO. Sizes of the

transistors are carefully designed to handle the huge load current of 100 mA. The

41

transistors in the current mirror are in ratio of 4 : 1. The impedence of a single

bonding wire of an IC is modeled as 1.37 nH inductor in series with 100 mΩ

resistor and the capacitance is 120 fF, as is shown in Fig. 3.9. Eight such parallel

models are connected to the input and output of the LDOs because the number of

pins used is eight each for both input and output. In this test bench, the battery

capacitor is configured such that its initial voltage value is 800 mV. The charge

pump is omitted.

The only difference between the test benches is, for LDO1 we use four

input pins and two output pins. On the other hand, for LDO2, all eight input

pins and output pins are used.

An AC input source with a magnitude of 1 V and a phase of 180o is placed

to perform the AC analysis. A capacitor of 1 F is used for injecting the AC input

signal to the LDO. A large resistor of 1 GΩ is used to the break the feedback loop

of the LDO from VOUT to the negative V− terminal of the error amplifier.

LDO1 and LDO2 are simulated at both minimum and maximum load

currents of 3 µA and 100 mA, respectively. Simulated AC results of LDO1 are

shown Fig. 3.10. The LDO2 simulated AC results are shown in Fig. 3.11. AC

analysis comparison of LDO1 and LDO2 at minimum load current IL,min=3 µA

and maximum load current IL,max=100 mA is given in Table. 3.5.

Table 3.5: AC analysis for LDO1 and LDO2 Regulator at IL,min = 3µA andIL,max = 100 mA.

LDO1 Regulator LDO2 RegulatorIL 3µA 100 mA 3µA 100 mAGain 66.6 dB 66.74 dB 66.6 dB 66.74 dBGM 50.57 dB 25.71 dB 15.62 dB 38.68 dBPM 49.17 91.3 57.52 91.94

fUGF 263.2 kHz 430.2 kHz 297.7 kHz 784.5 kHz

42

AC

12.5 mΩ

0.171 nH

12.5 mΩ

0.171 nH

LDO

VIN

VREF

1 F 1 GΩ

CL

IBIAS

VDD

IL/4

IL5

0 Ω

50

Ω

VOUT

VSS

96

0 f

F

10

0 p

F

96

0 f

F

VDD

Ro

utm

ax

8 Parallel I/O Pads

and Bonding Wires

8 Parallel I/O Pads

and Bonding Wires

AC open-loop

4:1

Figure 3.9: Testbench for AC analysis.

From Table. 3.5, we see that the unity gain frequency fUGF increases as IL

increases. Phase Margin (PM) also increases as IL increases. The gain is identical

for the two designs because only compensation is different. Results show improved

AC performance of LDO2 over LDO1.

3.4.2 Dropout Voltage Measurement

The test bench for dropout measurement is shown in Fig. 3.12. Like the

AC analysis, this test bench also has the same value for equivalent series inductors,

resistors and equivalent capacitors based on the number of pads used. In the case

43

Figure 3.10: LDO1 AC analysis.

of dropout measurement, a triangular input VIN with a very slow rise and fall

times of 25 ms is applied. The dropout is measured at the maximum load current

IL,max=100 mA. Initially the dropout voltage was measured using a battery in

place of CBATT . The battery voltage was set to 800 mV. After the dropout test,

the battery was replaced by CBATT and a charge pump in simulation. The charge

pump was expected to deliver an 800 mV difference in the DC voltage between

the output of the second stage and the input of the third stage. And the system

was again tested for dropout voltage.

44

Figure 3.11: LDO2 AC analysis.

Dropout voltage comparison for both LDO’s at maximum load current

IL,max = 100 mA is shown in Table. 3.6. The measured dropout voltages using

the battery are 62 mV and 39 mV, respectively for LDO1 and LDO2 which are

within our specifications. And the measured values for dropout are 202 mV and

121 mV, respectively for LDO1 and LDO2 with CBATT and charge pump. The

difference is significant, roughly three times higher than expected.

45

0.171 nH

0.171 nH

LDO

VREF

CL

IBIAS

VDD

IL/4

IL

50

Ω

50

Ω

VOUT

VSS

Tri

ang

ula

r P

uls

e w

ith

rise

an

d f

all

tim

e 2

5 m

s

VFB

96

0 f

F

10

0 p

F

96

0 f

F

VDD

Routm

ax

8 Parallel I/O Pads

and Bonding Wires

8 Parallel I/O Pads

and Bonding Wires

4:1

12.5 mΩ

12.5 mΩ

Figure 3.12: Test bench for dropout voltage simulation.

Table 3.6: Simulated dropout voltage for LDO1 and LDO2 at maximum load withand without the charge pump and the capacitor CBATT .

LDO1 LDO2

VDO with battery 62 mV 39 mVVDO with CBATT and CP 202 mV 121 mV

46

3.4.3 Line Transient

The testbench for line transient analysis is given in Fig. 3.13 with the same

differences between the two designs, as discussed in earlier test benches. A current

source was used as the load so that the output current is constant. The input

voltage, VIN was varied from 1.5 V to 1.8 V with rise and fall times of 10 ns while

the load current, IL was kept constant at 1 mA during this test. The line transient

responses for LDO1 and LDO2 are shown in Figs. 3.14 and 3.15, respectively.

Rise time tRH,Line, fall time tRL,Line, ∆VOUT,Line, overshoot and undershoot of line

transient response for both designs are shown in Table. 3.7. From the table we see

that, although LDO1 has higher overshoot and undershoot, the recovery time is

faster than LDO2. Line regulation of LDO1 is roughly twenty times smaller than

LDO2. But total change in VOUT during the line transient of LDO2 is almost half

that of LDO1.

Why the line transient of LDO2 is much better than that of LDO1? The

answer is the capacitor C3. For LDO2 this extra capacitor holds the charges for

a longer time. During transient analysis, when the input voltage changes, the

output voltage tends to follow the input, but the gate of the pass transistor gets

enough voltage from C3 to make the transistor on, resulting smaller overshoot and

undershoot than LDO1.

Table 3.7: Line transient simulation results for LDO1 and LDO2 regulators.

LDO1 LDO2

tRH,Line 1.6 µs 2.99 µs

tRL,Line 2.4 µs 3.84 µs

∆VOUT,Line 310 mV 159.5 mV

Overshoot 200 mV 81.06 mV

Undershoot 110 mV 78.5 mV

Line Regulation 0.3 mV/V 6.7 mV/V

47

0.171 nH

0.171 nH

LDO

VREF

CL

IBIAS

VDD

IL/4

IL

50

Ω

50

Ω

VDD

VOUT

VSS

Pu

lse

wit

h r

ise

and

fal

l

tim

e 1

0 n

s

VFB

96

0 f

F

10

0 p

F

96

0 f

F

8 Parallel I/O Pads

and Bonding Wires

4:1

Ro

utm

ax

8 Parallel I/O Pads

and Bonding Wires

12.5 mΩ

12.5 mΩ

Figure 3.13: Test bench for line transient simulation.

48

Figure 3.14: Line Transient Response for LDO1.

49


50

3.4.4 Load Transient

A testbench for load transient analysis is given in Fig. 3.16. The number

of input and output pins determines the equivalent inductance, resistance and

capacitance values associated with each pad/pins. The load current IL varies

from 3µ A to 100 mA with a rise time of 10 ns and fall time of 10 ns while the

input voltage, VIN stayed at 1.5 V throughout this test. As shown in the test

bench, the maximum load current is drawn from VOUT which is mirrored by a

current source so that for any overshoot or undershoot, the output current does

not change. The minimum load current is drawn by a 400 kΩ resistor. Only the

maximum load current was switched on and off to create the load variations.

The load transient response for both LDO’s are shown in Figs. 3.17 and

3.18. tRH,Load, tRL,Load, ∆VOUT,Load, overshoot and undershoot of load transient

response for both designs are summarized in Table. 3.8.

From the simulated results, we see that recovery times and load regula-

tion are almost same for both LDOs but there is a significant difference in total

load transient values. Total load transient value is lower for LDO2 than LDO1.

Although overshoots are almost same for both LDOs, there is a significant im-

provement in undershoot for LDO2. LDO2 is performing better than LDO1 if

load transient test is considered.

Why LDO2 has a better undershoot value than LDO1? The answer is

again the capacitor, C3. This capacitor holds the gate voltage. When load current

increases from 3 µA to 100 mA, the source of the pass transistor starts to decrease

to accomodate higher current. Because the capacitor C3 holds the charges, the

gate voltage remains high, which resists the source voltage to go to a low value.

Already we know that this source voltage is our output voltage.

51

0.171 nH

0.171 nH

LDO

VREF

CL

IBIAS

VDD

RL

IL

50 Ω

50 Ω

VL

VOUT

VSS

Pulse such that IL rise

and fall time is 10 ns

VFB

VIN 960 f

F

100 p

F

960 f

F

Routm

ax

8 Parallel I/O Pads

and Bonding Wires

8 Parallel I/O Pads

and Bonding Wires4:1

12.5 mΩ

12.5 mΩ

Figure 3.16: Testbench for load transient simulation.

Table 3.8: Load transient simulation results for LDO1 and LDO2 regulator.

LDO1 LDO2

tRH,Load 16 µs 16 µs

tRL,Load 5.2 µs 7 µs

∆VOUT,Load 879 mV 668 mV

Overshoot 300 mV 297 mV

Undershoot 579 mV 371 mV

Load Regulation 0.02 mV/mA 0.0198 mV/mA

52

(b)

Figure 3.17: LDO1 load transient response.

53

Figure 3.18: LDO2 load transient response.

54

3.4.5 Ripple

Fig. 3.19 shows the test bench for measurement of ripple for both LDOs.

A direct connection from VOUT is drawn to the negative input terminal of the

error amplifier. A constant voltage of 1.5 V is applied as the input. A transient

simulation is run. The test is performed for different load current, and the ripple

is found to be the same.

0.171 nH

0.171 nH

LDO

VREF

CL

IBIAS

VDD

IL/4

IL

50

Ω 50

Ω

VDD

VOUT

VSS

VFB

96

0 f

F

10

0 p

F

96

0 f

F

8 Parallel I/O Pads

and Bonding Wires

4:1

Ro

utm

ax

8 Parallel I/O Pads

and Bonding Wires

VDD

12.5 mΩ

12.5 mΩ

Figure 3.19: Test Bench for Ripple measurement.

Clock is the source of ripple in the LDO. When there is a transition in

clock, ripple can be observed in the output. If clock is removed, ripple goes away.

The measured values of ripple are shown in Figs. 3.20 and 3.21 for LDO1 and

LDO2, respectively. As seen from the figures, LDO2 has lower ripple voltage

(0.6 mV) than LDO1 (1.6 mV) and is almost three times smaller.

55

Figure 3.20: Ripple measurement for LDO1 at Load Current = 1 mA.

3.4.6 Power Supply Rejection

Fig. 3.22 shows the test bench for measuring power supply rejection (PSR).

A direct connection from VOUT is given to the negative terminal of the error

amplifier. In the input signal, noise is introduced with the help of an AC voltage

source. An AC supply is connected in series with the DC supply voltage VDD.

Our goal is to find how much AC signal we receive at the output for different

frequencies. AC analysis is run in Spectre. PSR is measured for a load current of

IL=1 mA. PSR is defined as

PSR = 20 · log(VDD,AC

VOUT

)(3.12)

56

Figure 3.21: Ripple measurement for LDO2 at Load Current = 1 mA..

The PSR results are shown in Figs. 3.23 and 3.24 for both LDO1 and

LDO2. As seen from the figures, PSR is very good at low frequencies, and as

frequency increases, the PSR drops. It was found that, within the unity gain

frequencies of the LDOs, the PSR values are 16 dB for LDO1 and 14 dB for

LDO2. We also see that, PSR curves of LDOs follows AC gain curves. We can

conclude that PSR values are roughly the AC gain plus 16 dB or 14 dB for LDOs

at high frequency. At low frequency, PSR value are the same for both LDOs.

57

0.171 nH

0.171 nH

LDO

VREF

CL

IBIAS

VDD

IL/4

IL

50

Ω 50

Ω

VDD

VOUT

VSS

VFB

96

0 f

F

10

0 p

F

96

0 f

F

8 Parallel I/O Pads

and Bonding Wires

4:1

Ro

utm

ax

8 Parallel I/O Pads

and Bonding Wires

AC

VDD

12.5 mΩ

12.5 mΩ

1 V 00Phase

Figure 3.22: Test Bench for PSR measurement.

58

Figure 3.23: PSR waveform for LDO1.

59


60

Chapter 4

EXPERIMENTAL RESULTS

The layout techniques used for LDO1 and LDO2 are discussed here. A microscopic

view of the IC is shown in this chapter along with major hardware results of LDO1

and LDO2.

4.1 Layout

Both chips were fabricated in 0.180 µm IBM 7 RF technology and packaged

in QFN-40 packages through MOSIS. A microscopic view of the LDO1 is shown

in Fig. 4.1. Almost nothing can be seen except for the metal 6 layer.

The layouts of LDO1 and LDO2 are shown in Figs. 4.2 and 4.3, respectively.

The total area of the two designs, area of the pass transistor and total capacitance

are shown in Table 4.1. LDO1 is also shown in Fig. 4.4 with the 40-pin pad frame.

29 pins are used for testing the LDO. 3 pins are left empty. The remaining 8 pins

are used for testing the charge pump and a resistor layed out in the IC. The same

configuration is used for LDO2.

The common-centroid technique is used to ensure good matching of both

NMOS and PMOS transistors. Common-centroid was mainly applied to differen-

tial pairs and current mirrors. The layout area of the two LDO designs are the

same except for the LDO2 has an additional 10 pF capacitor and 100 kΩ resistor.

4.1.1 Passive Elements Layout

Several capacitors and resistors were layed out in the IC, which are mainly

used in the compensation network, charge pump and clock generator. Five capac-

61

Figure 4.1: Microscopic view of LDO1 (Die measure 1.5 mm x 1.5 mm).

itors were used of size 10 pF, 3 pF, 1.5 pF, 500 fF and 100 fF. One of the beauty

of the IBM 7 RF tool kit is that it automatically creates the layout. We need to

choose only the dimensions. We used the MIM capacitor which uses metal layers 6

and 7. Resistors are also layed out automatically and we need to choose only the

dimensions. Three resistors are layed out in the IC of values 500 kΩ, 200 kΩ and

100 kΩ. We use oprrpres (the high-resistance polisilicon resistor) resistors.

Figs. 4.5 and 4.6 show layouts of a 10 pF capacitor and 200 kΩ resistor.

4.1.2 Pass Element Layout

The layout of the pass element is challenging. The width of the NMOS

pass element is 6 mm. It is a mammoth transistor. It is layed out block by block.

The first step is to layout a transistor with a width of 300 µm. Then connect four

identical 300 µm transistors with drains and sources shared, which results in a

62

Table 4.1: Layout Area for LDO1 and LDO2 regulators and Components.

LDO1 LDO2

Pass Element 44.84 µm x 127.17 µm

Error Amplifier 30.11 µm x 15.15 µm

Cap 10 pF 74 µm x 73.87 µm

Cap 3 pF 42.35 µm x 42.35 µm

Cap 1.5 pF 31.14 µm x 31.15 µm

Cap 500 fF 19.71 µm x 19.72 µm

Resistor 500 k 44.84 µm x 127.17 µm

Resistor 200 k 21.85 µm x 23.14 µm

Resistor 100 K 21.85 µm x 11.29 µm

Charge Pump 95.64 µm x 74 µm

Clock Generator 155.55 µm x 137.24 µm

Total Area of Components 38484 µm2 43950 µm2

1.2 mm transistor. Five rows of 1.2 mm transistor are then connected to get the

whole 6 mm pass transistor. Because the LDO is designed for 100 mA maximum

load current, the source and drain of the pass element are made very thick and

three layers of metal are used. For better connectivity of the gate, metal 2 is used

to strap the poly layer. Fig. 4.7 shows the layout of the NMOS pass element.

4.1.3 Layout of Other Circuits

The error amplifier has a split-length NMOS differential with a PMOS

current mirror load, bias circuitry and an output PMOS transistor in common-

source configuration with an NMOS current source load. The NMOS differential

pair, PMOS current mirror, all the biasing circuits and the second-stage PMOS

common-source amplifier, were all layed out using the common centroid technique

for better matching. Once all the transistors are connected properly, compensation

networks are added to respective ports.

63

Figure 4.2: Layout of LDO1 (Dimension 275 µm x 437 µm).

The charge pump consists of five transistors of unit size and two capacitors

of 10 pF and 100 fF. The function of the charge pump is to take the error am-

plifier output as input and boost the value so that the pass element can have the

necessary voltage it needs to operate the LDO properly. The first step of laying

out the charge pump is placing two capacitors. They take considerable space.

Then the rest of the transistors are placed in the empty spaces between the two

capacitors and connected properly with metal layers.

64

Figure 4.3: Layout of LDO2 (Dimension 424 µm x 437 µm).

A non-overlapping clock generator with one input clock but two output

clocks is designed and layed out. There is a common turn off time between the

two phases of the clock outputs which is known as dead time. The clock generator

has a series of resistors and inverters which generate the necessary delay for the

dead time, a driving cell and NAND gates. The designed and layed out clock

generator has a dead time of 8 ns. While laying it out, the first step is to layout a

resistor and an inverter. Then connect seven such blocks together for each path.

The driver circuit, transmission gate and NAND gates are layed out and connected

with metal 1 and metal 2.

65

Figure 4.4: Layout of LDO1 with 40-pin pad frame (1.5 mm x 1.5 mm).

4.2 Hardware Results

LDO1 is tested on a bread board with the help of a 40 pin QFN to DIP

converter. For LDO2, a custom made Printed Circuit Board (PCB) was designed.

The reason to design a PCB over a bread board is that the PCB offers less parasitic

capacitance than that of a breadboard. The test procedure for LDO2 is described

in Appendix A. The same bias current Ib = 200 nA is used for both LDO1 and

LDO2. The 100 pF output load capacitance, CL, is not layed-out on chip. A

capacitor of 90 pF is used as the load capacitor CL. The parasitic capacitance

of the probes is about 10 pF, making the total load capacitance 100 pF. All the

66

Figure 4.5: Layout of 10 pF Capacitor.

connections are the same for both designs. For testing using the bread board, the

connections are changed manually, keeping all of the component values the same.

4.2.1 Dropout Voltage

The dropout voltage measurement for LDO1 and LDO2 are shown in

Figs. 4.8 and 4.9, respectively. Matlab is used for plotting these waveforms.

Dropout is measured at the maximum load current IL = 100 mA. At IL = 3 µA

the dropout value is almost zero. The clock frequency used to test the dropout

was 40 kHz. The load capacitor is 100 pF. To ensure a biasing current IBIAS of

200 nA, a resistor of appropriate value is used. Dropout is measured using

VDO = (VIN − VOUT ) |VOUT=VOUT,MAX−VOUT,MAX∗5% (4.1)

67

Figure 4.6: Layout of 200 kΩ resistor.

Table 4.2: Experimental dropout voltage for LDO1 and LDO2 at maximum load.

LDO1 LDO2Vdo 177 mV 82 mV

Table 4.2 shows the measured dropout voltages for LDO1 and LDO2. We

see that LDO2 has much better dropout (82 mV) than that of LDO1 (177 mV).

4.2.2 Ripple Measurement

Figs. 4.10 and 4.11 show a zoomed area for measuring the ripple of LDO1

and LDO2, respectively. Ripple is found to be independent of load current. In

this test, ripple is measured for a load current of 1 mA. The clock is responsible

for any ripple in the output. During every clock transition, ripple is observed at

the output. If we disconnect the clock, the ripple goes away. During this test,

68

Figure 4.7: Layout of NMOS Pass Element (Dimensions 44.65 µm x 127.97 µm).

a fixed input of 1.5 Volts is supplied to the LDOs. Ripple values are 9 mV and

3.8 mV, respectively, for LDO1 and LDO2.

4.2.3 Line Transient Response

Figs. 4.12 and 4.13 show the measured line transient response for LDO1

and LDO2, respectively. For the line transient measurement, the line voltage VIN

varies between 1.5 V to 1.8 V with equal 18 ns rise (trise) and fall (tfall) times.

Rise and fall times in Rigol DG4102 function generator can not be lowered below

10 ns. Because of the parasitic capacitance the rise and fall times are found to be

18 ns. Rise and fall times are measure from 0% to 100%, rather than from 10%

to 90% or 20% to 80%.

During the line transient test the load current IL stays at 1 mA. The test

procedure for the line transient is described in Appendix A. A load capacitor of

69

Figure 4.8: LDO1 Dropout Voltage Measurement.

100 pF is used for this testing. The measured data is averaged over 512 samples

using the oscilloscope and plotted using MATLAB. Averaging is used to remove

clock ripple, and 60 Hz noise coming from the elecctronic equipment. Overshoot,

undershoot, settling times and total output variation ∆VOUT are given in Ta-

ble 4.3.

70

Figure 4.9: LDO2 Dropout Voltage Measurement.

Table 4.3: Line transient experimental results for proposed LDOs.

LDO1 LDO2

tRH,Line 1.5 µs 1.9 µs

tRL,Line 2.2 µs 2.5 µs

∆Vout,Line 340 mV 162 mV



Line Regulation 1 mV/V 6.7 mV/V

71

Figure 4.10: Waveform for measuring Ripple for LDO1.

72

Figure 4.11: Waveform for measuring Ripple for LDO2.

73


74


75

4.2.4 Load Transient Response

Figs. 4.14 and 4.15 show the measured load transient response for LDO1

and LDO2, respectively. For the load transient analysis, the load current IL varies

between 3µA to 100 mA. During the load transient test, the input voltage VIN

stays at 1.5 V. The test procedure for the load transient is described in Appendix

A. A load capacitor of 100 pF is used. The measured data is averaged over 512

samples using the oscilloscope and plotted using MATLAB. Overshoot, under-

shoot, settling times and total output variation ∆VOUT are given in Table. 4.4.

Figure 4.14: Load Transient Response for LDO1.

4.2.5 PSR Measurements

Figs. 4.16 and 4.17 show the measured PSR waveform versus frequency.

In this test, an AC signal is connected in series with the supply voltage. The

76

Figure 4.15: Load Transient Response for LDO2.

Table 4.4: Load transient experimental result for proposed LDOs.

LDO1 LDO2

tRH,Load 7 µs 16 µs

tRL,Load 2.6 µs 7 µs

∆Vout,Load 1042 mV 610 mV



Load Regulation 0.02 mV/mA 1.0 mV/mA

amplitude of the AC signal is 300 mV (peak to peak) and the supply voltage is

fixed at 1.65V so that the input voltage of the LDO remains within its regulating

range. During this test, the load current is set at 1 mA. With the help of an

77

oscilloscope, the AC portion of the output voltage is measured. PSR is calculated

using the formula

PSR = 20 logInput

Output(4.2)

PSR at low frequency is very high, but as the frequency increases, the PSR

value decreases. At the unity gain frequency fUGF , PSR is found to be the same

for both LDO’s.

78


79


80

Chapter 5

DISCUSSION AND CONCLUSION

In this chapter, the simulated and measured results of the designed LDOs are

discussed. A comparison with several existing designs is provided. Finally, future

work is suggested in this chapter.

5.1 Result Comparison : Simulated vs. Measured

Major test results for LDO1 and LDO2 are summarized in Tables 5.1

and 5.2, respectively. The tables only list the simulated and measured results

of the LDOs. Although we also simulated the LDOs with a battery, instead of

with a capacitor and charge pump, the only change in simulated results occured

for dropout voltage. Other than that, there was no difference between the results

of simulation with a battery and the results of simulation with a capacitor and

charge pump. To calculate % error, we used,

Mismatch =Measured− Simulated

Simulated× 100% (5.1)

Tables 5.1 and 5.2 show that there are some variations between simu-

lated results and measured results. In some cases, measured values are smaller

than simulated values, in some cases, simulated values are smaller than measured

values. For instance, the measured dropout voltages are smaller than simulated

voltages for both LDOs. But measured ripple values are very high in comparison

with simulated ripple values. Measured line and load transient settling times are

81

either smaller than or equal to simulated values. Measured total change in VOUT

in both line and load transient for LDO1 is higher than that of simulated results.

On the other hand, for LDO2, measured total change in VOUT in load transient is

smaller than the simulated value.

The mismatch between simulated and measured results can be caused by

noise from the environment, normal process parameter tolerances, and test setup

and equipment. For instance, the power supply, measurement probe, and func-

tion generator all contribute noise at 60 Hz. Moreover, they have built-in parasitic

capacitance and resistance. All these parasitic capacitances and resistances can

affect the results of the LDOs. And process variation occurs for layed-out com-

ponents. For example, we haved layed-out a 500 kΩ resistor on the chip for test

purpose. When we measured the value with the help of a DMM, the values we

measured were 464 kΩ, 470 kΩ and 460 kΩ. This normal variation occurs for all

on chip resistors and capacitors that we have designed and used in the system.

Moreover, transistor mismatch can contribute in results variation. Metal routing

and contacts contributes parasitic capacitance and resistance of designed values

against layed-out values.

Using Tables 5.1 and 5.2 we can also compare LDO1 and LDO2. We see

a significant improvement in LDO2 in terms of dropout voltage, total variation

in VOUT in line and load transient. However, considering load regulation alone,

LDO1 performs better than LDO2.

Table 5.3 shows the dropout voltage result summary for both LDOs. From

the table, we see that simulated dropout voltages with the battery instead of a

capacitor and charge pump are very low. In contrast, simulated results with a

capacitor and a charge pump and measured results, are roughly three times larger.

82

Table 5.1: Results Comparison for LDO1.

Simulated Measured Mismatch(%)

Dropout Voltage 202 mV 177 mV −12.4

Ripple 1.82 mV 9 mV 374

Line Regulation 0.3 mV/V 1 mV/V 233

OvershootLine 200 mV 224 mV 12

UndershootLine 110 mV 126 mV 14.5

tRH,Line 1.6 µs 1.5 µs −6.2

tRL,Line 2.4 µs 2.2 µs −8.3

∆Vout,Line 310 mV 340 mV 9.7

Load Regulation 0.02 mV/mA 0.02 mV/mA 0

OvershootLoad 300 mV 416 mV 38.6

UndershootLoad 579 mV 626 mV 8.1

tRH,Load 16 µs 7 µs −56.2

tRL,Load 5.2 µs 2.6 µs −50

∆Vout,Load 879 mV 1042 mV 18.5

PSR at fUGF 16 dB 13 dB −18.7

The error in the dropout voltage simulation result was not known until

after measuring the fabricated chips. Due to a memory limitation of the server,

simulations including the capacitor and charge pump of the dropout voltage, were

not possible. Because all other results matched for both simulations (with the

battery or with the capacitor and charge pump), it was thought to be the same.

After analysing the charge pump, the problem was discovered.

. Fig. 5.1 is included here again for better understanding. Looking back

at the description of charge pump operation in Chapter 3, during phase one,

the voltage at the upper terminal of the flying capacitor is charges to value one

VGS below the VREF . Because the charge pump clock cycles are so long, we

assumed VGS= 0.2 V and VREF=1.2 V, respectively, resulting in 1000 mV across

the flying capacitor. As such, during phase two, we expect the gate voltage of the

83

Table 5.2: Results Comparison for LDO2.

Simulated Measured Mismatch(%)

Dropout Voltage 121 mV 82 mV −32.2

Ripple 0.6 mV 3.8 mV 533

Line Regulation 6.7 mV/V 6.7 mV/V 0

OvershootLine 81.06 mV 90 mV 11

UndershootLine 78.5 mV 72 mV −8.2

tRH,Line 2.99 µs 1.9 µs −36.4

tRL,Line 3.84 µs 2.5 µs −34.9

∆Vout,Line 159.5 mV 162 mV 1.5

Load Regulation 0.0198 mV/mA 1.0mV/mA 4950

OvershootLoad 297 mV 210 mV −29.2

UndershootLoad 371 mV 305 mV −17.7

tRH,Load 16 µs 16 µs 0

tRL,Load 7 µs 7 µs 0

∆Vout,Load 668 mV 610 mV −8.6

PSR at fUGF 14 dB 13 dB −7.1

Table 5.3: Simulated dropout voltage for LDO1 and LDO2 at maximum load.

LDO1 LDO2

VDO with battery 62 mV 39 mVVDO with CP 202 mV 121 mVVDO measured 177 mV 82 mV

pass transistor to be 800 mV above the output of the second stage of the error

amplifier after a drop of approximately 0.2 V across MC2. Transistors MC1 and

MC2 experienced body effect. The body effect increases Vthn, leaving a smaller

boosting voltage on CBATT than we expected. This low boosting voltage causes

higher dropout voltage when simulated with a capacitor and a charge pump.

Figs. 5.2 and 5.3 shows measured and simulated PSR values for LDO1

and LDO2, respectively. Both figures follow a similar pattern. Simulated values

are higher than measured values. At low frequencies, simulated PSR values are

84

(a) (b)

Figure 5.1: Charge Pump operation.

higher. As frequency increases the difference between simulated PSR values and

measured PSR values becomes very small. The reason behind this phenomenon

can be justified by the presence of environmental noise. At low frequencies, elec-

tronic devices introduce 60 Hz and 60 Hz harmonics. As frequency increases, PSR

values decrease, hence, measurements at higher frequencies are more tolerant to

environmental noise. Moreover, at frequencies above 1 kHz, 60 Hz harmonics are

negligible.

We were not able to compare simulated and measured AC gain and phase

because it would require opening the feedback loop in the LDOs.

5.2 Comparison with Existing Designs

The proposed LDOs are compared with both NMOS and PMOS pass tran-

sistor LDOs from the literature. Table [5.4] shows comparison of performance pa-

85

Figure 5.2: Measured and Simulated PSR values for LDO1.

rameter with other NMOS LDO. We see from table that our design has the very

low quiescent current in comparison with all other NMOS LODs. The dropout

and line regulations are among the top but total change in VOUT for load transient

is high. For LDO2, load regulation is very poor. PSR of our designs are poor in

comparison with other LDOs.

In Table [5.5] we see the comparison of performance parameter of proposed

LDOs with existing PMOS LDOs. From table we see that, we have the best

86

Figure 5.3: Measured and Simulated PSR values for LDO2.

dropout voltage and efficiency. But total change in VOUT for load transient is very

high. Quiescent current and total change in VOUT for line transient are among the

top.

5.3 Future Work

This was the first ever charge pump NMOS LDO designed in the VLSI

group at New Mexico State University. So we adopted a basic amplifier topology

87

LDO Regulator for Comparison This Work[20] [21] [2] [22] [23] LDO1 LDO2

Technology (nm) 180 350 500 350 500 180 180VDO (mV) 50 300 160 185 ≈300 177 82VDD(V ) 1.9 1.5 1.95 3.3 5 1.5 1.5VOUT (V ) 1.5 1 1.5 2.8 3.3 1.2 1.2Max Load Current (mA) 200 100 500 150 300 100 100Min Load Current (µA) 2 100 0 0 200 100 100CL (pF) 100 100 470 100 100 100IGND(µA) 70 50 517 750 6.88 6.88Line Regulation (mV/V) 10 0.1 12 1 6.7OvershootLine(mV ) 250 1000 224 90UndershootLine(mV ) 250 1100 126 72Load Regulation (mV/mA) 0.1 0.006 0.09 0.02 1OvershootLoad(mV ) 500 50 40 330 416 210UndershootLoad(mV ) 700 110 60 330 626 305Ripple(mV) 12 9 3.8PSR(dB) at fUGH 56 32 13 13Area(mm2) 0.1 0.1 1 0.1 1 0.12 0.18

Table 5.4: Comparison table with existing NMOS LDO.

to make the operation and design not too complex. There are few things that can

be done to improve this LDO performance.

The most pressing issue is the need for a better charge pump that can

boost the voltage by a desired amount.

In LDO2, the addition of a compensation capacitor to ground from the

gate of the pass transistor reduced the gain from V o2 to V i3, from near unity to

0.5. Exploring the effect on performance parameter with the change of the ratio

of this compensation capacitor and CBATT , surely deserves a chance.

Moreover, instead of a two-stage CMOS error amplifier, we can use three-

stage amplifier for higher gain, or class AB amplifier for higher slew rate for

reduced recovery time or feed-forward compensation also reduced recovery time.

88

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If we need higher PSR, feedforward ripple cancellation technique can be

introduced [5].

There is a good scope of optimizing the area of the chip which can be easily

reduced to around 0.05 mm2 to 0.06 mm2

And finally, adaptive biasing can be introduced, which should significantly

improve line and load transient performance of the LDOs. This technique will

increase the device area and quiescent current, however, if the LDO is used to

power highly sensitive devices, then adaptive biasing is one of the best choices.

90

APPENDICES

APPENDIX A

Test Document

A.1 With PCB:

A.1.1 Procedure to Measure Dropout Voltage VDO

1. Place the chip on the PCB. Fig. A.4 shows the dropout measurement setup.

VDD

JPVDDSUPJPVDD

JPIBIAS

IDIODE

JP1JP100MLVS

IOUTMAXJP1M

JPLOADR

VOUT

JPVREF

CLK

JPPADVDD1

JPPADVDD

Figure A.4: Jumper Configuration for Dropout measurement.

2. Apply 1.5 volt in disconnected end of the JPVDDSUP, JPIBVS and JP1.

3. Connect all the negative terminals of the power supplies to the ground pin

of the PCB.

4. Apply 1.2 volt at the jumper JPVREF.

5. Apply a 10 KHz clock at the SMA connector named CLK.

6. Place a DMM at the SMA VOUT.

7. Close the jumper JP 100 MLVS and JPVDD.

8. The resistor value of R3U was chosen using the equation (1) which is always

on.

R3U =1.2

3 · 10−6= 400kΩ (1)

93

9. Resistor value of RBIAS was chosen by equation (2)

RBIAS =1.5− 0.367

200 · 10−9= 5.67MΩ (2)

10. Value of the resistor R100ML was chosen considering 50mV drop at the end

of the current mirror using the equation (3)

R100ML =1.5− 0.7− 0.05

25 · 10−3= 30Ω (3)

11. 11. Connect 47µF capacitor with every power supply line with one end to

ground, add another 0.1µF capacitor parallel with the 47µF capacitor to

reduce the noises.

12. By hand slowly vary the voltage from 0 V to 1.5 V at JPVDDSUP. Complete

the below Table. 1 Measure the dropout voltage using the equation (4)

Vdo = Vin − Vout|Vout=Vout,max−Vout,max∗5% (4)

13. Verify that ILOAD= 100 mA for dropout measurement

A.1.2 Line Transient Test Procedure

1. The setup for line transient is shown in Fig.

2. Disconnect the capacitor from the VDD i.e the jumper JPVDD, the main

purpose to detach the capacitor is that, the capacitor does not allow the

voltage to vary 0.3 volt within 10 nano second

94

Table 1: Dropout Voltage Measurement Table

Input Voltage, Vs (V) Output Voltage, Vout (V) Load Current,IL mA0

0.20.40.60.81.01.21.251.31.351.41.451.5

3. Close the jumper JP1ML, the value of the resistor was chosen by the equa-

tion the equation (5).

R1ML =1.2

1 · 10−3= 1.2kΩ (5)

4. Now input a wave varying from 1.85 V to 1.55 V with rise and fall time

of 10 ns to SMA Connector VDD. (Note: As the function generator has

an internal resistance of 50 and the current owing through it is 1 mA, the

voltage drop across it is 50 mV. Hence, varying the input wave from 1.85V

to 1.55 V at the function generator ensures the input varies from 1.8 V to

1.5V at the VDD). The frequency of the waveform is 100 kHz

5. Procedure for Generating a 10 ns Rise and Fall Times Waveform:

Procedure for Generating a 10 ns Rise and Fall Times Waveform

95

Connect the CPU (Central Processing Unit) of the system to function gen-

erator with the help of GPIB (General Purpose Interface Bus). GPIB which

was developed by HP (Hewlett Packard), is a common protocol used by

different testing equipments for their communication. With help of probes

connect the function generator and the oscilloscope.

On the desktop, launch the waveform editor.

From the communications menu, select connection, when the connection

dialog window appears double click on GPIB::10::INSTR, then select the

Internal Type Arb and then click connect.

From the menu select Line Draw Mode, and then draw the desired waveform

with help of mouse.

After drawing the waveform, click on Send Waveform to Arb on the menu.

When the window appears, set the desired frequency and amplitude and

then click send.

Observe the waveform on the scope.

With the help of function generator, parameters like frequency, amplitude

of the waveform on the scope can be changed.

After generating Waveform, Connect the function generator to the JPVDD

6. With the help of 10x probes observe Vout waveform on oscilloscope

and measure undershoot, overshoot, line regulation, trise and tfall by using

cursor. Plot the observed waveforms.

7. Store the waveforms on digital scope and save on Portable Disk.

96

A.1.3 Load Transient Test Procedure

1. The setup for load transient is shown in Fig.

2. Disconnect the function generator from the SMA connector named VDD

3. Disconnect the jumper JP1ML

4. Disconnect the jumper JP100MLVS

5. Connect the function generator to SMA Connector IDIODE, input a wave

form that can vary from 0 to 1.5V with rise and fall time 100 nano seconds.

This way we can make the load current to vary from 3uA to 100mA

6. Connect the jumper JPVDD

7. With the help of 10x probes observe Vout waveform on oscilloscope and mea-

sure undershoot, overshoot, line regulation, trise and tfall by using cursor.

Plot the observed waveforms.

8. Store the waveforms on digital scope and save on Portable Disk.

A.2 With Bread Board

1. All the connection and procedure will be the same.

2. In the bread board there was no jumper, instead direct wire was used.

3. In the bread board connection for input was taken from four pins and two

pins for output.

4. If the solder of the IC was proper, all the eight input and output pins could

have been used.

97

APPENDIX B

Maple

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