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DIGITAL ELECTRONICS

CHETTINAD COLLEGE OF ENGINEERING & TECHNOLOGY

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

Subject Name: Digital Electronics Faculty Name: D.Devilatha & M.Vinoth

Year/Sem: II/III Regulation: 2008

DIGITAL ELECTRONICS

SYLLABUS

UNIT I MINIMIZATION TECHNIQUES AND LOGIC GATES

Minimization Techniques: Boolean postulates and laws – De-Morgan’s Theorem -

Principle of Duality - Boolean expression - Minimization of Boolean expressions ––

Minterm – Maxterm - Sum of Products (SOP) – Product of Sums (POS) – Karnaugh map

Minimization – Don’t care conditions - Quine-McCluskey method of minimization.

Logic Gates: AND, OR, NOT, NAND, NOR, Exclusive–OR and Exclusive–NORImplementations

of Logic Functions using gates, NAND–NOR implementations – Multi

level gate implementations- Multi output gate implementations. TTL and CMOS Logic

and their characteristics – Tristate gates

UNIT II COMBINATIONAL CIRCUITS

Design procedure – Half adder – Full Adder – Half subtractor – Full subtractor - Parallel

binary adder, parallel binary Subtractor – Fast Adder - Carry Look Ahead adder – Serial

Adder/Subtractor - BCD adder – Binary Multiplier – Binary Divider - Multiplexer/

Demultiplexer – decoder - encoder – parity checker – parity generators - code

converters - Magnitude Comparator.

UNIT III SEQUENTIAL CIRCUITS Latches, Flip-flops - SR, JK, D, T, and Master-Slave – Characteristic table and equation

–Application table – Edge triggering – Level Triggering – Realization of one flip flop

using other flip flops – serial adder/subtractor- Asynchronous Ripple or serial counter –

Asynchronous Up/Down counter - Synchronous counters – Synchronous Up/Down

counters – Programmable counters – Design of Synchronous counters: state diagram-

State table –State minimization –State assignment - Excitation table and maps-Circuit

implementation - Modulo–n counter, Registers – shift registers - Universal shift registers

– Shift register counters – Ring counter – Shift counters - Sequence generators.

UNIT IV MEMORY DEVICES Classification of memories – ROM - ROM organization - PROM – EPROM – EEPROM –

EAPROM, RAM – RAM organization – Write operation – Read operation – Memory

cycle - Timing wave forms – Memory decoding – memory expansion – Static RAM Cell-

Bipolar RAM cell – MOSFET RAM cell – Dynamic RAM cell –Programmable Logic

Devices – Programmable Logic Array (PLA) - Programmable Array Logic (PAL) - Field

Programmable Gate Arrays (FPGA) - Implementation of combinational logic circuits

using ROM, PLA, PAL

UNIT V SYNCHRONOUS AND ASYNCHRONOUS SEQUENTIAL CIRCUITS

Synchronous Sequential Circuits: General Model – Classification – Design – Use of

Algorithmic State Machine – Analysis of Synchronous Sequential Circuits

Asynchronous Sequential Circuits: Design of fundamental mode and pulse mode

circuits – Incompletely specified State Machines – Problems in Asynchronous Circuits –

Design of Hazard Free Switching circuits. Design of Combinational and Sequential

circuits using VERILOG

DIGITAL ELECTRONICS

TEXT BOOKS 1. M. Morris Mano, Digital Design, 3rd Edition, Prentice Hall of India Pvt. Ltd., 2003 /

Pearson Education (Singapore) Pvt. Ltd., New Delhi, 2003.

2. S. Salivahanan and S. Arivazhagan, Digital Circuits and Design, 3rd Edition., Vikas

Publishing House Pvt. Ltd, New Delhi, 2006

REFERENCES 1. John F.Wakerly, Digital Design, Fourth Edition, Pearson/PHI, 2006

2. John.M Yarbrough, Digital Logic Applications and Design, Thomson Learning, 2002.

3. Charles H.Roth. Fundamentals of Logic Design, Thomson Learning, 2003.

4. Donald P.Leach and Albert Paul Malvino, Digital Principles and Applications, 6th

Edition, TMH, 2003.

5. William H. Gothmann, Digital Electronics, 2nd Edition, PHI, 1982.

6. Thomas L. Floyd, Digital Fundamentals, 8th Edition, Pearson Education Inc, New

Delhi, 2003

7. Donald D.Givone, Digital Principles and Design, TMH, 2003.

DIGITAL ELECTRONICS

UNIT-I

MINIMIZATION TECHNIQUES AND LOGIC GATES

Two marks:

1. What is meant by bit? A binary digit is called bit.

2. Define byte? A group of 8 bits is called byte.

3. List the number systems? i) Decimal Number system ii) Binary Number system iii) Octal Number system

iv) Hexadecimal Number system

4. What is the abbreviation of ASCII and EBCDIC code? ASCII- American Standard Code for Information Interchange.

EBCDIC- Extended Binary Coded Decimal Information Code.

5. What are the universal gates? NAND and NOR gates(DEC 2011)

6. What are the different types of number complements?

i) r’s Complement ii) (r-1)’s Complement.

7. Why complementing a number representation is needed? Complementing a number becomes as in digital computer for simplifying the

subtraction operation and for logical manipulation complements are used.

8. How to represent a positive and negative sign in computers? i) Positive (+) sign by 0 ii) Negative (-) sign by 1.

9. What is meant by Map method?

The map method provides a simple straightforward procedure for minimizing

Boolean function.

10. What is meant by two variable map?

Two variable map have four minterms for two variables, hence the map consists of four

squares, one for each minterm

11. What is meant by three variable map?

Three variable map have 8 minterms for three variables, hence the map consists of 8

squares, one for each minterm

12. Which gate is equal to AND-inverter Gate? NAND gate.

13. Which gate is equal to OR-inverter Gate? NOR gate.

DIGITAL ELECTRONICS

14. What are the Don’t care conditions? The K map is simplified using 1’s or 0’s which correspond to input varibles that make the

function equal to 1or 0 respectively.The cells which do not contain are assumed to contain 0 and

viceversa.There are cases in which,certain combinations of input variables do not occur.Also for

some functions,the outputs corresponding to certain combinations of input variables do not

matter.In such situations, the designer can assume a 0 or 1 as output for each of these

combinations.This condition is known as don’t care condition and is represented as a X mark in the

corresponding cell.

15. What is the algebraic function of Exclusive-OR gate and Exclusive-NOR gate?

i) F=xy’ + x’y ii) F=xy +x’y’

16. What are the methods adopted to reduce Boolean function? i) Karnaugh map ii) Tabular method or Quine mccluskey method

iii) Variable entered map technique.

17. Why we go in for tabulation method? This method can be applied to problems with many variables and has the

advantage of being suitable for machine computation.

18. State the limitations of karnaugh map.

i) Generally it is limited to six variable map (i.e.) more then six variable

involving expressions are not reduced. ii) The map method is restricted in its capability since they

are useful for simplifying only Boolean expression represented in standard form.

19. What is tabulation method? A method involving an exhaustive tabular search method for the minimum

expression to solve a Boolean equation is called as a tabulation method.

20. What are prime-implicants? The terms remained unchecked are called prime-implicants. They cannot be

reduced further.

21. Explain or list out the advantages and disadvantages of K-map method?(DEC2009) The advantages of the K-map method are

It is a fast method for simplifying expression up to four variables. ii. It gives a visual

method of logic simplification. iii. Prime implicants and essential prime implicants are

identified fast. iv. Suitable for both SOP and POS forms of reduction. v. It is more

suitable for class room teachings on logic simplification.

The disadvantages of the K-map method are i. It is not suitable for computer reduction. ii.

K-maps are not suitable when the number of variables involved exceed four. iii. Care

must be taken to fill in every cell with the relevant entry, such as a 0, 1 (or) don’t care

terms.

DIGITAL ELECTRONICS

22. List out the advantages and disadvantages of Quine-Mc Cluskey method? The advantages are,a. This is suitable when the number of variables exceed four. b. Digital

computers can be used to obtain the solution fast. c. Essential prime implicants, which are not

evident in K-map, can be clearly seen in the final results.The disadvantages are, a. Lengthy

procedure than K-map. b. Requires several grouping and steps as compared to K-map. c. It is much

slower. d. No visual identification of reduction process. e. The Quine Mc Cluskey method is

essentially a computer reduction method.

23. What are the two forms of Boolean expression? i) Sum of Products (SOP) ii) Product of Sum (POS)

24. What are the three laws of Boolean algebra?

i) Commutative Law: A+B=B+A ii) Associative Law:A+(B+C)= (A+B)+C

iii) Distributive Law: A(B+C)=AB+AC

25. Write down the basic rules of Boolean algebra.

a) A+0=A b) A+1=A c) A.0=0 d) A .1=A e) A+A=A f) A+A’=1 g) AA=A h) AA’=0 i)

A=A j) A+AB=A k) A+A’B=A+B l) (A+B)(A+C)=A+BC

26. List the characteristics of digital ICs.

i) propagation delay ii) power dissipation iii) Fan-in iv) Fan-out v) Noise margin

27. What is Fan-in?(MAY 2006) The Fan-in of a logic gate is the number of inputs that can be accommodated on one gate.

When applied to a logic circuit, it’s the number of inputs that the logic circuit can handle.

28. What is Fan-out? (MAY 2006) The Fan-out is the number of similar gates, which can be driven by a gate. High Fan-out is

advantageous because it reduces the need for additional drivers to drive more gates.

29. What is noise immunity or Noise margin? (DEC2009) Noise immunity represents the amount of noise, a logic system can handle without being

amplified beyond unity gain. It is the maximum noise voltage induced in a logic circuit.

30. Define Figure of Merit. It is defined as the product of speed and power. The speed is specified in terms of

propagation delay time expressed in nano seconds.

31. What are the three different types of output configuration in TTL gates? i) open collector output ii) Totem Pole output iii) Three state output

32. Give some applications of open collector TTL gate.

i) Driving a lamp or relay ii) performing wired logic iii) Construction of a common bus

system.

DIGITAL ELECTRONICS

33. When is a totem pole output TTL gate called as a three state gate?

The outputs of the two TTL gates with Totem pole structures cannot be connected together

in an open collector output. There is a special type of totem pole gate that allows the wired

connections of outputs for the purpose of forming a common bus system. When a totem pole

output TTL gate has this property, it is called as a three state (tri state) gate.

34. What are the output states of a three state gate?(MAY2005)

There are three output states. They are i) A low level state, when the lower transistor in the

totem pole is ON and the upper transistor is OFF. ii) A high level state, when the upper transistor

in the totem pole is ON and the lower transistor is OFF. Iii) A third state, when both transistors in

totem pole are OFF.

35.List the six steps in simplifying a Boolean expression using K map.

1. Start with a minterm Boolean expression. 2. Record 1’s on the K map. 3. Loop adjacent

1’s (loops of 2,4,or 8 squares). 4. Simplify by dropping terms that contain a term and its

complement with in a loop. 5. OR the remaining terms. 6. Write the simplified minterm Boolean

expression.

36. What is meant by minterm and maxterm?(APR2004,DEC 2011)

Each individual term in SOP is called minterm and in POS is called maxterm.

37. Give an example of expression in SOP and POS. Sum of Products (SOP): AB+BCD Product of Sum (POS): (A+B)(B+C+D)

38. Where are the CMOS IC’s used?

Electronic wrist watches, Portable computers, Calculators, Space vehicles.

39. State Demorgan’s theorem.(DEC 2009,MAY 2010) 1.The first theirem states that the complement of a product is equal to the sum of the

complements (AB)’ = A’+B’.2.The second theorem states that , the complement of a sum is equal

to the products of the complements (A+B)’ = A’.B’

40. What are the applications of Boolean algebra? (MAY 2010)

It is a convenient and systametic method of expressing and analyzing the operation of

digital circuits and systems.BOOlean algebra uses binary arithmetic variables which have two

distinct symbols 0 and 1.

41. What does LS in 74LS00 indicate?(DEC 2009) LS represent Low Power Schottky TTL Series.

42. Define binary logic?

Binary logic consists of binary variables and logical operations. The variables are

designated by the alphabets such as A, B, C, x, y, z, etc., with each variable having only two

distinct values: 1 and 0. There are three basic logic operations: AND, OR, and NOT.

DIGITAL ELECTRONICS

43. When does the noise margin allow digital circuits to function properly. When noise voltages are within the limits of VNA(High State Noise Margin) and VNK

for a particular logic family.

44.What happens to output when a tristate circuit is selected for high impedance. Output is disconnected from rest of the circuits by internal circuitry.

45. Define power dissipation?

Power dissipation is measure of power consumed by the gate when fully driven by all

its inputs.

12 Marks:

1.Reduce the following function using K map f(A,B,C,D) = ∑m(5,6,7,12,13) + ∑d(4,9,14,15)

• Find the Number of variable map

• Don’t care treat as variable X.

• Draw the Map

• Simplification of SOP & POS

2. Simplify the following expression using Boolean algebra f(x, y, z) = π M(3,5,7) (MAY 2009)

• Reduce the expression using Boolean algebra Laws and theorems

3. Compare and contrast the features of TTL and CMOS logic families. (MAY 2009)

• TTL series and their characteristics

• TTL configurations

• TTL gate circuit

• CMOS characteristics

• CMOS gate circuits

4. Use the Truth table method to prove AB’C+B+BD’+ABD’+A’C = B+C (MAY 2009)

• Truth table

• K’Map Simplification

• Draw the Logic Diagram

5. Determine the minterm and maxterm for the given expression A (A’+B)(A’+B+C)


6.Minimize the following using K map realization and verify the result using Tabular

methods: ∑m(0,2,4,5,6,8,10,14,15) (MAY 2009)


• Draw the Map


DIGITAL ELECTRONICS

7. Draw the circuit diagram of 2 inputs CMOS-NAND gate and explain their operation and

characteristics. What are the different types of TTL gates available? Explain their operation

taking suitable example. (MAY 2009)

• Implementation of CMOS using NAND gate

• CMOS characteristics

• TTL types

� Open collector output

� Totem pole output

� Three state output

8. State and prove Demorgan’s law. (NOV/DEC 2003)

• Demorgan’s law

� (x+y)’ = x’+y’

� (xy)’ = x’ + y’

• Proof

9. Obtain a 4 level NAND network for f(A,B,C,D) = (A’B+C)D+EF (APRIL/ MAY 2004)

• Algebraic manipulation

• Gate implementation

10.Simplify using Tabulation method F(w, x, y, z) = ∑(1,4,6,7,8,9,10,11,15) (MAY 2004)

• Determination of Prime Implicants

• Selection of prime Implicants

11. Reduce the following function using K map f = ABC’+ A’B’C+ABC+AB’C and realize

using NAND gates only.( MAY/JUNE 2006)


• Draw the Map



12. Convert (A+B)(A+C)(B+C’) in to standard POS form. (APRIL/MAY 2008)


13. Find the minimal expression using Tabulation method. (DEC 2008)

F(A,B,C,D) = ∑(1,2,4,8,10,11,12,13,15)



14. Simplify the following functions and draw the logic diagram for the same (DEC 2008)

a) F1 = f(A,B,C) =∑(2,3,7) b) F2= f(A,B,C) =∑(0,1,3)


• Draw the Map


• Draw the logic diagram

DIGITAL ELECTRONICS

15. Simplify the following functions using tabulation method (DEC 2009)

F(A,B,C,D) = ∑m(2,3,7,9,11,13) +∑d(1,10,15)



16. Reduce the following functions using K-Map (DEC 2009)

(a) F = ∑m(0,2,4,5,6,7,8,10,11,12,14,15)

(b) F = π (0, 6, 7, 8, 12, 13, 14, 15)



• Draw the Map


17. a.Find the minimal SOP for the Boolean expression f(w,x,y,z) = ∑m(1,3,4,5,9,10,11)

(MAY2010)

+∑φ (1,10,15) using Quine-Mc Clusky method b.Simplify the expression π (0,

1,4,5,6,8,9,12,13,14) using K-Map



• Draw the Map


18. a. Simplify the following Boolean function (i) sum of products (ii) product of sums

(MAY2010)

F(A,B,C,D) = ∑ (0,1,2,5,8,9,10) and implement the function using gates.


• Draw the Map


b. Realize the following function as (i) multilevel NAND-NAND gate network (ii)

multilevel

NOR-NOR network f =B(A+CD)+A’C


• Realize using gates

19. a. Simplify the expression AB+(AC)’+ABC’(AB+C) b. Obtain canonical SOP form of the

function Y = AB+ACD c. Find the complement of the function F1 = x’yz’+x’y’z and

F2 = x (y ’z’) + yz d. Realize Y = A+BCD using NAND gates. e. Draw the open collector

TTL NAND gate. f. Write the truth table for 3 input OR gate.(MAY 2010)


• Realize using gates

DIGITAL ELECTRONICS

UNIT-II

COMBINATIONAL CIRCUITS

Two marks:

1. What is the truth table? A truth table lists all possible combinations of inputs and the corresponding

outputs.

2. What are the two types of logic circuits for digital systems? Combinational circuits and sequential circuits

3. Define Combinational circuit.(MAY2005)

A combinational circuit consist of logic gates whose outputs at anytime are

determined directly from the present combination of inputs without regard to previous

inputs.

4. Define sequential circuits.(MAY2005) Their outputs are a function of the inputs and the state of memory elements. The state of

memory elements, in turn, is a function of previous inputs.

5. What is a half-adder?(DEC 2009) The combinational circuit that performs the addition of two bits is called a halfadder.

6. What is a full-adder?

The combinational circuit that performs the addition of three bits is called a Fulladder.

7. What is half-subtractor?(DEC2008) The combinational circuit that performs the subtraction of two bits are called a

half-subtractor.

8. What is a full-subtractor? The combinational circuit that performs the subtraction of three bits is called a half-

subtractor.

9. What is Binary parallel adder? A binary parallel adder is a digital function that produces the arithmetic sum of

two binary numbers in parallel.

10. Why parity checker is needed?(DEC 2008) Parity checker is required at the receiver side to check whether the expected parity

is equal to the calculated parity or not. If they are not equal then it is found that the

received data has error.

DIGITAL ELECTRONICS

11. What is meant by parity bit? Parity bit is an extra bit included with a binary message to make the number of 1’s

either odd or even. The message, including the parity bit is transmitted and then checked

at the receiving and for errors.

12. Why parity generator necessary? (DEC 2008)

Parity generator is essential to generate parity bit in the transmitter.

13. What is IC? An integrated circuit is a small silicon semiconductor crystal called a chip

containing electrical components such as transistors, diodes, resistors and capacitors. The

various components are interconnected inside the chip to form an electronic circuit.

14. What are the needs for binary codes?

a. Code is used to represent letters, numbers and punctuation marks.

b. Coding is required for maximum efficiency in single transmission.

c. Binary codes are the major components in the synthesis (artificial generation) of

speech and video signals.

d. By using error detecting codes, errors generated in signal transmission can be detected.

e. Codes are used for data compression by which large amounts of data are transmitted in

very short duration of time.

15. Mention the different type of binary codes? The various types of binary codes are, 1. BCD code (Binary Coded decimal). 2. Self-

complementing code.3. The excess-3 (X’s-3) code.4. Gray code.5 Binary weighted code.6.

Alphanumeric code.7. The ASCII code.8.Extended binary-coded decimal interchange code

(EBCDIC).9. Error-detecting and error-correcting code.10. Hamming code.

16. List the advantages and disadvantages of BCD code? The advantages of BCD code are

a. Any large decimal number can be easily converted into corresponding binary number

b. A person needs to remember only the binary equivalents of decimal number from 0 to 9.

c. Conversion from BCD into decimal is also very easy.

The disadvantages of BCD code are

a. The code is least efficient. It requires several symbols to represent even small numbers.

b. Binary addition and subtraction can lead to wrong answer.

c. Special codes are required for arithmetic operations.

d. This is not a self-complementing code.

e. Conversion into other coding schemes requires special methods.

17. What is meant by self-complementing code? A self-complementing code is the one in which the members of the number

system complement on themselves. This requires the following two conditions to be

satisfied. a. The complement of the number should be obtained from that number by

replacing 1s with 0s and 0s with 1s. b. The sum of the number and its complement should be equal

to decimal 9.Example of a self-complementing code is i. 2-4-2-1 code. ii. Excess-3 code.

DIGITAL ELECTRONICS

18. What is BCD adder?(MAY 2010)

A BCD adder is a circuit that adds two BCD digits in parallel and produces a sum

digit also in BCD.

19. What is Magnitude Comparator?

A Magnitude Comparator is a combinational circuit that compares two numbers,

A and B and determines their relative magnitudes.

20. What is decoder? A decoder is a combinational circuit that converts binary information from ‘n’

input lines to a maximum of 2n unique output lines.

21. What is encoder? A encoder is a combinational circuit that converts binary information from

2n Input lines to a maximum of ‘n’ unique output lines.

22. Define Multiplexing?(DEC 2009) Multiplexing means transmitting a large number of information units over a

smaller number of channels or lines.

23.What is Demultiplexer?(MAY2004) A Demultiplexer is a circuit that receives information on a single line and

transmits this information on one of 2n possible output lines

24..What is code conversion? If two systems working with different binary codes are to be synchronized in

operation, then we need digital circuit which converts one system of codes to the other.

The process of conversion is referred to as code conversion.

25. What is code converter?

It is a circuit that makes the two systems compatible even though each uses a

different binary code. It is a device that converts binary signals from a source code to its

output code. One example is a BCD to Xs3 converter.

26. What do you mean by analyzing a combinational circuit? The reverse process for implementing a Boolean expression is called as analysing

a combinational circuit. (ie) the available logic diagram is analysed step by step and

finding the Boolean function

27. Give the applications of Demultiplexer.

i) It finds its application in Data transmission system with error detection. ii) One simple

application is binary to Decimal decoder.

DIGITAL ELECTRONICS

28. Mention the uses of Demultiplexer. Demultiplexer is used in computers when a same message has to be sent to

different receivers. Not only in computers, but any time information from one source can

be fed to several places.

29. Give other name for Multiplexer and Demultiplexer. Multiplexer is otherwise called as Data selector. Demultiplexer is otherwise called as Data

distributor.

30. What is the function of the enable input in a Multiplexer? The function of the enable input in a MUX is to control the operation of the unit.

31. What is priority encoder? (DEC 2009)

A priority encoder is an encoder that includes the priority function. The operation

of the priority encoder is such that if two or more inputs are equal to 1 at the same time,

the input having the highest priority will take precedence.

32. Can a decoder function as a Demultiplexer?(MAY2004) Yes. A decoder with enable can function as a Demultiplexer if the enable line E is

taken as a data input line A and B are taken as selection lines.

33. List out the applications of multiplexer? The various applications of multiplexer are a. Data routing. b. Logic function generator. c.

Control sequencer. d. Parallel-to-serial converter.

34. List out the applications of decoder? The applications of decoder are a. Decoders are used in counter system. b. They are used in

analog to digital converter. c. Decoder outputs can be used to drive a display system.

35. List out the applications of comparators?

The following are the applications of comparator a. Comparators are used as a part of the

address decoding circuitry in computers to select a specific input/output device for the storage of

data. b. They are used to actuate circuitry to drive the physical variable towards the reference

value. c. They are used in control applications.

36.Why multiplexer is called as Data Selector? (MAY 2010)

Multiplexer is called as Data Selector since it selects one of the many inputs and steers the

information to the output.

DIGITAL ELECTRONICS

37.Write the truth table of 1X4 Demultiplexer. (MAY 2010)

Data input Select inputs Outputs

D S1 S0 Y3 Y2 Y1 Y0

D 0 0 0 0 0 D

D 0 1 0 0 D 0

D 1 0 0 D 0 0

D 1 1 D 0 0 0

38.How does encoder differs from decoder(MAY 2010) An encoder is a digital circuit that performs the inverse operation of decoder.An encoder is

a combinational logic circuit that converts an active input signal in to a coded output signal.

39. Explain the design procedure for combinational circuits The problem definition

Determine the number of available input variables & required O/P variables.

Assigning letter symbols to I/O variables

Obtain simplified Boolean expression for each O/P.

Obtain the logic diagram.

40. What are the two types of logic circuits for digital systems? Combinational and sequential

12 Marks:

1. Draw the logic diagram of 6 bit binary to gray code converter.

• Truth Table for binary to gray code conversion.

• K-map simplification

• Logic circuit implementing the Boolean Expression

2. Implement the following function using 4X1 and 8:1 MUX multiplexer

F(A,B,C)=∑(1,3,5,6)DEC08

• Implementation table

• Multiplexer Implementation

3. Design a BCD adder and explain its operation. MAY/JUNE 2009

• Explanation

• Logic diagram

4. Design a 4 bit carry look-ahead adder and compare its advantages over 4 bit parallel

binary adder. MAY/JUNE 2009

• Basic equations

• Comparison of equations

• Design using twos complement

• Circuit diagram

• 4 bit parallel binary adder

• Comparison

DIGITAL ELECTRONICS

5. Construct a 5X32 decoder with four 3X5 decoders and a 2X4 decoder. Use block diagrams.

NOV/DEC 2006.

• Definition

• Truth table

• Logic Diagram

6. Implement a full adder using two half adders.NOV/DEC 2007

• Truth table



7. Mention the steps involved in the design of digital combinational circuits. MAY 2008

• Determine the number of inputs and outputs and assign a symbol to each.

• Derive the truth table

• Obtain the simplified Boolean functions


8. Design a combinational circuit that detect an error in the representation of a decimal digit

in BCD.NOV/DEC 2008

• Truth table



9. Design a combinational circuit to check for even parity of four bit. A logic 1 output is

required when four bits do not constitute an even parity.NOV/DEC 2008

• Truth table



10. Design a combinational logic circuit that will generate the square of all the combinations

of a 3 bit binary number.NOV/DEC 2005

• Truth table



11. a. Design and explain the working of Full adder.

• Truth table



DIGITAL ELECTRONICS

b. Explain octal to binary Encoder.DEC2009

• Definition

• Truth table

• Logic Diagram

12. Design BCD to EX-3 code converter. DEC2009

• Truth Table for BCD to Excess-3 conversion.

• K-map simplification

• Logic circuit implementing the Boolean Expression

13. a. Design a combinational circuit that performs the arithmetic sum of three input bits and

produces a sum and carry output. b. IC7485 – 4 bit magnitude comparator has A= 1011 and

B = 1001 Determine the outputs (b)Show how to connect <, = and > inputs if it is to be the

least significant stage.MAY2010

• Truth table



14. a. Design a combinational circuit which distributes one input line to eight output lines

based on the select inputs. b. Design a 4- bit Binary to gray code converter. MAY2010

• Truth table



DIGITAL ELECTRONICS

UNIT-III

SEQUENTIAL CIRCUITS

Two marks:

1. What is sequential circuit?(MAY2005) Sequential circuit is a broad category of digital circuit whose logic states depend

on a specified time sequence. A sequential circuit consists of a combinational circuit to

which memory elements are connected to form a feedback path.

2. List the classifications of sequential circuit.

i) Synchronous sequential circuit. ii) Asynchronous sequential circuit.

3. What is Synchronous sequential circuit? A Synchronous sequential circuit is a system whose behavior can be defined from

the knowledge of its signal at discrete instants of time.

4. What is clocked sequential circuits? Synchronous sequential circuit that use clock pulses in the inputs of memory

elements are called clocked sequential circuit. One advantage as that they don’t cause

instability problems.

5. What is called latch?

Latch is a simple memory element, which consists of a pair of logic gates with

their inputs and outputs inter connected in a feedback arrangement, which permits a

single bit to be stored.

6. List different types of flip-flops. i) SR flip-flop ii) Clocked RS flip-flop iii) D flip-flop iv) T flip-flop v) JK flip-flop

vi) JK master slave flip-flop

7. What do you mean by triggering of flip-flop. The state of a flip-flop is switched by a momentary change in the input signal.

This momentary change is called a trigger and the transition it causes is said to trigger the

flip-flop.

8. Mention the different types of triggering. Ans: i. Level Triggering ii. Edge Triggering

9. What is meant by level triggering?

The clock input triggers the flip flop i.e., enables the flip flop.When the clock pulse goes

high,the flip flop is said to be level triggered flip flop.In level triggering the output of the flip-flop

changes state or responds only when the clock pulse is present.

DIGITAL ELECTRONICS

10. What is an excitation table?(MAY2008) During the design process we usually know the transition from present state to

next state and wish to find the flip-flop input conditions that will cause the required

transition. A table which lists the required inputs for a given chance of state is called an excitation

table.

11. Give the excitation table of a JK flip-flop. (DEC2007)

Q(t) Q(t+1) J K

0 0 0 X

0 1 1 X

1 0 X 1

1 1 X 0

12. Give the excitation table of a SR flip-flop.

Q(t) Q(t+1) S R

0 0 0 X

0 1 1 0

1 0 0 1

1 1 X 0

13. Give the excitation table of a T flip-flop.

Q(t) Q(t+1) T

0 0 0

0 1 1

1 0 1

1 1 0

14. Give the excitation table of a D flip-flop. (DEC2007)

Q(t) Q(t+1) D

0 0 0

0 1 1

1 0 0

1 1 1

15. What is a characteristic table? A characteristic table defines the logical property of the flip-flop and completely

characteristic its operation.

16. Give the characteristic equation of a SR flip-flop. Ans: Q(t+1)=S+R’Q

17. Give the characteristic equation of a D flip-flop. Ans: Q(t+1)=D

18. Give the characteristic equation of a JK flip-flop. Ans: Q(t+1)=JQ’+K’Q

19. Give the characteristic equation of a T flip-flop. Ans: Q(t+1)=TQ’+T’Q

DIGITAL ELECTRONICS

20. What is the difference between truth table and excitation table? i) An excitation table is a table that lists the required inputs for a given

change of state. ii) A truth table is a table indicating the output of a logic circuit for various input

states.

19. What is counter?

A counter is used to count pulse and give the output in binary form.

20. What is synchronous counter?(MAY2010) In a synchronous counter, the clock pulse is applied simultaneously to all flipflops.The

output of the flip-flops change state at the same instant. The speed of operation is high compared

to an asynchronous counter.

21. What is Asynchronous counter?

In a Asynchronous counter, the clock pulse is applied to the first flip-flops. The

change of state in the output of this flip-flop serves as a clock pulse to the next flip-flop and so on.

Here all the flip-flops do not change state at the same instant and hence speed is less.

22. What is the difference between synchronous and asynchronous counter?

Sl.No. Synchronous counter Asynchronous counter

1 Clock pulse is applied

Simultaneously

Clock pulse is applied to the first

flip-flop, the change of output is

given as clock to next flip-flop

2 Speed of operation is high Speed of operation is low.

23. Name the different types of counter. a) Synchronous counter

b) Asynchronous counter

i) Up counter ii) Down counter iii) Modulo – N counter iv) Up/Down counter

24. What is up counter?

A counter that increments the output by one binary number each time a clock

pulse is applied.

25. What is down counter?

A counter that decrements the output by one binary number each time a clock

pulse is applied.

26. What is up/down counter?

A counter, which is capable of operating as an up counter or down counter,

depending on a control lead.

27. What is a ripple counter?

A ripple counter is nothing but an asynchronous counter, in which the output of the flip-

flop change state like a ripple in water.

DIGITAL ELECTRONICS

28. What are the uses of a counter? i) The digital clock ii) Auto parking control iii) Parallel to serial data conversion.

29. What is meant by modulus of a counter? By the term modulus of a counter we say it is the number of states through which a counter

can progress.

30. What is meant by natural count of a counter? By the term natural count of a counter we say that the maximum number of states through

which a counter can progress.

31. A ripple counter is a ------------ sequential counter. Ans: Synchronous.

32. What is a modulo counter? A counter that counts from 0 to T is called as modulo counter.

33. A counter that counts from to T is called a modulo counter. True or False. Ans: True

34. The number of flip-flops required for modulo-18 counter is ------- Ans: Five.(DEC2009)

35. What is a ring counter? A counter formed by circulating a ‘bit’ in a shift register whose serial output has

been connected to its serial input.

36. What is BCD counter?

A BCD counter counts in binary coded decimal from 0000 to 1001 and back to

0000. Because of the return to 0000 after a count of 1001, a BCD counter does not have a

regular pattern as in a straight binary counter.

39. What is Johnson counter?

It is a ring counter in which the inverted output is fed into the input. It is also

know as a twisted ring counter.

40. What is a shift register?

In digital circuits, datas are needed to be moved into a register (shift in) or moved

out of a register (shift out). A group of flip-flops having either or both of these facilities is

called a shift register.

41. What is serial shifting? In a shift register, if the data is moved 1 bit at a time in a serial fashion, then the

technique is called serial shifting.

42. What is parallel shifting? In a shift register all the data are moved simultaneously and then the technique is

called parallel shifting.

43. Write the uses of a shift register. i) Temporary data storage ii) Bit manipulations.

DIGITAL ELECTRONICS

44. What is a cycle counter?

A cycle counter is a counter that outputs a stated number of counts and then stops.

45. Define state of sequential circuit? The binary information stored in the memory elements at any given time defines

the “state” of sequential circuits.

46. What is meant by race around condition?(MAY2008) In JK flip-flop output is fed back to the input, and therefore changes in the

output results change in the input. Due to this in the positive half of the clock pulse if

J and K are both high then output toggles continuously. This condition is known as

race around condition.

47. Compare Serial Adder and Parallel Adder.

Sl.No Serial Adder Parallel Adder

1 It uses shift registers It uses register with parallel load

2 It requires only one full adder and

carry flip flop

The number of full adder circuit is equal to the

number of bit of the binary number

3 It is a sequential circuit It is a combinational circuit

48. Shift register can be operated in all possible ways then it is called as----------- (DEC2008) Univerasal register: It can be operated in all possible modes with bidirectional

shift facility.

49. Give the applicatons of flip flops.(DEC2009) The flip flop can be used in Bounce elimination switch, registers,counters and Random

Access Memory(RAM)

50.Define edge triggering.(MAY2010) When the output of flip flop responds to change of state of clock it is called edge

triggering.The change of state from 0 to 1 is known as positive edge and change of state from 1 to

0 is known as negative edge. Based on this edge triggering may be positive edge triggering or

negative edge triggering.

12 Marks:

1.Explain the working of BCD ripple counter with timing diagrams.MAY2010

• BCD Ripple Counter Count sequence

• Truth Table

• State diagram representing the Truth Table

• Truth Table for the J-K Flip Flop

• Block Diagram

DIGITAL ELECTRONICS

2. Explain the parallel load- serial out data transfer operation in a 4 bit shift register.

• Block diagram

• Theoretical explanation

• Logic diagram with D flipflop

• Working

3. Design a 3 bit universal shift register and explain its operation. MAY/JUNE 2009

• Block diagram


• Logic diagram

• Working

4. Design a 3 bit asynchronous ripple counter using T flip flops and explain its

operation.MAY'09

• Asynchronous Ripple Counter Count sequence

• Truth Table


• Truth Table for the T Flip Flop

• Logic Diagram

5. Draw a six stage ring counter and explain its opration.NOV/DEC 2005

• Ring Counter Count sequence

• Truth Table



• Logic Diagram

6. Draw flip flop shift counter, its truth table and waveforms. Explain its operation as a

decade counter. NOV/DEC 2005

• Decade Counter Count sequence

• Truth Table



• Logic Diagram

7.Explain the working of master slave JK flip flop. State its merit.MAY/JUN 2006

• Block diagram


• Logic diagram

• Working

• Advantages

DIGITAL ELECTRONICS

8.Draw the four bit Johnson counter and explain the operation. NOV/DEC 2006

• Johnson Counter Count sequence

• Truth Table


• Construction of Johnson counter using D Flip Flop

• Logic Diagram

9.Design a sequence detector to detect the sequence 1010 using the state diagram and state

table. APRIL/MAY 2008

• Construct state diagram

• Obtain the flow table

• Obtain the flow table & output table

• Transition table

• Select flip flop

• Excitation table

• Logic diagram

10.Design and explain the working of mod 7 up down counter.NOV/DEC 2007

• Mod 7 up down Counter Count sequence

• Truth Table



• Logic Diagram

11. Design and explain the working of up – down counter. DEC 2008

• Up - down Counter Count sequence

• Truth Table



• Logic Diagram

12.a.With neat diagram explain the SR flip flop.DEC 2009

b.Define i) Edge triggering ii) Level triggering

• Logic Diagram

• Graphical Symbol

• Characteristics table

• Characteristics equation

• Excitation Table

• Triggering

� Edge triggering

� Level triggering

o

DIGITAL ELECTRONICS

13. a.Discuss in detail about JK flip flop with its truth table, state diagram and

characteristics equation

• State diagram

• Excitation State table

• Truth table

• Characteristics

• Logic diagram

b.Realize Trigger flip flop using SR flip flop.DEC 2009

• Logic Diagram

• Graphical Symbol

• Characteristics table

• Characteristics equation

• Excitation Table

14. Explain in detail about serial in parallel out shift register.MAY 2010

• Block diagram


• Logic diagram

• Working

DIGITAL ELECTRONICS

UNIT -IV

MEMORY DEVICES

Two marks:

1. List the types of ROM.

i) Programmable ROM (PROM) ii) Erasable ROM (EPROM) iii) Electrically Erasable

ROM (EEROM)

2. Differentiate ROM & PLD’s

ROM (Read Only Memory) PLD’s (Programmable Logic Devices)

It is a device that includes both the decoder and

the OR gates with in a single IC package

It is a device that includes both AND

and OR gates with in a single IC package

ROM does not full decoding of the

variables and does generate all the minterms

PLD’s does not provide full decoding of

the variable and does not generate all the

minterms

3. What are the types of arrays in RAM?

RAM has two type of array namely, a. Linear array b. Coincident array

4. Explain DRAM?(MAY2010) The dynamic RAM (DRAM) is one which stores the binary

information in the form of electric charges on capacitors. The capacitors are provided inside the

chip by MOS transistors.

5. Explain SRAM? (MAY2010)

Static RAM (SRAM) consists of internal latches that store the binary

information. The stored information remains valid as long as the power is applied to

the unit. SRAM is easier to use and has shorter read and write cycle. The memory capacity of a

static RAM varies from 64 bit to 1 mega bit.

6. Differentiate volatile and non-volatile memory?(DEC2011)

Volatile memory Non-volatile memory

They are memory units which lose stored

information when power is turned off.

E.g. SRAM and DRAM

It retains stored information when power is

turned off.

E.g. Magnetic disc and ROM

7. What is meant by memory decoding?(DEC2008) The memory IC used in a digital system is selected or enabled only for the

range of addresses assigned to it .

8.Draw the basic configuration of PAL.

inputs outputs

Programmable

AND

Array

Fixed

OR Array

DIGITAL ELECTRONICS

9. Draw the basic configuration of PLA.(DEC2009)

10. List the types of semiconductor memories. 1.Random Access Memory(RAM) 2.Read Only Memory(ROM)

11. List the different types of RAM.

1.NMOS RAM 2.CMOS RAM 3. Schottky TTL RAM 4.ELL RAM

12. What are the terms that determine the size of a PAL? The size of a PAL is specified by the

a. Number of inputs b. Number of products terms c. Number of outputs

13. What are the advantages of RAM?(DEC2009) The advantages of RAM are a. Non-destructive read out b. Fast operating speed

c. Low power dissipation d. Compatibilitye. Economy.

14. What is access and cycle time? The access time of the memory is the time to select word and read it. The cycle time of a

memory is a time required to complete a write operation.

15. Explain RAM.(DEC2011) RAM has the basic unit called binary cell. The binary cell can store 0 or 1 indefinitely as

long as power is ON. Data can be written in to RAM as well as read out from RAM. The

previously stored data can be erased and new data can be written in to RAM. Hence it is called

READ/WRITE memory. When power supply is switched OFF all the binary cells are erased.

16. What is memory enable? Memory enable(sometimes called chip select) is a control input, which is used to enable the

particular memory in multichip implementation of a large memory. When the memory enable is

inactive, the memory chip is not selected and no operation is performed. When the memory enable

input is active, the read/write input determines the operation to be performed.

inputs outputs

Programmable

AND Array

Programmable

OR Array

DIGITAL ELECTRONICS

17. What is the procedure followed to store a new word in memory?(DEC2008) a. Apply the binary address of the desired word to the address line. b. Apply the data bits

that must be stored in memory to the data input lines. c. Activate the write input: The memory unit

will then take the bits from the input data lines and store them in the word specified by the address

lines.

18. What is the procedure followed to take a word out of memory? a. Apply the binary address of the desired word to the address lines.

b. Activate the read inputs.

19. List out the advantages and disadvantages of dynamic RAM cell. Advantages: It’s very simple thus allowing very large memory arrays to be constructed on

a chip at a lower cost per bit than in static memories.

Disadvantages: The storage capacitor can not hold its charge over an extended period of

time and will lose the stored data bit unless its charge is refreshed periodically .This process of

refreshing requires additional circuitry and complicates the operation of dynamic RAM.

20.What is cross point in ROM?

In ROM the programmable intersection between two lines is called a cross point. It’s

logically equivalent to a switch that can be altered to either be close or open.

21. List out the different methods by which a ROM can be programmed.

a. Mask programming b. PROM c. EPROM d. EEPROM

22. Compare PROM and EPROM.(MAY2010)

PROM EPROM

PROM once programmed, the fixed

pattern is permanent and can not be

altered.

EPROM can be restructured to the initial

state, even though it has been programmed

previously.

23.What are the steps undertaken for implementing a circuit with a PLA?

a. To reduce the number of distinct product terms as a PLA has a finite number of

AND gates. This can be done by simplifying Boolean functions to a minimum number of

terms. b. The true and complement of each function should be simplified to find which one

can be expressed with fewer product terms and which one provides product terms that are

common to other functions.

24. List the several devices that can be used to solve very complicated logic problems. 1.ROM 2.PROM 3.PAL 4.Gate Arrays 5.Programmable Gate Arrays.

25. What is a software and a firmware?

A computer program is typically referred to as software. When a computer program is

stored in ROM, it’s called as firmware.

DIGITAL ELECTRONICS

26. What are the advantages of RAM? a. Non-Destructive read out. b. Fast operating speed. c. Low power dissipation.

d. Compatibility.

27. Define memory Expansion. Memory IC’s can be connected together to expand the number of memory words or

the number of bits per word.

28. List basic types of programmable logic devices. . Read only memory

. Programmable logic Array

. Programmable Array Logic

29. Explain ROM

A read only memory(ROM) is a device that includes both the decoder and the OR

gates within a single IC package. It consists of n input lines and m output lines. Each bit

combination of the input variables is called an address. Each bit combination that comes out

of the output lines is called a word. The number of distinct addresses possible with n input

variables is 2n.

30. Define address and word: In a ROM, each bit combination of the input variable is called on address. Each bit

combination that comes out of the output lines is called a word.

31. State the types of ROM . Masked ROM.

. Programmable Read only Memory

. Erasable Programmable Read only memory.

. Electrically Erasable Programmable Read only Memory.

32. What is programmable logic array? How it differs from ROM? In some cases the number of don’t care conditions is excessive, it is more economical

to use a second type of LSI component called a PLA. A PLA is similar to a ROM in concept;

however it does not provide full decoding of the variables and does not generates all the

minterms as in the ROM.

33. Which gate is equal to AND-invert Gate? NAND gate.

34.Which gate is equal to OR-invert Gate?

NOR gate.

44. Bubbled OR gate is equal to-------------- NAND gate

45. List the major differences between PLA and PAL

DIGITAL ELECTRONICS

PLA:

Both AND and OR arrays are programmable and Complex

Costlier than PAL

PAL

AND arrays are programmable OR arrays are fixed

Cheaper and Simpler

12 Marks:

1.Give the classification of semiconductor memories.MAY/JUNE 2009

• Introduction of semiconductor memory

• Classification

� RAM - SRAM ,DRAM

� ROM – PLD, PAL, FPGA

2.Write a short notes on EPROM and EEPROM. MAY/JUNE 2009 PG NO:657

• ROM

• Third type of ROM

� EPROM

• Fourth type of ROM

� EEPROM

• Advantage

• Application

3.Compare Static RAMs and Dynamic RAMs .MAY/JUNE 2009/DEC2009 PG NO:646

• Comparison in terms of:

� Construction

� Stored charge

� Power consumption

� Read and write cycles

4.Explain the read cycle and write cycle timing parameters with the help of timing diagrams.

• Introduction about read and write cycle

• Timing parameters

� Steps for writing a data

� Steps for reading a data

• Timing diagram

• Explanation

5.Implement the following function using PLA. DEC2011

F1= ∑m(3,5,7) F2 = ∑m(4,5,7)

• PLA programming table

• K map simplification

• PLA construction

DIGITAL ELECTRONICS

6. Draw the block diagram of a PLA device and briefly explain each block. MAY 2008 PG

NO:650

• PLA Structure

• PLA with three inputs, four product terms and two outputs


7. Write short notes on Field Programmable Gate Arrays (FPGA). MAY 2008 PG NO:646

• Introduction

• Internal configurations

• Performance

• Applications

8. Write short notes on Memory Decoding. NOVEMBER/DECEMBER 2009

• Internal construction

• Coincident decoding

• Address multiplexing

9. Illustrate the concept of 16X8 bit ROM array with diagram. NOVEMBER/DECEMBER

2006

• ROM block diagram

• Internal logic of a 16*8 ROM

• Programming of ROM

• Combinational circuit implementation

10. Obtain the PLA program table with only 7 product terms for a BCD to Excess 3 code

Converter. Also give the fuse map. NOVEMBER/DECEMBER 2006

• PLA Structure

• PLA with 7 product terms


• Fuse map

11. Implement the following function using PLA. NOVEMBER/DECEMBER 2005

F1(x, y, z)= ∑m(1,2,4,6);F2(x, y, z) = ∑m(0,1,6,7); F3 (x, y, z) =∑m(2 ,6)

• PLA Structure

• Simplification


12. What is PAL? Show how a PAL is programmed for the following logic function X =

AB’C+A’BC’+A’B’+AC. DEC2008

• Introduction

• Boolean functions - Simplification of min terms

• Similar to PLA

• Fuse map

DIGITAL ELECTRONICS

13.With neat diagram explain the RAM organization.DEC2011

• Introduction

• Write and read operation

• Memory description

• Timing waveform

• Types of Memory

� SRAM

� DRAM

14.a. Show how a PAL is programmed for the following 3 variable logic function MAY2010

X= A’BC’+AB’C’+A’B+AC

• Boolean functions - Simplification of min terms

• Similar to PLA

• Fuse map

b.Implement the following functions using 3X4X2 PLA

f1(a,b,c) = ∑m(1,2,3,6) f2(a,b,c) = ∑m(0,1,3,6,7)

• Simplification of min terms

• Similar to PLA

• Fuse map

DIGITAL ELECTRONICS

UNIT-V

SYNCHRONOUS AND ASYNCHRONOUS SEQUENTIAL CIRCUITS

Two marks:

1. Define state of sequential circuit?

The binary information stored in the memory elements at any given time defines

the “state” of sequential circuits.

2. Define state diagram.

A graphical representation of a state table is called a state diagram.

3. What is the use of state diagram?(DEC2007) i) Behavior of a state machine can be analyzed rapidly. ii) It can be used to design a

machine from a set of specification.

4. What is state table? A table, which consists time sequence of inputs, outputs and flip-flop states, is

called state table. Generally it consists of three section present state, next state and output.

5. What is a state equation? A state equation also called, as an application equation is an algebraic expression

that specifies the condition for a flip-flop state transition. The left side of the equation

denotes the next state of the flip-flop and the right side; a Boolean function specifies the

present state.

6. What is flow table? During the design of synchronous sequential circuits, it is more convenient to name the

states by letter symbols without making specific reference to their binary values. Such table is

called Flow table.

7. What is primitive flow table?(DEC 2005)

A flow table is called Primitive flow table because it has only one stable state in each row.

8. Define race condition.(DEC2008) A race condition is said to exist in a synchronous sequential circuit when two or more

binary state variables change, the race is called non-critical race.

9. Define critical & non-critical race with example.(DEC2007) The final stable state that the circuit reaches does not depend on the order in

which the state variables change, the race is called non-critical race.

The final stable state that the circuit reaches depends on the order in which the

state variables change, the race is called critical race.

DIGITAL ELECTRONICS

10. How can a race be avoided?(DEC2009)

Races can be avoided by directing the circuit through intermediate unstable states with a

unique state – variable change.

11. Define cycle and merging?

When a circuit goes through a unique sequence of unstable states, it is said to have a cycle.

The grouping of stable states from separate rows into one common row is called merging.

12. Give state – reduction procedure.

The state – reduction procedure for completely specified state tables is based on the

algorithm that two states in a state table can be combined in to one if they can be shown to be

equivalent.

13. Define hazards.(MAY2008) Hazards are unwanted switching transients that may appear at the output of a

circuit because different paths exhibit different propagation delays.

14. Does Hazard occur in sequential circuit? If so what is the problem caused? Yes, Hazards occur in sequential circuit that is Asynchronous sequential circuit. It may

result in a transition to a wrong state.

15. Give the procedural steps for determining the compatibles used for the purpose of

merging a flow table.

The purpose that must be applied in order to find a suitable group of compatibles for the

purpose of merging a flow table can be divided into 3 procedural steps. i. Determine all compatible

pairs by using the implication table. ii. Find the maximal compatibles using a Merger diagram iii.

Find a minimal collection of compatibles that covers all the states and is closed.

16. What are the types of hazards?

The 3 types of hazards are 1) Static – 0 hazards 2) Static – 1 hazard 3) Dynamic hazards

17.What is mealy and Moore circuit? Mealy circuit is a network where the output is a function of both present state and input.

Moore circuit is a network where the output is function of only present state.

18.How can the hazards in combinational circuit be removed? Hazards in the combinational circuits can be removed by covering any two

min terms that may produce a hazard with a product term common to both. The

removal of hazards requires the addition of redundant gates to the circuit.

19.How does an essential hazard occur?(MAY2011)

An essential hazard occurs due to unequal delays along two or more paths that originate

from the same input. An excessive delay through an inverter circuit in

comparison to the delay associated with the feedback path causes essential hazard.

DIGITAL ELECTRONICS

20.What is Timing diagram?

Timing diagrams are frequently used in the analysis of sequential network. These

diagrams show various signals in the network as a function of time.

21.Define equivalent state.

If a state machine is started from either of two states and identical output

sequences are generated from every possible set of sequences, then the two states are said

to be equivalent.

22.Define state reduction algorithm. State reduction algorithm is stated as “Two states are said to be equivalent if, for each

member of the set of inputs they give the same output and send the circuit either to the same state

or to an equivalent state. When two states are equivalent, one of them can be removed without

altering the input-output relation.

23. What is meant by flow table?(DEC 2011) During the design of asynchronous sequential circuits, it is more convenient to

name the states by letter symbols without making specific reference to their binary

values. Such a table is called a flow table.

24. What are the problems involved in asynchronous circuits?

The asynchronous sequential circuits have three problems namely,

a. Cycles b. Races c. Hazards

25. Define cycles? (DEC2007)

If an input change includes a feedback transition through more than unstable

state then such a situation is called a cycle.

26. Define primitive flow table?

A primitive flow table is a flow table with only one stable total state in each.

27. Give the comparison between synchronous & Asynchronous sequential circuits?

Synchronous sequential circuits Asynchronous sequential circuits.

Memory elements are clocked flip-

flops

Memory elements are either

unlocked flip -

flops or time delay elements.

Easier to design More difficult to design

DIGITAL ELECTRONICS

28. The following wave forms are applied to the inputs of SR latch. Determine the Q

waveform Assume initially Q = 1

Here the latch input has to be pulsed momentarily to cause a change in the latch

output state, and the output will remain in that new state even after the input pulse is over.

29. The t pd for each flip-flop is 50 ns. Determine the maximum operating frequency for

MOD - 32 ripple counter f max (ripple) = 5 x 50 ns = 4 MHZ

30. Give the comparison between synchronous & Asynchronous counters.

Asynchronous counters Synchronous counters

In this type of counter flip-flops are

connected in such a way that output of 1st

flip-flop drives the clock for the next flipflop.

In this type there is no connection between

output of first flip-flop and clock input of

the next flip - flop

All the flip-flops are Not clocked

simultaneously

All the flip-flops are clocked

simultaneously

31. What are the steps for the design of asynchronous sequential circuit? -construction of primitive flow table

-reduction of flow table

-state assignment is made

-realization of primitive flow table

32. Write a short note on fundamental mode asynchronous circuit.

Fundamental mode circuit assumes that. The input variables change only when the

circuit is stable. Only one input variable can change at a given time and inputs are levels and

not pulses.

33.Write a short note on pulse mode circuit. Pulse mode circuit assumes that the input variables are pulses instead of level. The

width of the pulses is long enough for the circuit to respond to the input and the pulse width

must not be so long that it is still present after the new state is reached.

DIGITAL ELECTRONICS

34. A pulse mode asynchronous machine has two inputs. If produces an output whenever

two consecutive pulses occur on one input line only. The output remains at 1 until a pulse has

occurred on the other input line. Write down the state table for the machine.

Present

State

Next State Output

Z X Y

A B C 0

B D C 0

C B E 0

D D A 1

E A E 1

35. What is fundamental mode.

A transition from one stable state to another occurs only in response to a change in the

input state. After a change in one input has occurred, no other change in any input occurs

until the circuit enters a stable state. Such a mode of operation is referred to as a fundamental

mode.

12 Marks:

1. Write an explanatory note on derivation of ASM charts and realization of ASM

charts.DEC’ 03

• Introduction

• ASM basic elements

� Chart state box

� Decision box

� Conditional box

• ASM block

• Timing consideration

• ASMD chart

2. Find a static and dynamic hazard free realization for the following function using NAND

and NOR gates. F(a, b, c, d) = ∑m(1,5,7,14,15) APRIL/MAY 2011

• K’Map simplification

• Create Hazard free link

� Static hazard

� Dynamic hazard

3. Explain races and hazards with suitable examples. APRIL/MAY 2010 PG NO:450

• Basics of races

• Problem created due to races

• Classification of races

DIGITAL ELECTRONICS

• Remedy for races

• Cycles

• Classification of hazards

• Static hazard & Dynamic hazard definitions

• K map for selected functions

• Method of elimination

• Essential hazards

4. Design an asynchronous sequential circuit that has two internal states and one output.The

excitation and output function describing the circuit are as follows.

Y = x1x2 + x1y2+x2y1 Y = x2 + x1y1y2+ x1y1 Z = x2 + y1

• Obtain the state diagram


• Using implication table reduce the flow table

• Using merger graph obtain maximal compatibles

• Verify closed & covered conditions

• Plot the reduced flow table

• Obtain transition table


• Logic diagram

5. What is meant by hazard free digital circuits? How the same can be realized? Explain with

an example.MAY/JUNE 2009



� Static hazard

� Dynamic hazard

• Example

6. Discuss a method used for race free assignments with example. MAY/JUNE 2011

• Design a primitive flow table

• Reduce the flow table by merging the rows

• Make a race-free binary state assignment

• Obtain the transition table and output map

• Obtain the logic diagram, using SR latches

7. Design a pulse mode circuit with three inputs x1, x2, x3 and one output z. The output z

should change from 0 to 1, only for the input sequence x1-x2-x3.Also the output z should

remain in 1 until x2 occurs. Use SR flip flop for the design. MAY/JUNE 2009

• Design a primitive flow table

• Reduce the flow table by merging the rows

• Make a race-free binary state assignment

• Obtain the state table and output map

• Obtain the logic diagram, using SR latches

DIGITAL ELECTRONICS

8. The circuit has two inputs T (Toggle) and C(Clock) and one output Q. The output state is

complemented if T =1 and clock C changes from 1 to 0 (Negative edge triggering) otherwise,

under the primitive flow table and implication table.









• Logic diagram

9. As asynchronous sequential circuit is described by the following excitation and output

function y = x1x2+(x1+x2)y z = y i) Draw the logic diagram of the circuit and

describe the behaviour of the circuit. ii) Derive the transition table and output map.

DEC2008









• Logic diagram

10. i)What is Hazard? Explain its types ii) Give the hazard free realization for the following

Boolean function F(A,B,C,D) =∑m(0,2,6,7,8,10,12) DEC2008

• Explain Static Hazard

• Explain Dynamic Hazard



11.a.Design a sequence detector that produces an output 1 whenever the non overlapping

sequence 1011 is detected.b.Write a verilog code for half adder.MAY2011







• Logic diagram

• Verilog code

DIGITAL ELECTRONICS

12.a. Define races and explain its types. b. Define the following i) cycles ii) Hazards DEC2009

PG NO:449

• Basics of races




• Cycles






DIGITAL ELECTRONICS

UNIVERSITY QUESTION PAPER

APRIL/MAY 2008

PART A

1. Find the complement of F=WX+YZ, then show that FF’=0.

F = W*X + Y*Z

~F = ~ (W*X + Y*Z)

~ (W*X + Y*Z) = ~(W*X) * ~(Y*Z)

~(WnX) = ~W + ~X and that ~(Y*Z) = ~Y + ~Z

~F = (~W + ~X) * (~Y + ~Z)

So FF’= (W*X + Y*Z) * ((~W + ~X) * (~Y + ~Z))

FF =0.

2. Convert (AB+C)(B+C’D) into sum of products form. (AB+C)(B+C'D)

=(A+C)(B+C)(B+C')(B+D)

=(A+C)(B)(B+D)

=(A+C)(B)(1+D)

=B(A+C)

3. Show that the positive logic NAND gate is negative logic NOR gate.

A NAND gate (positive logic 1s) is a Negative OR gate (negative logic 0s) and a NOR gate

is a negative AND. DeMorgan's Theorem can be used. (NAND BAR (A • B) = BAR A +

BAR B), which converts AND's to OR's and vice versa.

4. Simplify F = ∑(1,4,5,6,7,13) using K-map. F = ∑(1,4,5,6,7,13)

F = m1 = m4 + m5 + m6 + m7 + m13

F = w’x’y’z + w’xy’z’ + w’xy’z + w’xyz’ + w’xyz + wxy’z

DIGITAL ELECTRONICS

F = w’x + xy’z + w’y’z

5. Draw the CMOS logic circuit for NOR gate.

6. Implement a full adder using two half adder.

7. Write the principle of carry look ahead logic. In ripple carry adders, the carry propagation time is the major speed limiting factor.Most

other arithmetic operations, e.g. multiplication and division are implemented using several

add/subtract steps. Thus, improving the speed of addition will improve the speed of all

other arithmetic operations. Accordingly, reducing the carry propagation delay of adders is

of great importance. Different logic design approaches have been employed to overcome

the carry propagation problem.

One widely used approach employs the principle of carry look-ahead solves this problem

by calculating the carry signals in advance, based on the input signals.

DIGITAL ELECTRONICS

8. Differentiate between decoder and demultiplexer. A decoder takes n inputs and produces 2^n outputs. An encoder takes 2^n inputs and

produces n outputs.

A multiplexer selects one line from many lines. The inverse of selection is distribution. A

demux essentially transmits data from one line line to 2^n possible output lines. The output

line is determined by n select lines. In short, a multiplexer selects an input line, a

demultiplexer selects an output line.

The differences between these two circuits is that, a demux simply selects an output line. A

decoder takes n inputs, and uses those inputs to determine which of the 2^n output lines is

high.

9. Implement F(X,Y,Z) = ∑(1,2,6,7) using 4*1 multiplexer.

Step 1: Find the truth table for the function, and group the rows into pairs. Within each pair

of rows, x and y are the same, so f is a function of z only.

a. When xy=00, f=z

b. When xy=01, f=z’

c. When xy=10, f=0

d. When xy=11, f=1

Step 2: Connect the first two input variables of the truth table (here, x and y) to the select

bits S1 S0 of the 4-to-1 mux.

Step 3: Connect the equations above for f(z) to the data inputs D0-D3

• The basic setup is to connect two of the input variables (usually the first two in the truth

table) to the mux select inputs.

x y z f

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 0

1 0 0 0

1 0 1 0

1 1 0 1

1 1 1 1

X Y Z C

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 1

DIGITAL ELECTRONICS

With S1=X and S0=Y, then

Q=X’Y’D0 + X’YD1 + XY’D2 + XYD3

Equation for the multiplexer

10. State the difference between a latch and a flip flop. Latches and flip-flops are the basic elements for storing information. One latch or

flip-flop can store one bit of information. The main difference between latches and flip-

flops is that for latches, their outputs are constantly affected by their inputs as long as the

enable signal is asserted. In other words, when they are enabled, their content changes

immediately when their inputs change. Flip-flops, on the other hand, have their content

change only either at the rising or falling edge of the enable signal. This enable signal is

usually the controlling clock signal. After the rising or falling edge of the clock, the flip-

flop content remains constant even if the input changes.

flip flop: -> it work's on the basis of clock pulses.

-> it is a edge trigerred , it mean that the output and the next state input changes when there

is a change in clock pulse whether it may a +ve or -ve clock pulse.

latch; -> it is based on enable function input

-> it is a level trigerred , it mean that the output of present state and input of the next state

depends on the level that is binary input 1 or 0.

11. Design a T-flip flop from D- flip flop.

12. Write the design procedure for designing a synchronous sequential circuit.

• Derive a state diagram for the circuit

• Reduce the number of states if necessary

• Assign binary values to the states

• Obtain the binary coded state table

• Choose the type of flip flops to be used

• Derive the simplified flip flop input equations and output equations

• Draw the logic diagram

DIGITAL ELECTRONICS

13. Sketch the timing signals for a 4-bit ring counter.

14. What is random access memory?

RAM has the basic unit called binary cell.The binary cell can store 0 or 1 indefinitely as

long as power is ON.Data can be written in to RAM as well as read out from RAM.The

previously stored data can be erased and new data can be written in to RAM.Hence it is

called READ/WRITE memory.When power supply is switched OFF all the binary cells are

erased.

15. What is the need for address multiplexing?

On block transfers, can use address lines to also send data after first word -- double data

rate Or can always send address, then data on same lines (fewer wires) Requires

multiplexing logic on each end and introduces some delay

16. State the importance of FPGA.

FPGAs provide a great deal of flexibility. Today's FPGAs, from companies such as Altera

and Xilinx, use cutting edge 45-nm silicon technology and offer a wide array of speeds and

capacity options. They also offer high speed PCI Express interfaces embedded into the

FPGA silicon, making them a perfect fit for PCI

17. Calculate the number of address lines and data lines for 2G byte memory. 2G = 2 × 230 = 21 × 230 = 231, so 2G x 32 takes 31 address lines and 32 data lines, for

a total of 63 I/O lines.

18. Draw the ASM chart for binary multiplexer.

DIGITAL ELECTRONICS

DIGITAL ELECTRONICS

19. Define hazards in sequential circuits. Hazards are unwanted switching transients that may appear at the output of a


20. Design a transition table for a pulse mode sequential circuit to generate an output

only when a second pulse occurs.

PART B

21. Minimize the switching function F(W,X,Y,Z) = ∑(0,5,7,8,9,10,11,14,15) using Quine-

McCluskey method and also implement the simplified function using NAND gates.

• Simplification of min terms


• Implementation using NAND gates.

22. a. Design a four bit parity checker and generator.

• Even parity checker truth table

• Logic diagram of parity checker and generator

• Implementation of parity checker with EX-OR gates

b. Design a single bit magnitude comparator.

• Introduction

• Algorithm

• Logic diagram

• Application

DIGITAL ELECTRONICS

23. Design a combinational circuit that converts a four bit gray code to four bit binary

number.

• Truth table



24. With neat circuit diagram and its waveforms, explain the concept of Master Slave JK-

flip flop.

• State diagram


• Truth table

• Characteristics

• Logic diagram

25. A sequential circuit has two JK flip flops A and B, two inputs x and y, and one output z.

The flip flop input equations and circuit output equation are,

JA = Bx + B’y’ KA = B’xy’

JB = A’x KB = A + xy’

z = Ax’y’ + Bx’y’

a) Tabulate the state table.

b) Derive the state equations for A and B.

• State diagram


• State equations

• Truth table

• Characteristics

• Logic diagram

26. Briefly explain about the various types of ROM and RAM cells.


• Classification


� ROM – PLD, PAL, FPGA, EPROM, EEPROM

27. a. Find a static hazard free circuit for the Boolean function F(A,B,C,D) =

∑(0,2,6,7,8,10,12)



� Static hazard

� Dynamic hazard

DIGITAL ELECTRONICS

b. Implement the following Boolean functions with a PLA.

F1 = ∑(0,1,2,4), F2 = ∑(0,5,6,7), F3 = ∑(0,3,5,7)



• PLA construction

28. Design a 4bit universal shift register.

• Block diagram


• Logic diagram

• Working

DIGITAL ELECTRONICS

ANNA UNIVERSITY COIMBATORE

080290010- DIGITAL ELECTRONICS- MAY/JUNE-2010

PART-A

1. What are the applications of a Boolean algebra?

Boolean algebra as the calculus of two values is fundamental to digital logic, computer

programming, and mathematical logic, and is also used in other areas of mathematics such

as set theory and statistics.

2. Reduce AB + (AC)' + AB’C (AB + C)

AB + (AC)' + AB’C (AB + C)

= AB + (AC)' + AAB'BC + AB'CC

= AB + (AC)' + AB'CC [A.A' = 0]

= AB + (AC)' + AB'C [A.A = 1]

= AB + A' + C' =AB'C [(AB)' = A' + B']

= A' + B + C' + AB'C [A + AB' = A + B]

= A' + B'C + B + C' [A + A'B = A + B]

= A' + B + C' + B'C

=A' + B + C' + B'

=A' + C' + 1

= 1 [A + 1 =1]

3. State demorgans theorem and obtain the canonical SOP form the function Y = AC +

AB + BC?

De Morgan suggested two theorems that form important part of Boolean algebra.

They are, 1) The complement of a product is equal to the sum of the complements.

(A.B)' = A'+B' 2) The complement of a sum term is equal to the product of the complements.

(A+B)' = A'.B'

Y = AC + AB + BC

=AC (B + B’) + AB (C + C’) + (A + A') BC

=ABC + ABC' + AB'C + AB'C' + ABC + ABC' + ABC

=ABC + ABC' +AB'C + AB'C' [A + A =1]

=m7 + m6 +m5 +m4

= ∑m (4, 5, 6, 7)

DIGITAL ELECTRONICS

4. Find the complement of the functions F1 = x'yz' + x'y'z and F2 = x (y'z' + yz).

F1' = (x'yz' + x'y'z)'

= (x'yz')'(x'y'z)'

= (x + y' + z) (x + y +z')

F2' = [x (y'z' + yz)]'

= x' + (y'z' + yz)'

= x' + (y'z')'(yz)'

= x' + (y + z) (y' + z')

5. Write truth table of 3 inputs or gate?

A B C OUTPUT

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 1

1 0 0 1

1 0 1 1

1 1 0 1

1 1 1 1

6. Prove A+BC=(A+B)(A+C)

=AA+AB+AC+BC

= A+AB+AC+BC

DIGITAL ELECTRONICS

= A(1+B)+AC+BC

=A+AC+BC

=A(1+C)+BC

=A+BC

7. Distinguish between decoder and encoder?

S.N

o Decoder Encoder

1 One of the input lines is activated

corresponding to the binary input

The input lines generate the binary code,

corresponding to the input value

2 Input of the decoder is an encoded information

presented as ‘n’ input producing 2n possible

outputs.

Input of the encoder is a decoded

information presented as ‘2n’ inputs

producing ‘n’ outputs.

3 The input code generally has a fewer bits than

the output code.

The input code generally has more bits

than the output code.

4

8. Why multiplexer is called as a data selector? Draw the block diagram?

A multiplexer is a digital switch which allows digital information from several sources to be

routed into a single output line.

The basic multiplexer has several data-input lines and a single output line. The

selection of a particular input line is controlled by a set of selection lines. So it is called as a

data selector. Normally there are 2n input lines and n selection lines.

DIGITAL ELECTRONICS

9. Differentiate static RAM and dynamic RAM?

S.No Static RAM Dyanamic RAM

1 It contains less memory cells per

unit area.

It contains more memory cells per unit

area.

2 Its access time is less, hence faster

memories. Its access time is greater than static RAM

3 It consists of number of flip-flops.

Each flip-flop stores one bit.

It stores the data as a charge on the

capacitor. It consists of MOSFET and

capacitor for each cell.

4 Refreshing circuitry is not required.

Refreshing circuitry is required to maintain

the charge on the capacitors every time

after every few milliseconds. Extra

hardware is required to control refreshing.

This makes system design complicated.

5 Cost is more Cost is less.

10. Write notes on dynamic hazards?

Hazards are unwanted switching transients that may appear at the output of a


When the output changes three or more times when it should change from 1 to 0 or from

0 to 1 is known as dynamic hazard.

DIGITAL ELECTRONICS

11. What is synchronous counter?

In a synchronous counter, the clock pulse is applied simultaneously to all flip-flops. The

output of the flip-flops changes state at the same instant. The speed of operation is high compared

to an asynchronous counter.

12. What is BCD adder?

A BCD adder is a circuit that adds two BCD digits in parallel and produces a sum digit also

in BCD.

13. Explain masked ROM.

In masked ROM, mask programming is done by the manufacturer during the last

fabrication process of the unit. The procedure for fabricating a ROM requires that the customer fill

out the truth table, the ROM is to satisfy.

14. Draw the block diagram of D flip-flop using SR –flip-flop?

Input Present state Next state Flip-Flop Inputs

D Qn Qn+1 S R

0

0

1

1

0

1

0

1

0

0

1

1

0

0

1

x

x

1

0

0

DIGITAL ELECTRONICS

15. Draw the open collector TTL NAND gate?

16. Draw the D flip-flop using NAND gate?

DIGITAL ELECTRONICS

17. Define edge triggering? Edge triggering is when the flip-flop state is changed as the rising or falling edge of a clock signal

passes through a threshold voltage. This true dynamic clock input is insensitive to the slope or time

spent in the high or low state.

18. Give any two applications PLA?

• One application of a PLA is to implement the control over a data path. It defines various

states in an instruction set, and produces the next state.

• PLAs that are embedded in more complex and numerous integrated circuits such as

microprocessors

19. Write the truth table of 1 to 8 demultiplexer?

20.What is the minimum number of flip-flops needed to build a counter of modulus- 8?

2n ≥ N

23 ≥ 8

Therefore, three flip-flops are required.

DIGITAL ELECTRONICS

PART-B

ANSWER ANY FIVE QUESTIONS

21. find the minimal sum of products for the Boolean expression

f(w,x,y,z)=∑(1,3,4,5,9,10,11)+∑(6,8) using quine-mc cluskey method?

• List all minterms in the binary form

• Arrange minterms according to categories of 1 in a table

• Compare each binary number with every term in the next higher category and ifthey differ

only one position put a check mark and copy the term in the nextcolumn with a – in the

position that they differed.

• Continue the process until no further elimination of literals

• List the prime implicants

• Select the minimum number of prime implicant

22. simplify the expression pi(0,1,4,5,6,8,9,12,13,14) using k map

• Simplify the function using 4-varabile map

• Represent the simplified function in sum of minterms

23. Design a sequential detector which produces an output 1 every time the input sequence 1011 is detected.







• Logic diagram

24. Explain in detail about serial in parallel out shift register?

• Block diagram


• Logic diagram

• Working

25. Explain the working of BCD Ripple Counter with the help of state diagram and logic

diagram.

• BCD Ripple Counter Count sequence

• Truth Table



DIGITAL ELECTRONICS

• Logic Diagram

26. Design a combinational circuit that performs the arithmetic sum of three inputs bits and

produces a sum and carry output?

• Given problem is full adder(3 bit)

• Write truth table for full adder

• Using k map to minimize the sum and carry values

• Realize the sum and carry minimized value in to logic diagram using basic gates.

27. Design a combinational circuit which distributes one input line to eight output lines based

on the select inputs?

• Given problem is 1:8 demultiplexers.

• Write truth table of 1:8 demux

• Draw the circuit which is going to perform truth table function using basic logic gates

28.Implement the following Boolean function with a PLAF1(A,B,C)= m(0,1,2,4)F2(A,B,C)=

m(0,5,6,7)

• Simplify F1 and F2 using k-map

• F1(A,B,C)=(AB+AC+BC)'

• F2(A,B,C)=AB+AC+A'B'C'

• Draw the PLA programming table with mintermsAB,AC,BC&A'B'C'

29. Write a Verilog coding for half adder?

• Write the module and module name

• Specifying the input and output

• Perform the corresponding operation

• Finally end module

30.i) Explain the 4 bit binary to gray code converter with the necessary diagram. (10)

• Write the 4 bit binary code truth table

• By using logic the binary code converted to 4 bit carry code

• Draw the logic diagram for the both

DIGITAL ELECTRONICS

31. Design a comparator.

• The two numbers are equal if all pairs of significant digits are equal

• To determine if A > B or A < B or A=B, we check the relative magnitude of pairs of

significant digits starting from MSB.

• .Write the truth table.

• .Form the K map and simplify the map.

• .Draw the logic diagram.

32. Discuss in detail about jk flip-flop

• Define flip-flop and types

• Draw the truth table of jk

• Draw the state diagram

• Write the characteristics equation

• Mention about race around condition

DIGITAL ELECTRONICS

ANNA UNIVERSITY CHENNAI

B.E/B.TECH DEGREE EXAMINATION MAY/JUNE 2007

EC 242- DIGITAL ELECTRONICS

PART-A

1. Convert binary number 10112 to gray code?

Write down the Binary number first. The left most significant bit of a given binary code

number is same as the most left significant bit of the gray number

2. To obtain the successive gray bits to produce the equivalent binary number for the

given binary code number, add the first bit of binary code to the second one and write

down the result next to the first bit, add the second binary code bit to third one and

write down the result and so on next to the second bit and repeat the same operation

until the last bit.

Answer is 1110

2. Minimize the function using Boolean algebra f=x(y+w’ z)+wxz

f=x(y+w’ z)+wxz

=xy+xw’z+wxz

=xy+xz(w+w’)

= x(y+z).

3. Design a half adder.

A half-adder is a combinational circuit that can be used to add two bits. It has two

inputs that represent the two bits to be added and two outputs, with one producing the

SUM output and the other producing the CARRY.

4. Define propagation delay?

DIGITAL ELECTRONICS

Propagation delay, symbolized tpd, is the time required for a digital signal to travel from

the input(s) of a logic gate to the output. It is measured in microseconds (µs),

Propagation delay is important because it has a direct effect on the speed at which a

digital device, such as a computer, can operate. This is true of memory chips as well as

microprocessors.

5. What are different modes operations in asynchronous sequential circuits?

Two types of asynchronous circuits are –

1. Fundamental mode circuit,

2. Pulse mode circuit.

According to the characteristics of the input,

Fundamental mode circuit:

The input is allowed to charge after the steady state condition. Here the inputs are levels

and not pulses.

Pulse mode circuit:

Here the inputs are pulses. The pulses width must not be so long that it is still present after

the new state is reached. Generally Fundamental mode circuit is preferred over pulse mode circuits

because it is very difficult to fix the pulse width.

6. What is hazard in asynchronous circuits?

The unwanted switching transients that may appear at the output of a circuit are called

hazards. The hazards cause the circuit to malfunction. The main cause of hazards is the

different propagation delays at different paths.

Hazards occur in the combinational circuits, where they may cause a temporary false

output value. When such combinational circuits are used in the asynchronous sequential

circuits, they may result in a transition to a wrong stable state.

7. Draw logical diagram of 4 bit bi-directional shift register?

DIGITAL ELECTRONICS

8. Write the characteristics equation of JK flip flop and show how JK is converted to

T flip flop?

• Characteristic equation of JK flip flop: Q(t+1)=JQ'+K'Q

Input Present state Next state Flip-Flop Inputs

T Qn Qn+1 J K

0

0

1

1

0

1

0

1

0

1

1

0

0

x

1

x

x

0

x

1

DIGITAL ELECTRONICS

9. What is advantage of using schottky TTL gate?

TTL integrated circuits were a standard method of construction for the processors of

mini-computer and mainframe processors; such as the DEC VAX and Data General

Eclipse, and for equipment such as machine tool numerical controls, printers and video

display terminals. As microprocessors became more functional, TTL devices became

important for "glue logic" applications, such as fast bus drivers on a motherboard,

which tie together the function blocks realized in VLSI elements.

10. .List the modeling techniques available in HDL.

• Structural Modeling

• Dataflow Modeling

• Behavioural Modeling

PART-B

11.a. find the minimum of sum of products using k map for the function f=∑ m(

7,9,10,11,12,13,14,15) and realized the minimized function using only NAND gate.

• Use 4 variable k map and place given variable

• Group variable

• Find simplified expression of given variable

• Realize the simplified expression using NAND gate only.

Or

11.b. simplify using quine mc-clusky method f= ∑ m(0,1,2,3,10,11,12,13,14,5)?

• List all minterms in the binary form

• Arrange minterms according to categories of 1 in a table

• Compare each binary number with every term in the next higher category and ifthey differ

only one position put a check mark and copy the term in the nextcolumn with a – in the

position that they differed.

• Continue the process until no further elimination of literals

• List the prime implicants

DIGITAL ELECTRONICS

• Select the minimum number of prime implicant.

12.a. write a detailed note on Race free state assignment.

• Three row flow table example

• Four row flow table example

• Multiple row method

b. Explain with neat diagram the different hazards and the way to eliminate them?






Or

12. Write notes on races and cycle that occur in fundamental modes circuits?

• Basics of races




• Cycles

13. Design a 4 bit comparator using logic gates?

• Two numbers represented by A = A3A2A1A0 & B = B3B2B1B0

• If two numbers equal P = Ai ⊕Bi

• Obtain the logic Expression.

• Obtain the logic diagram

Or

13.b. implement the given function using PROM AND PLA F1=∑M(0,1,3,5,7,9) ,

F2=∑M(1,2,4,7,8,10,11)

• Simplify F1 and F2 using k-map

• Draw the PLA programming table with min terms of f1,f2

• Draw the PROM programming table with min terms of f1,f2

DIGITAL ELECTRONICS

14. Design a synchronous counter which counts sequence 0,2,6,1,7,5,0 using D-FLIP-

FLOP. Draw the state and logic diagram?

• Form a present and next state table from the given count sequence

• From the present and next state find the flip-flop inputs using k maps

• Using simplified expression in k map, draw the logic diagram.

Or

14. Explain in detail about semiconductor memory?


• Classification


� ROM – PLD, PAL, FPGA

15. What are the different types of TTL gates available? Explain the operation suitable

examples?

• Define TTL logic

• Explain about fundamental of TTL logic

• Explain sub types of TTL

• Low power TTL

• High speed TTL

• Schottky TTL

• Low power TTL

• Low voltage TTL

Or

15.b. Draw the circuit diagram of 2 input CMOS NOR gate and CMOS NAND gate using

CMOS logic and explain their operation in detail?

• Define CMOS logic

• Draw the circuit diagram of 2 input CMOS using NOR logic

• Explain the operation with truth table

• Draw the circuit diagram of 2 input CMOS using NAND logic

• Explain the operation with truth table

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