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DEPARTMENT OF INFORMATION TECHNOLOGY

CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN

UNIT 2

COMBINATIONAL LOGIC

Combinational circuits – Analysis and design procedures – Circuits for arithmetic operations – Code conversion – Introduction to Hardware Description Language (HDL)

This unit gives the basic ideas for designing and analyzing the simple digital circuit (combinational) using the concepts learnt in first unit.

INTRODUCTION

In digital circuit theory, combinational logic (also called combinatorial logic) is a type of logic circuit whose output is a pure function of the present input only. This is in contrast to sequential logic, in which the output depends not only on the present input but also on the history of the input. In other words, sequential logic has memory while combinational logic does not.

Combinational logic is used in computer circuits to do Boolean algebra on input signals and on stored data. Practical computer circuits normally contain a mixture of combinational and sequential logic. For example, the part of an arithmetic logic unit, or ALU, that does mathematical calculations is constructed in accord with combinational logic, although the ALU is controlled by a sequencer that is constructed in accord with sequential logic.

For n input variables, there are 2n possible input combinations. For each input there is only one output. A combinational circuit is described by m Boolean functions, one for each output variable. Each output function is expressed in terms of n input variables.

2.1 ANALYSIS PROCEDUREProcedure starts with getting Boolean expression and truth

table from the logic circuit or by computer simulation program. Check first whether the given circuit is combinational or not.To get Boolean expression from circuit,

i) Label all gates outputs which are the direct function of input variables with arbitrary symbols and determine Boolean function for each gate output

ii) Label all gates outputs which are the functions of input variables and previously labeled gates and determine Boolean function for these gates

iii) Repeat step ii until the output of the circuits are obtained.iv) By repeated Substitution of previously defined symbols,

outputs in terms of input variables is obtainedExample:

Figure 2.1 Logic diagram for analysis exampleT1, T2 and F2 are defined first.T1 = A+B+CT2 = ABCF2= AB+AC+BC

T3 by next step.T3 = F2’T1 = (AB+AC+BC)’ A+B+C

F1 is the finalized expression for one outputF1 = T3+T2 = A’BC’+A’B’C+AB’C’+ABC

Table 2.1 Truth table for the above exampleTruth table is constructed directly from the Boolean

expression. From the circuit, start constructing from the calculation for each logic gate until the output of the circuit is reached.

2.2 DESIGN PROCEDUREDesign starts from the specification of the problem and

culminates in a logic circuit diagram or set of Boolean functions from which the circuit is obtained.Steps:

i) Determine the number of inputs and outputs from the specification of the problem.

ii) Derive the truth table.iii) Obtain simplified Boolean functions for each output as

function of inputsiv) Draw the logic diagram and verify the correctness of the

designVerbal specification of the problem should be interpreted

correctly in truth table. Output binary functions in truth table are simplified by algebraic manipulation, map method or by computer simulation depending upon the application.

Example: BCD to Excess-3 code.Here the BCD is considered under 4-bit case. Excess-3 also have

the same number of bits. Conversion table is shown below.

Table 2.2 Truth table for BCD to Excess-3 code conversionK-Map simplification for the outputs (w,x,y,z) is done as shown under to arrive at the simplified Boolean function.

The two level logic diagram for the derived Boolean expression is drawn directly. But the function may be simplified further as

Figure 2.2 Logic diagram for BCD to Excess-3 conversion

2.3 ARITHMETIC CIRCUITSVarious arithmetic operations are encountered in computing

tasks. Most basic operation is addition of two binary digits. Starting with the addition of 2 LSb and adding the next higher order bit with the generated carry and proceeds through the number.

2.3.1 Half adder

It is a Combinational circuit doing the addition of two bits only. Output is Sum and Carry.

Figure 2.3 Half adderThe output Boolean expressions are,

So = Ao’Bo +AoBo’Co = AoBo

The logic diagram for the above expression can be expressed as follows:

Figure 2.4 logic circuit of Half adder Figure 2.5 Simplified circuit

Now this is only a half adder, since although we are generating a carry, we cannot add in the carry from the previous addition.

2.3.2 Full adder

For all other bits (except the lsb) a half adder will not suffice because there may be a carry input from a previous stage. ie) It is a Combinational circuit doing the addition of three bits only. (Two information bit+one previous carry).

Figure 2.6 Full adder and Truth table

Full adder can be built by using two half adders as shown below.Two bits are added and the sum is given as one of the input to the next half adder along with the previous carry. Carry in cascaded blocks are added separately to produce the final carry.Remember the Boolean operationFor half adder:S’K = AK BK

Figure 2.7 Full adder in terms of half adder

C’K = AKBK

For full adder:SK = AK BK CK-1

CK = AKBK + CK-1(AK BK)

Proof:

Figure 2.8 Simplified Full adder

2.3.3 The parallel (binary) adder: Also called ripple carry adder used to add two n-bit numbers.

it consists of n full adders where the carry output of each stage is the carry in of the next stage.

Figure 2.9 Simplified Full adderInitial carry, C-1 , is zero. But to get Co, propagation delay, 2

gate delay, inside Full adder is encountered. Totally 8x2 gate delays

are there to get C3 finally. This is avoided by using Carry look ahead generator which is generating Carries simultaneously.

Figure 2.10 Full adder CircuitFrom the above full adder circuit,

Where Gi is Carry generate as it produces the output carry regardless of the input carry and Pi is Carry propagate as it is associated with the carry propagation from input to the output.We can have the following Boolean expression from the figure 2.10.

Above Boolean functions is implemented by the logic diagram shown in 2.11.

Figure 2.11 Logic diagram of a Carry look ahead generator

A 4-bit Binary adder is built with the Carry look ahead generator as shown in figure 2.12

Figure 2.12 4-bit full adders with look ahead carryIn Connection with the above diagram, all the output carries are generated simultaneously by having Gi, Pi and Co as the inputs.

2.3.4 Decimal adder: Decimal numbers are presented in coded form in all case of

digital devices for manipulation. Accepting numbers in coded form and presenting the result in same form.

In these cases 9 inputs (8 data+1 Previous carry) and 5 outputs(4 data+1 output carry) are needed.

2.3.4.1 BCD adder: One example of the decimal adder is BCD adder. It is

useful because many digital devices process + display numbers in tens in BCD each number is defined by a binary code of 4 bits.

We will now look at into the effort of using a binary adder to add 2 single digit BCD numbers.

The maximum possible BCD number is 9. So for adding two BCD number, 9+9+1(for Carry) = 19 is the maximum value the BCD adder should represent at its output.

Following table represents the BCD, binary values for the corresponding decimal number till 19. We can use this table to detect the binary combinations which are greater than the BCD number 1001. ie) 9.

From the table, (Look at the Binary Sum column) For the first group of numbers, partitioned till 9, BCD

and binary are equal. In the next 6 combinations, Z8 is 1 always also with 1s in

either Z4 or Z2 places. This condition is stated as Z8Z4+ Z8Z2

In the last 4 combinations, K is 1.As a consequence we can deduce the condition of getting

carry once the result of the summation of a binary adder exceeds the number 9.

C = K+ Z8Z4+ Z8Z2

Figure 2.13 Block diagram of a BCD adder

So When C =1, 0110 is added to the result to convert the binary number to BCD number. The entire process is implemented as a block diagram in figure 2.13

2.3.5 Binary Multiplier : Binary multiplier performs the operation similar to the decimal

multiplication using partial products method.Consider two 2-bit number B1 B0 and A1 A0

B1 B0 A1 A0

A0B1 A0B0 A1B1 A1B0 C3 C2 C1 C0

Figure 2.14 Block diagram of 2-bit multiplier

For J multiplier bits and K multiplicand bits, we need(J*K) AND gates(J-1) K-bit adders to produce (J+K) bits as result.

2.3.5 Magnitude Comparator : It compares two numbers and gives relative magnitudes.3-variables used to specify the result for three conditions (>,

=, <)Thus for an n-bit comparator 22n entries are needed in the

truth table. So design is cumbersome unless we use algorithmic procedure.Consider for 4-bit comparison of A A3 A2 A1 A0 and B B3 B2 B1 B0

A=B If all the bits are equal. Ex-NOR gate is used to check this status as

Xi = Ai Bi + A’i B’I for i = 0,1,2,3Finally the condition is, (A=B)= X3X2X1X0

A>B if MSB of A= 1 and that of B = 0. This can be stated as, (A>B) = A3B3’ + X3A2B2’ + X3X2A1B1’ + X3X2X1A0B0’ B>A if MSB of A= 1 and that of B = 0. This can be stated as, (A>B) = A3’B3 + X3A2’B2 + X3X2A1’B1 + X3X2X1A0’B0The stated condition is implemented simply by the logic diagram as shown in figure 2.14

A0 A1 B0 B1 C0 C1 C2 C3

Figure 2.15 4-bit magnitude comparatorThe same circuit can be used to compare the magnitudes of two BCD digits.

2.4 CODE CONVERSIONCode conversion is necessary to achieve the

compatibility between two different systems following different coding schemes. The code that has to be converted is applied as the inputs and the output gives the transferred code. BCD to Excess-3 conversion was given already.

2.4.1 Excess-3 to BCD code conversionThe truth table for excess-3 to BCD is constructed and from the table the equation for conversion of BCD to excess-3 is obtained. It is then implemented with the help of logic gates.TRUTH TABLE

EXCESS-3 BCDA B C D W X Y Z0 0 1 1 0 0 0 00 1 0 0 0 0 0 10 1 0 1 0 0 1 00 1 1 0 0 0 1 10 1 1 1 0 1 0 01 0 0 0 0 1 0 11 0 0 1 0 1 1 01 0 1 0 0 1 1 11 0 1 1 1 0 0 01 1 0 0 1 0 0 1

By applying K-map method the simplified circuit is shown below

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7432

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330k

Figure 2.16 Excess-3 to BCD converter

2.4.2 Binary to Gray code converterThe first bit of the gray code will be the same as the first bit of the binary code. Second bit of gray code is obtained by the XOR operation of first two bits in the binary code .Similarly third bit is obtained by the XOR combination of second and third bit in binary and so on.

TRUTH TABLEDECIMAL BINARY CODE

D C B A

GRAY CODEG3 G2 G1

G00 0 0 0 0 0 0 0 01 0 0 0 1 0 0 0 12 0 0 1 0 0 0 1 13 0 0 1 1 0 0 1 04 0 1 0 0 0 1 1 05 0 1 0 1 0 1 1 16 0 1 1 0 0 1 0 17 0 1 1 1 0 1 0 08 1 0 0 0 1 1 0 09 1 0 0 1 1 1 0 110 1 0 1 0 1 1 1 111 1 0 1 1 1 1 1 012 1 1 0 0 1 0 1 013 1 1 0 1 1 0 1 114 1 1 1 0 1 0 0 115 1 1 1 1 1 0 0 0

Figure 2.17 Binary to Gray converter

2.4.3 Gray to Binary code converter

TRUTH TABLE

GRAY CODE BINARY CODEG3 G2 G1 G0 D C B A0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 1 0 0 1 00 0 1 0 0 0 1 10 1 1 0 0 1 0 00 1 1 1 0 1 0 10 1 0 1 0 1 1 00 1 0 0 0 1 1 11 1 0 0 1 0 0 01 1 0 1 1 0 0 11 1 1 1 1 0 1 01 1 1 0 1 0 1 11 0 1 0 1 1 0 01 0 1 1 1 1 0 11 0 0 1 1 1 1 01 0 0 0 1 1 1 1

Figure 2.18 Gray to Binary converter

2.5 PARITY CHECKING AND GENERATION

It is the simple error detecting code by appending or prepending one (parity) bit in each data word at the transmitter. The bit added

will make the total number of 1s in the word (including parity bit) as even or odd. The receiver detects the error by counting the number of 1s in each word.IC 74180 is used to check/generate even/odd parity of the 9-bit data.

Figure 2.19 PIN configuration

The data (X0 – X7) along with the Even or odd input (9-bits in total) is checked by the IC. It will act as the parity generator if PE = 1, PO = 0 (shown in first two entry in truth table). These inputs also taken into account while counting for the 1s. ∑ even output will glow to generate a 1 to make the total number of 1s even. The last two entries show the IC operation as parity checker. It checks the number of 1s in those 9-bits and gives output accordingly.Both the ∑ outputs are produced simultaneously. Output is derived from any of these two pins depending up on the parity we follow.TRUTH TABLE

INPUT OUTPUTNo.of.highData input

(X0-X7)

PE PO ∑ EVEN ∑ ODD

EVEN 1 0 1 0ODD 1 0 0 1EVEN 0 1 0 1ODD 0 1 1 0

IC 74180 is cascaded to increase the word length capability from 9-bit to 16-bit. It is shown below. MODE = 1 for checking parity and for MODE = 0, for generating parity.

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Figure 2.20 bit parity checker/Generator

2.6 INTRODUCTION TO HARDWARE DESCRIPTION LANGUAGE (HDL)

HDL is a language that describes the hardware of digital systems in a textual form.

It resembles a programming language, but is specifically oriented to describing hardware structures and behaviors.

The main difference with the traditional programming languages is HDL’s representation of extensive parallel operations whereas traditional ones represents mostly serial operations.

The most common use of a HDL is to provide an alternative to schematics.

When a language is used for the above purpose (i.e. to provide an alternative to schematics), it is referred to as a structural description in which the language describes an interconnection of components.

Such a structural description can be used as input to logic simulation just as a schematic is used.

Models for each of the primitive components are required.

If an HDL is used, then these models can also be written in the HDL providing a more uniform, portable representation for simulation input.

HDL can be used to represent logic diagrams, Boolean expressions, and other more complex digital circuits.

Thus, in top down design, a very high-level description of a entire system can be precisely specified using an HDL.

This high-level description can then be refined and partitioned into lower-level descriptions as a part of the design process.

As a documentation language, HDL is used to represent and document digital systems in a form that can be read by both humans and computers and is suitable as an exchange language between designers.

The language content can be stored and retrieved easily and processed by computer software in an efficient manner.

There are two applications of HDL processing: Simulation and Synthesis

2.6.1 Logic Simulation A simulator interprets the HDL description and produces a

readable output, such as a timing diagram, that predicts how the hardware will behave before its is actually fabricated.

Simulation allows the detection of functional errors in a design without having to physically create the circuit.

The stimulus that tests the functionality of the design is called a test bench.

To simulate a digital system Design is first described in HDL Verified by simulating the design and checking it with a

test bench which is also written in HDL.

2.6.2 Types of HDLThere are two standard HDL’s that are supported by IEEE.

VHDL (Very-High-Speed Integrated Circuits Hardware Description Language) - Sometimes referred to as VHSIC HDL, this was developed from an initiative by US. Dept. of Defense.

Verilog HDL – developed by Cadence Data systems and later transferred to a consortium called Open Verilog International (OVI).

2.6.3 Verilog Verilog HDL has a syntax that describes precisely the legal

constructs that can be used in the language. It uses about 100 keywords pre-defined, lowercase, identifiers

that define the language constructs. Example of keywords: module, endmodule, input, output wire,

and, or, not , etc., Any text between two slashes (//) and the end of line is

interpreted as a comment. Blank spaces are ignored and names are case sensitive.

2.6.3.1 Verilog - Module A module is the building block in Verilog. It is declared by the keyword module and is always terminated

by the keyword endmodule. Each statement is terminated with a semicolon, but there is

no semi-colon after endmodule.

HDL Example: module smpl_circuit(A,B,C,x,y);

input A,B,C;output x,y;

wire e;and g1(e,A,B);not g2(y,C);or g3(x,e,y);

endmodule

2.6.3.2 Verilog – Gate Delays Sometimes it is necessary to specify the amount of delay from

the input to the output of gates. In Verilog, the delay is specified in terms of time units and the

symbol #. The association of a time unit with physical time is made using

timescale compiler directive. Compiler directive starts with the “backquote (`)” symbol.

`timescale 1ns/100ps The first number specifies the unit of measurement for time

delays. The second number specifies the precision for which the

delays are rounded off, in this case to 0.1ns.

//Description of circuit with delay module circuit_with_delay (A,B,C,x,y); input A,B,C; output x,y; wire e; and #(30) g1(e,A,B); or #(20) g3(x,e,y); not #(10) g2(y,C);endmodule2.6.3.3 Test Bench

In order to simulate a circuit with HDL, it is necessary to apply inputs to the circuit for the simulator to generate an output response.

An HDL description that provides the stimulus to a design is called a test bench.

The initial statement specifies inputs between the keyword begin and end.

Initially ABC=000 (A,B and C are each set to 1’b0 (one binary digit with a value 0).

$finish is a system task.

HDL Example:module circuit_with_delay (A,B,C,x,y); input A,B,C; output x,y; wire e; and #(30) g1(e,A,B); or #(20) g3(x,e,y); not #(10) g2(y,C);endmodule

//Stimulus for simple circuitmodule stimcrct;reg A,B,C;wire x,y;circuit_with_delay cwd(A,B,C,x,y);initial begin A = 1'b0; B = 1'b0; C = 1'b0; #100 A = 1'b1; B = 1'b1; C = 1'b1; #100 $finish; endendmodule

Self Test1. The output expression for an AND-OR circuit having one AND gate with inputs A,B,C and D and one AND gate with inputs E and F is

a. ABCDEF b. A+B+C+D+E+Fc. (A+B+C+D)(E+F) d. ABCD + EF

2. A logic circuit with an output X = AB’C + AC’ consists of a. two AND gates and one OR gateb. two AND gates, one OR gate and two invertersc. two OR gates, one AND gate and two invertersd. two AND gates, one OR gate and one inverter

3. To implement the expression A’BCD+AB’CD+ABC’D’, it takes one OR gate and

a. one AND gateb. three AND gatesc. three AND gates and four invertersd. three AND gates and three inverters

4.The expression A’BCD+ABCD’+AB’C’D a. can not be simplifiedb. can be simplified to A’BC+AB’c. can be simplified to ABCD’+A’BC’d. None of these answers is correct

5. An Exclusive OR function is expressed as a. A’B’+AB b. A’B+AB’c. (A’+B)(A+B’) d. (A’+B’)+(A+B)

6. The AND operation can be produced with a. two NAND gates b. three NAND gatesc. one NOR gate d. two NOR gates

7. All Boolean expressions can be implemented with a. NAND gates onlyb. NOR gates onlyc. Combination of AND gates, OR gates and invertersd. any of these

8. According to DeMorgan’s theorems, the following equality(s) are correct

a. (AB)’ = A’+B’ b. (XYZ)’ = X’+Y’+Z’c. (A+B+C)’ = A’B’C’ d. all of these

9. The Boolean expression AB’CD’ is a. a sum term b. a product termc. a literal term d. always 1

10. Which of the following rule states that if one input of an AND gate is always 1, the output is equal to the other input?

a. A+1 =1 b. A+A = Ac. A.A = A d. A.1 = A

11. An example of standard SOP expression isa. A’B+AB’C+ABD’ b. AB’C+AC’Dc. AB’+A’B+AB d. AB’CD’+A’B+A’

12. The minimized form of the logical expression (A’B’C’+A’BC’+A’BC+ABC’) is

a. A’C’+BC’+A’B b. AC’+B’C+A’Bc. A’C+B’C+A’B d. AC’+B’C+AB’

13. If X= 1 in the logic equation [X+Z{Y’+(Z’+XY’)}]{X’+Z’(X+Y)} = 1 , then

a. Y = Z b. Y = Z’c. Z = 1 d. Z = 0

14. The output of a logic gate is 1 when all its inputs are at logic 0. Then gate is either

a. a NAND or an EXOR gate b. a NOR or an EXNOR gate

c. an OR or an EXNOR gate d. an AND or an EXOR gate

15. The Boolean function A+BC is reduced form of a. AB+BC b. (A+B) (A+C)c. A’B+AB’C d. (A+C) B

Review QuestionsPart-A

1. How will you build a full adder using 2 half adders and an OR gate?2. Implement the switching function Y= BC’ + A’B + D3. Draw 4 bit binary parallel adder4. Write down the truth table of a full adder5. Write down the truth table of a full sub tractor6. Write down the truth table of a half sub tractor7. Find the syntax errors in the following declarations (note that names for primitive gatesare optional):module Exmp1-3(A, B, C, D, F)

Answers for Self Test1. d 2. b 3. c 4. a 5. b 6. a7. d 8. d 9. b 10. d 11. c 12. a13. d 14. b 15. b

inputs A,B,C,and g1(A,B,D);not (D,B,A);OR (F,B,C);endmodule ;8. Draw the logic diagram of the digital circuit specified bymodule circt (A,B,C,D,F);input A,B,C,D;output F;wire w,x,y,z,a,d;and (x,B,C,d);and y,a,C);and (w,z,B);or (z,y,A);or (F,x,w);not (a,A);not (d,D);endmodule9. Define Combinational circuits10. Define Half and Full adder11. Give the four elementary operations for addition and subtraction12. Design the combinational circuit with 3 inputs and 1 output. The output is 1 when the binary value of the inputs is less than 3.The output is 0 otherwise13. Define HDL14. What do you mean by carry propagation delay?15. What is code converter?16. Give short notes on Logic simulation and Logic synthesis17. What do you mean by functional and timing simulation?18. What do you mean by test bench?19. Give short notes on simulation versus synthesis20. Define half sub tractor and full sub tractor

Part-B1 Design a 4 bit magnitude comparator to compare two 4 bit number

2 Construct a combinational circuit to convert given binary coded decimal number into an Excess 3 code for example when the input to the gate is 0110 then the circuit should generate output as 10013 Design a combinational logic circuit whose outputs are F1 = a’bc + ab’c andF2 = a’ + b’c + bc’4 (a) Draw the logic diagram of a *-bit 7483 adder(b) Using a single 7483, Draw the logic diagram of a 4 bit adder/sub tractor5 (a) Draw a diode ROM, which translates from BCD 8421 to Excess 3 code(b) Distinguish between Boolean addition and Binary addition6 Realize a BCD to Excess 3 code conversion circuit starting from its truth table7 (a) Design a full sub tractor(b) How to it differ from a full sub tractor8 Design a combinational circuit which accepts 3 bit binary number and converts its equivalent excess 3 codes9 Derive the simplest possible expression for driving segment “a” through ‘g’ in an 8421 BCD to seven segment decoder for decimal digits 0 through 9 .Output should be active high (Decimal 6 should be displayed as 6 and decimal 9 as 9)10 Write the HDL description of the circuit specified by the following Boolean function

(i) Y= (A+B+C) (A’+B’+C’)(ii) F= (AB’ + A’B) (CD’+C’D)(iii) Z = ABC + AB’ + A(D+B)(iv) T= [(A+B} {B’+C’+D’)]