chip pak mold compound and plating qual for customers.ppt€¦ · chip pak 0217 asekr maskset /...

Chip Pak Pressure Sensor Mold Compound and Leadframe Plating Qual

TM

Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006.

Introduction

This file contains:• Electrical Test Distributions• Reliability Test Results• Reliability Test Electrical Deltasyfor the chip pak pressure sensor mold compound (MC) and leadframe (LF) qualification.

The qualification was performed for:1 new leadframe and new mold compound1. new leadframe and new mold compound 2. new leadframe and current mold compound

TMFreescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006. 2

Electrical Distributions


ZinNew LF and New MC New LF and Old MC

Control

Lot 1 o

Lot 2Lot 2

Lot 3


ZoutNew LF and New MC New LF and Old MC

Control

Lot 1 o

Lot 2Lot 2

Lot 3


TcONew LF and New MC New LF and Old MC

Control

Lot 1 o

Lot 2Lot 2

Lot 3


OffsetNew LF and New MC New LF and Old MC

Control

Lot 1 o

Lot 2Lot 2

Lot 3


SpanNew LF and New MC New LF and Old MC

Control

Lot 1 o

Lot 2Lot 2

Lot 3


RcalNew LF and New MC New LF and Old MC

Control

Lot 1 o

Lot 2Lot 2

Lot 3


Reliability Test Results

TMFreescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006. Slide 10

Rel ResultsNew LF and New MCNew LF and New MC

Objective:

FreescalePN / Part Name:

Customer Name / PN:

Plan-ResultsRevision #/Date: Rev 1: July-9-2009

Technology & Package: QUARTZ Tracking #:

Design Engr/

Various

To New Mold Compound (UDEL P-1710) for Chip Pak

DXD2310M16R0A

Chip pak 0217

Fab/Assembly/Final Test Sites: Design Engr/Phone #: (Signature/Date may be electronic)

Maskset / Rev#: Product Engr/Phone #:

Prepared By Signature/Date: David Sebert / July-9-09

Die Size(u m) W x L x T

NPI PRQE/Phone #:

NPI Quality Approval Signature/Date: David Sebert / July-9-09

Part OperatingTemperature Grade: 15-40 C Lot Trace/Date Codes:

LOT AK0947EB

LOT BK0947EC

LOT CK0947ED

CAB Approval Signature/Date:

Target Dates:

Alyssa Kris480-413-3572

Heidi Denton 480-413-4032

L07K (100 mm), M16R (150 mm)

Andrew McNeilASEKr

Test StartTest Finish Q4 2009

Q1 2010 Final Test Program Name: 48ARB61241B Final Test Program Revision: Rev N

Customer ApprovalSignature/Date:

STRESS

Reference

M=MIL883J=JESD22

Test Conditions(Test Conditions if shown below are typical and must be modified to meet specific qualification tier/customer requirements)

End Point RequirementsMinimum Sample

Size # of Lots Total UnitsResults

LotID-(#Rej/SS)(NO failures allowed)

Comments(NA = Not Applicable)

(Testing performed by Rel Lab unless otherwise noted below)

GROUP A - ACCELERATED ENVIRONMENTAL STRESS TESTS

Temp Cycle (TC) JA104 Temp Cycle; -20°C to +70°C >/= 15 minute dwell, </= 5 min transfer for 250, 500 cycles TEST @ RHC 77 3 + 1 control 308 0/231

0/77 Done at ASEk

Temp Humidity Storage (THS) JA101

Temperature Humidity Storage60°C/90%RH for 168, 504 hrs TEST @ RHC 77 3 + 1 control 308 0/231

0/77 Done at ASEk

High Temperature StorageHTSL AEC Q100-005

High Temperature StorageTa=85 CRO 504 hrs

TEST @ RHC 77 3 + 1 control 308 0/2310/77 Done at ASEk


Rel ResultsNew LF and Old MCNew LF and Old MC

Objective:

FreescalePN / Part Name:

Customer Name / PN:

Plan-ResultsRevision #/Date: Rev 3: August 6 2009

Technology & Package: QUARTZ Tracking #:

Fab/Assembly/Final Test Sites: Design Engr/Phone #: (Signature/Date may be electronic)

Various

Andrew McNeil

New Plating for Chip Pak

DXD2310M16R0A

Chip pak 0217

ASEKr

Maskset / Rev#: Product Engr/Phone #:

Prepared By Signature/Date: David Sebert August 6 2009

Die Size(u m) W x L x T

NPI PRQE/Phone #:

NPI Quality Approval Signature/Date: David Sebert August 6 2009

Part OperatingTemperature Grade: 15-40 C Lot Trace/Date Codes:

LOT AK0947EF

LOT BK0947EG

LOT CK0947EH

CAB Approval Signature/Date:

Target Dates:Test StartTest Finish Q4 2009 Final Test Program Name: 48ARB61241B Final Test Program

R i i R NCustomer ApprovalSi t /D t

Alyssa Kris480-413-3572

Heidi Denton480-413-4032

L07K (100 mm), M16R (150 mm)

Test Finish Q4 2009 Final Test Program Name: 48ARB61241B Revision: Rev N Signature/Date:

Stresses in Yellow will be performed.

Reference T t C diti Minimum Sample R lt Comments

GROUP A - ACCELERATED ENVIRONMENTAL STRESS TESTS

STRESS M=MIL883J=JESD22

Test Conditions(Test Conditions if shown below are typical and must be modified to meet specific qualification tier/customer requirements)

End Point RequirementsMinimum Sample

Size # of Lots Total UnitsResults

LotID-(#Rej/SS)(NO failures allowed)

(NA = Not Applicable)(Testing performed by Rel Lab unless otherwise

noted below)

Temp Cycle (TC) JA104 Temp Cycle; -20°C to +70°C >/= 15 minute dwell, </= 5 min transfer for 250, 500 cycles TEST @ RHC 77 3 + 1 control 308 0/231

0/77 Done at ASEk

Temp Humidity Storage (THS) JA101

Temperature Humidity Storage60°C/90%RH for 168, 504 hrs TEST @ RHC 77 3 + 1 control 308 0/231

0/77 Done at ASEk

HTSL AEC Q100-005High Temperature StorageTa=85 CRO 504 hrs

TEST @ RHC 77 3 + 1 control 308 0/2310/77 Done at ASEk

STRESS

Reference

M=MIL883Test Conditions End Point Requirements

Minimum Sample Size # of Lots Total Units

ResultsLotID-(#Rej/SS)

Comments(NA = Not Applicable)

(Testing performed by Rel Lab unless otherwise

TEST GROUP C - PACKAGE ASSEMBLY INTEGRITY TESTS


M=MIL883J=JESD22 Note 1 (NO failures allowed) (Testing performed by Rel Lab unless otherwise

noted below)

SD JB102Solderability;8hr. Steam age (1 hr. for Au-plated leads) prior to test.If production burn-in is done, samples must also undergo burn-in.

>95% lead coverage of critical areas 15 3 + 1 control 60 0/60 Done at ASEk

Reliability Test DeltasReliability Test DeltasH3T



Control

Lot 1 o

Lot 2Lot 2

Lot 3


Reliability Test DeltasReliability Test DeltasHTS



Control

Lot 1 o

Lot 2Lot 2

Lot 3


Reliability Test DeltasReliability Test DeltasTC



Control

Lot 1 o

Lot 2Lot 2

Lot 3


End PresentationEnd Presentation

TM

Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006.

chip pak mold compound and plating qual for customers.ppt€¦ · chip pak 0217 asekr maskset /...

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