chisel @ cs250 part i lecture 02inst.eecs.berkeley.edu/~cs250/fa12/lectures/lec02.pdf · clean...
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Chisel @ CS250 – Part I – Lecture 02
Jonathan Bachrach
EECS UC Berkeley
August 30, 2012
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Standard Design Methodology 1
Specification
Simulation Synthesis
Hierarchically defines structure and function
of circuit.
Verification: Does the design behave as required with regards
to function (and timing, and power consumption)?
Maps design to resources of implementation platform
(FGPA or ASIC).
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Design Entry 2
Design circuits graphicallyUsed commonly untilapproximately 2002Schematics are intuitiveLabor intensive to produce(especially readable ones).Requires a special editor toolUnless hierarchy is carefullydesigned, schematics can beconfusing and difficult to followon large designs
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Hardware Description Languages 3
Structural Description:connections of components witha nearly one-to-onecorrespondence to schematicdiagram.
Decoder(output x0,x1,x2,x3;
input a,b) {
wire abar, bbar;
inv(bbar, b);
inv(abar, a);
and(x0, abar, bbar);
and(x1, abar, b );
and(x2, a, bbar);
and(x3, a, b );
}
Behavioral Description: usehigh-level constructs (similar toconvential programming) todescribe the circuit function.
Decoder(output x0,x1,x2,x3;
input a,b) {
case [a b]
00: [x0 x1 x2 x3] = 0x1;
01: [x0 x1 x2 x3] = 0x2;
10: [x0 x1 x2 x3] = 0x4;
11: [x0 x1 x2 x3] = 0x8;
endcase;
}
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Verilog Issues 4
Originally invented for simulationMany constructs don’t synthesize: ex: deassign, timing constructsOthers lead to mysterious results: for-loopsDifficult to understand synthesis implications of proceduralassignments (always blocks), and blocking versus non-blockingassignmentsIn common use, most users ignore much of the language and stickto a very strict styleVery weak meta programming support for creating circuit generatorsVarious hacks around this over the years, ex: embedded TCLscriptingVHDL has much the same issues
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Chisel 5Constructing Hardware In Scala Embedded Language
Embed a hardware-description language in Scala, using Scala’sextension facilitiesChisel is just a set of class definitions in Scala and when you write aChisel program you are actually writing a Scala programA hardware module is just a data structure in ScalaClean simple set of design construction primitives for RTL designFull power of Scala for writing hardware generatorsDifferent output routines can generate different types of output (C,FPGA-Verilog, ASIC-Verilog) from same hardware representationCan be extended above with domain specific languages (such asdeclarative cache coherence specifications)Can be extended below with new backends (such as quantum)Open source with lots of librariesOnly 5200 lines of code in current version!
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Chisel Workflow 6
Chisel Program
C++ Code FPGA Verilog ASIC Verilog
Scala / JVM
C++ Compiler FPGA Tools ASIC Tools
C++ Simulator FPGA Emulation GDS Layout
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The Scala Programming Language 7
Compiled to JVMGood performanceGreat Java interoperabilityMature debugging, execution environments
Object OrientedFactory Objects, ClassesTraits, overloading etc
FunctionalHigher order functionsAnonymous functionsCurrying etc
ExtensibleDomain Specific Languages (DSLs)
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Scala Collections 8
// Array’s
val tbl = new Array[Int](256)
tbl(0) = 32
val y = tbl(0)
val n = tbl.length
// ArrayBuffer’s
val buf = new ArrayBuffer[Int]()
buf += 12
val z = buf(0)
val l = buf.length
// List’s
val els = List(1, 2, 3)
val a :: b :: c :: Nil = els
val m = els.length
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Scala Iteration 9
val tbl = new Array[Int](256)
// loop over all indices
for (i <- 0 until tbl.length)
tbl(i) = i
// loop of each sequence element
for (e <- tbl)
tbl(i) += e
// nested loop
for (i <- 0 until 16; j <- 0 until 16)
tbl(j*16 + i) = i
// create second table with doubled elements
val tbl2 = for (i <- 0 until 16) yield tbl(i)*2
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Scala Functional 10
// simple scaling function, e.g., x2(3) => 6
def x2 (x: Int) = 2 * x
// produce list of 2 * elements, e.g., x2list(List(1, 2, 3)) => List(2, 4, 6)
def x2list (xs: List[Int]) = xs.map(x2)
// simple addition function, e.g., add(1, 2) => 3
def add (x: Int, y: Int) = x + y
// sum all elements using pairwise reduction, e.g., sum(List(1, 2, 3)) => 6
def sum (xs: List[Int]) = xs.foldLeft(0)(add)
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Scala Object Oriented 11
object Blimp {
var numBlimps = 0
def apply(r: Double) = {
numBlimps += 1
new Blimp(r)
}
}
Blimp.numBlimps
Blimp(10.0)
class Blimp(r: Double) {
val rad = r
println("Another Blimp")
}
class Zep(r: Double) extends Blimp(r)
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Scala Console 12
> scala
scala> 1 + 2
=> 3
scala> def f (x: Int) = 2 * x
=> (Int) => Int
scala> f(4)
=> 8
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Chisel Example 13
class Mux2 extends Component {
val io = new Bundle{
val sel = Bits(INPUT, 1)
val in0 = Bits(INPUT, 1)
val in1 = Bits(INPUT, 1)
val out = Bits(OUTPUT, 1)
}
io.out := (io.sel & io.in1) |
(~io.sel & io.in0)
}
Mux2~
&
&
|Bits
Bits
Bits
in0
in1
sel
Bits
out
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Literals 14
Bits(1) // decimal 1-bit literal from Scala Int.
Bits("ha") // hexadecimal 4-bit literal from string.
Bits("o12") // octal 4-bit literal from string.
Bits("b1010") // binary 4-bit literal from string.
Fix(5) // signed decimal 4-bit literal from Scala Int.
Fix(-8) // negative decimal 4-bit literal from Scala Int.
UFix(5) // unsigned decimal 3-bit literal from Scala Int.
Bool(true) // Bool literals from Scala literals.
Bool(false)
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Literals 15
Bits("h_dead_beef") // 32-bit literal of type Bits.
Bits(1) // decimal 1-bit literal from Scala Int.
Bits("ha", 8) // hexadecimal 8-bit literal of type Bits.
Bits("o12", 6) // octal 6-bit literal of type Bits.
Bits("b1010", 12) // binary 12-bit literal of type Bits.
Fix(5, 7) // signed decimal 7-bit literal of type Fix.
UFix(5, 8) // unsigned decimal 8-bit literal of type UFix.
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Literal Node Construction 16
UFix(1)
UFix(1)
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Algebraic Construction 17
UFix(1) + UFix(1)
UFix(1)
UFix(2)
+
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Combinational Circuits 18
(sel & in1) | (~sel & in0)
~
in0 &
in1 &
sel |
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Fan Out 19
val sel = a | b
val out = (sel & in1) | (~sel & in0)
~
in0 &
in1 &
|a
b
| outsel
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Wires 20
val sel = Bits()
val out = (sel & in1) | (~sel & in0)
sel := a | b
~
in0 &
in1 &
|a
b
| outBitssel
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Bitwise operators 21
Valid on Bits, Fix, UFix, Bool.
// Bitwise-NOT
val invertedX = ~x
// Bitwise-AND
val hiBits = x & Bits("h_ffff_0000")
// Bitwise-OR
val flagsOut = flagsIn | overflow
// Bitwise-XOR
val flagsOut = flagsIn ^ toggle
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Bitwise reductions 22
Valid on Bits, Fix, and UFix. Returns Bool.
// AND-reduction
val allSet = andR(x)
// OR-reduction
val anySet = orR(x)
// XOR-reduction
val parity = xorR(x)
where reduction applies the operation to all the bits.
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Equality comparison 23
Valid on Bits, Fix, UFix, and Bool. Returns Bool.
// Equality
val equ = x === y
// Inequality
val neq = x != y
where === is used instead of == to avoid collision with Scala.
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Shifts 24
Valid on Bits, Fix, and UFix.
// Logical left shift.
val twoToTheX = Fix(1) << x
// Right shift (logical on Bits & UFix, arithmetic on Fix).
val hiBits = x >> UFix(16)
where logical is a raw shift and arithmetic performs top bit sign extension.
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Bitfield manipulation 25
Valid on Bits, Fix, UFix, and Bool.
// Extract single bit, LSB has index 0.
val xLSB = x(0)
// Extract bit field from end to start bit pos.
val xTopNibble = x(15,12)
// Replicate a bit string multiple times.
val usDebt = Fill(3, Bits("hA"))
// Concatenates bit fields, w/ first arg on left
val float = Cat(sgn,exp,man)
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Logical Operations 26
Valid on Bools.
// Logical NOT.
val sleep = !busy
// Logical AND.
val hit = tagMatch && valid
// Logical OR.
val stall = src1busy || src2busy
// Two-input mux where sel is a Bool.
val out = Mux(sel, inTrue, inFalse)
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Arithmetic operations 27
Valid on Nums: Fix and UFix.
// Addition.
val sum = a + b
// Subtraction.
val diff = a - b
// Multiplication.
val prod = a * b
// Division.
val div = a / b
// Modulus
val mod = a % b
where Fix is a signed fixed-point number represented in two’scomplement and UFix is an unsigned fixed-point number.
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Arithmetic comparisons 28
Valid on Nums: Fix and UFix. Returns Bool.
// Greater than.
val gt = a > b
// Greater than or equal.
val gte = a >= b
// Less than.
val lt = a < b
// Less than or equal.
val lte = a <= b
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Bitwidth Inference 29
operation bit widthz = x + y wz = max(wx, wy)
z = x - y wz = max(wx, wy)
z = x & y wz = min(wx, wy)
z = x | y wz = max(wx, wy)
z = Mux(c, x, y) wz = max(wx, wy)
z = w * y wz = wx + wy
z = x << n wz = wx + maxNum(n)
z = x >> n wz = wx - minNum(n)
z = Cat(x, y) wz = wx + wy
z = Fill(n, x) wz = wx * maxNum(n)
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Functional Abstraction 30
def mux2 (sel: Bits, in0: Bits, in1: Bits) =
(sel & in1) | (~sel & in0)
val out = mux2(k,a,b)
~
b &
k &
a | out
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Bundles 31
class MyFloat extends Bundle {
val sign = Bool()
val exponent = UFix(width = 8)
val significand = UFix(width = 23)
}
val x = new MyFloat()
val xs = x.sign
UFix
UFix
Bool
sig
exp
sig
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Vecs 32
// Vector of 3 23-bit signed integers.
val myVec = Vec(3) { Fix(width = 23) }
can be used as Scala sequencescan also be nested into ChiselBundles
Fix
Fix
Fix
2
1
0
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Static Vec Element Access 33
val myVec = Vec(3) { Fix(width = 23) }
// Connect to one vector element chosen at elaboration time.
val fix0 = myVec(0)
val fix1 = myVec(1)
fix1 := data1
myVec(2) := data2
Fix
Fix
Fix
2
1
0
data2
data1 fix1
fix0
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Dynamic Vec Element Access 34
val myVec = Vec(3) { Fix(width = 23) }
// Connect to one vector element chosen at runtime.
val out0 = myVec(addr0)
val out1 = myVec(addr1)
myVec(addr2) := data2
Fix
Fix
Fix
2
1
0
addr2
data2 deselector
selector
addr0
out0
selector
addr1
out1
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Ports 35
Data object with directions assignedto its members
class FIFOIO extends Bundle {
val data = Bits(INPUT, 32)
val valid = Bool(OUTPUT)
val ready = Bool(INPUT)
}
Direction assigned at instantiationtime
class ScaleIO extends Bundle {
val in = new MyFloat().asInput
val scale = new MyFloat().asInput
val out = new MyFloat().asOutput
}
Bool
Bool
UFix
ready
valid
data
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Component 36
inherits from Component,contains an interface storedin a port field named io, andwires together subcircuits inits constructor.
class Mux2 extends Component {
val io = new Bundle{
val sel = Bits(INPUT, 1)
val in0 = Bits(INPUT, 1)
val in1 = Bits(INPUT, 1)
val out = Bits(OUTPUT, 1)
}
io.out := (io.sel & io.in1) |
(~io.sel & io.in0)
}
Mux2~
&
&
|Bits
Bits
Bits
in0
in1
sel
Bits
out
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Chisel Workflow 37
Mux2.scala bytecodes
Mux2.cpp
scalacompiler
jvmchiselbuilder
jvm cpp backend
Mux2g++
+
1 2
Mux2.v
jvm verilog backend
verificationvcs
simulation
exec
net list + power, area, and speed estimates
dc
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State Elements 38
Reg(in)
Regin
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Rising Edge 39
def risingEdge(x: Bool) = x && !Reg(x)
Reg
x
!
&&
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Counter 40
def counter(max: UFix) = {
val x = Reg(resetVal = UFix(0, max.getWidth))
x := Mux(x == max, UFix(0), x + UFix(1))
x
}
RegMux
UFix(0)
===
maxUFix(1)
+
UFix(0)
reset
tst
consequent
alternate
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Sequential Circuits 41
// Produce pulse every n cycles.
def pulse(n: UFix) = counter(n - UFix(1)) === UFix(0)
// Flip internal state when input true.
def toggle(p: Bool) = {
val x = Reg(resetVal = Bool(false))
x := Mux(p, !x, x)
x
}
// Square wave where each half cycle has given period.
def squareWave(period: UFix) = toggle(pulse(period))