This work was supported by the Turkish Scientific and Technological Research Council (TUBITAK) (Project number: 108T500)

Chracteristic parameters of CdS thin film and C-V properties of Cd/CdS/GaAs/In sandiwich structure as

a function of frequency grown by SILAR Method

Aytunç ATEŞ/Yıldırım Beyazıt University Faculty of Engeenering and Nature Sciences /Deparment of Material Engeenering Ankara/TURKEY aytungaates@gmail.com

Betül GÜZELDİR/Atatürk University Science Faculty/Department of Physics Erzurum/TURKEY bguzeldir84@gmail.com

Mustafa SAĞLAM/Atatürk University Science Faculty/Department of Physics Erzurum/TURKEY msaglam@atauni.edu.tr

Rıdvan DURAK/Atatürk Universiity Science Faculty/ Department of Physics Erzurum/TURKEY rdurak@atauni.edu.tr

Abstract— In the present paper, Cd/CdS/n-GaAs/In sandwich structure grown by Successive Ionic Layer Adsorption and Reaction (SILAR) technique. For structural properties, the XRD and SEM measurements have been done and it is seen that films exhibit polycrystalline behavior. The energy band gap value of CdS thin film has been found as 2.30 eV from the absorption measurements. For electrical properties, C-V measurements have been done as a function of the frequency. The effective barrier height values have been calculated from C-V measurements as 0.681 eV for 30 kHz and 0.957 eV for 3000 kHz.

Keywords-component; SILAR, CdS, structural properties, Cd/CdS/n-GaAs/In sandwich structure

I. INTRODUCTION

In particular, thin CdS films deserve attention because their expected gap emission lies very close to the highest sensitivity of the human eye. Thus, one might assume that thin CdS thin films are an appealing host for photonic devices [1]. Cadmium sulphide (CdS) is an important and useful material for optoelectronic applications. Metal-interfacial layer-semiconductor sandwich structures are of essential importance in semiconductor devices. Such sandwich structures with very thin interlayer behave electrically like Schottky contacts. The barrier heights of such devices depend on the nature of the interfacial layer, its thickness, and the specific metal used [1]. The electrical properties of metal-interfacial layer-semiconductor sandwich structures have been widely studied, both for their basic physical properties and for their technological applications to electronic devices. The thermal stability of the metal–semiconductor (M–S), metal-insulator-semiconductor (MIS) and metal-interfacial layer-semiconductor structures is of great practical importance in device technology owing to the subjection to elevated temperatures at some stage of the manufacturing process [2–4]. In this work, the SILAR method has been used for growth the CdS thin film. Up to now, much effort has been devoted to the preparation sandwich structures. But, there has not been seen any report on preparation of such structures (on directly n-GaAs semiconductor) by means of SILAR method. In this

working, we present how Cd/CdS/n-GaAs/In sandwich structure prepared and calculated of characteristic parameters and frequency effect on the structure. Firstly, structural and optical properties of CdS thin film have been investigated. After, some electrical properties of the Cd/CdS/n-GaAs/In sandwich structure have been investigated by using C-V measurements.

II. EXPERIMENTAL PROCEDURE

In this study, n-type GaAs (100) wafer of relatively carrier density 2.5x1017 cm-3 was used to fabricate Cd/CdS/n-GaAs/In sandwich structure. The substrate was sequentially cleaned with trichloroethylene, acetone, and methanol and then rinsed in deionised water. The native oxide on the surface was etched in sequence with acid solutions ( H2SO4 : H2O2 : H2O = 3:1:1) for 60 s, and ( HCl : H2O = 1:1) for another 60 s. After a rinse in deionised water and a blow-dry with nitrogen, a low resistance ohmic contact on the back side of the sample was formed by evaporating of indium metal at a pressure of about 10−5 Torr, followed by an annealing at 425 ◦C for 3 min in N2 atmosphere. After ohmic contact was made, the ohmic contact side and the edges of the n-GaAs semiconductor substrate was covered by wax so that the polished and cleaned front side of the semiconductor sample was exposed to the cationic precursor solution employed for SILAR method. For the deposition of CdS thin film, a well-cleaned n-type GaAs substrate was immersed in the cationic precursor solution (CdCl2) for 40 s, causing cadmium ions to be adsorbed on the surface of the n-type GaAs substrate. Following this process, the substrate was immersed in doubly distilled water for 50 s to prevent irregular precipitation. The substrate was finally immersed in the anionic precursor solution (Na2S) for 40 s. Sulfide ions was reacted with the adsorbed cadmium ions on the n-type GaAs substrate. The substrate was then immersed in double-distilled water for 50 s. Thus, one cycle of CdS film deposition is completed. For homogeneous thin film layer, this cycles have been repeated as 30 cycle. Cd dots with diameter of about 1.0 mm (the contact area = 7.85×10−3 cm2) were evaporated on the CdS thin film in vacuum coating unit at about 10-5 torr. In this way, the Cd/CdS/n-GaAs/In sandwich structure was obtained.

This work was supported by the Turkish Scientific and Technological Research Council (TUBITAK) (Project number: 108T500)

III. STRUCTURAL MORPHOLOGICAL AND OPTICAL PROPERTIES

The structural analysis of CdS film was carried out by using XRD with varying diffraction angle 2θ, from 20 to 70o. The XRD patterns of this film grown on n-GaAs substrate are shown in Fig. 2. It is seen from the XRD patterns that the CdS film is in polycrystalline orientation along different planes and phases. These planes are (002) and (222). The plane of n-GaAs (100) substrate is clearly observed in “Fig. 1” and the plane intensity is dominant when compared with the others. It is seen from “Fig.2” that, the crystallization is very high.

It is known that the surface properties of the films influence their optical and electrical properties which are important factors in applications to optoelectronic devices. Thus, it is very important to investigate the surface morphology of the films. SEM is well- known technique to study the surface morphology of thin films. Fig. 2 shows SEM image of the CdS film. It is observed that the as-deposited CdS thin film is well covered the substrate. Also, there are macroscopic defects like void, pinhole, peeling or cracks on the film surface. In spite of these, from the surface morphology of the deposited CdS thin film, we can anticipate that these films will exhibit very low optical scattering losses and should therefore be suitable for optoelectronic applications.

The absorption measurements of CdS thin film was carried out at room temperature. The energy band gap value of thin film was calculated with the help of the optical absorption spectra.

To determine the energy band gap, we plotted (αhv)2 versus (hν) where α is the absorption coefficient and hν is the photon energy. The theory of inter band absorption shows that at the optical absorption edge the absorption coefficient α varies with the photon energy hν according to the [1];

2/1)()( gEhBh −= ννα (1)

where B is a constant, Eg is the optical band gap. Thus a plot of (αhv)2 versus (hν) is a straight line whose intercept on the energy axis gives the energy gap, Eg. The band gap energy of film has been determined by the extrapolation of the linear region on the energy axis (hν) as 2.3 eV. This result is agreement with the literature [5-7].

IV. CAPACITANCE-VOLTAGE (C-V) CHARACTERISTICS OF THE CD/CDS/N-GAAS/IN SANDWICH STRUCTURE AT ROOM

TEMPERATURE

The C–V characteristics of the Cd/CdS/n-GaAs/In structure with measured at different frequencies are shown in Fig. 3. The capacitance decreases with the applied bias, which reveals that a depletion region exists at the CdS/n-GaAs junction, and the depletion region width increases with the reverse bias. The peak values of the forward biased capacitance are increased as the operating frequency is decreased. The dependence of the capacitance of such a junction upon frequency can also arise due to the presence of deep lying impurities in the depletion region. Presence of deep traps in the depletion region of the junction makes the junction capacitance a complicated function of the bias voltage and the measuring frequency. The capacitance is nearly constant at the reverse biases region.

The plots of C-2 vs. reverse bias voltage are linear which indicates the formation of junction [8]. Therefore, it follows a standard Mott–Schottky relationship:

( )

dso

bi

NAqqkTVV

C 22

/21εε

−−= (2)

where C is the diode capacitance, Vbi is the built in voltage, εs is the semiconductor dielectric constant, εo is the permitivity in vacuum, V is the applied voltage, q is the electronic charge, A is the diode active area, kT/q is the thermal voltage at 300 K and Nd is the free charge carrier concentration. The value of the barrier height can be calculated by Φb=Vbi + Vn equation using C–V data, where Vn is the potential difference between the Fermi energy level (Ef) and the bottom of the conduction band in the neutral region of n-GaAs, which is directly equal to Ef and can be calculated by knowing Nd and Nc, density of states in the conduction band (Vn= kTln(Nc/Nd)). Fig. 3 shows the frequency dependent of the capacitance values. The free charge carrier concentration can be determined from the slope of 1/C2 vs. V plots. From the extrapolated intercept on voltage axis Vbi can be estimated. Fig. 4 shows the 1/C2–V plot of the Cd/CdS/n-GaAs/In structure that was measured at the frequency of 30–3000 kHz. For 30- 3000 kHz frequencies, calculated the built in voltages, barrier height, carrier concentration and Vn values are calculated from C-2–V.

20 30 40 50 60 70 80

0

5000

10000

15000

20000

25000

30000

(002)

GaAs

CdS

Inte

nsit

y (a

rbt.u

nit)

2θθθθ (degree)

(222)

Figure1. XRD pattern of CdS thin films grown on n-GaAs

Figure2. SEM micrographs of CdS thin film at room temperature

This work was supported by the Turkish Scientific and Technological Research Council (TUBITAK) (Project number: 108T500)

-2.0 -1.0 0.0 1.0 2.0V (Volts)

0.0E+0

1.0E-10

2.0E-10

3.0E-10

4.0E-10

5.0E-10

6.0E-10

7.0E-10C

(F)

Cd/CdS/n-GaAs/In T= 300 K

30 kHz

50 kHz

70 kHz

100 kHz

200 kHz

300 kHz

500 kHz

700 kHz

1000 kHz

2000 kHz

3000 kHz

400 kHz

-2.0 -1.0 0.0 1.0 2.0V (Volts)

5.0E-4

1.0E-3

1.5E-3

2.0E-3

2.5E-3

3.0E-3

3.5E-3

C-2(p

F)-2

Cd/CdS/n-GaAs/In T= 300 K

30 kHz

3000 kHz

-0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0V (Volts)

0

10000

20000

30000

40000

50000

Rs

(Ohm

)

Cd/CdS/n-GaAs/In T= 300 K

30 kHz

50 kHz

70 kHz

100 kHz

200 kHz

300 kHz

400 kHz

500 kHz

700 kHz

1000 kHz

2000 kHz3000 kHz

•

•

•

•

•

•

For 30, 300 1000 and 3000 kHz frequencies, the built in voltages are calculated as 0,402 eV, 0,465 eV 0,631eV and 0,685 eV, the effective barrier heights are are calculated as 0,681 eV, 0,742 eV 0,905 eV and 0,957 eV respectively. The calculated Vn, Nd, built in potentials and effective barrier height values from C-2–V are given in below table 1. The Series resistance values are calculated as a function of the frequency and given in “Fig. 5”

V. CONCLUSION

CdS thin film has been directly growth on n-GaAs substrate by using SILAR method. For structural properties XRD and SEM measurements have been performed. The XRD and SEM studies reveal that the films are covered well with n-GaAs substrate and exhibit polycrystalline characterization. From optical absorbance measurements the energy band gap value is found as 2.3 eV for CdS thin film. For electrical properties, C-V measurements have been done as a function of the frequency. The effective barrier height values have been calculated from C-V measurements as 0.681 ev for 30 kHz and 0.957 eV for 3000 kHz. According to the electrical characterization results, in the future, it can be used rectifying contacts, integrated circuits, the other electronic devices and so on.

ACKNOWLEDGMENT

This work was supported by the Turkish Scientific and Technological Research Council (TUBITAK) (Project number: 108T500). The Authors wish to thank to TUBITAK.

REFERENCES [1] A. Ateş, M. A. Yıldırım, M. Kundakçı, and M. Yıldırım, “Investigation

of Optical and Structural Properties of CdS Thin Films” Chinese Journal of Physics Vol. 45, No. 2-I (2007), 135.�

[2] M. Saglam, A. Ates, B. Guzeldir, A. Astam, M.A. Yıldırım. Effects of thermal annealing on electrical characteristics of Cd/CdS/n-Si/Au–Sandwich structure 484 (2009) 570–574

[3] W. Monch, Semiconductor Surfaces and Interfaces, third ed., Springer- Verlag Press, 2001.

[4] A. Van der Ziel, Solid State Physical Electronics, second ed., Prentice-Hall, New Jersey, 1968

[5] J. I. Pankove, Optical Process in Semiconductors, Dover, New York, (1971) 34.

[6] A. S. Khomane, “Morphological and opto-electronic characterization of chemically deposited cadmium sulphide thin filmsJ. Alloys Compd. 496 (2010) 508–511.

[7] H. M. Pathan and C. D. Lokhande, “Deposition of metal chalcogenide thin films by successive ionic layer adsorption (SILAR) method” Bull. Mater. Sci. 27 (2004) 85–111.

[8] K. Kudo, “Organic light emitting transistors” Curr. Appl. Phys. 5 (2005) 337–340.

F(kHz) Vd(eV) Nd(cm-3)

Vn

(eV) Фb(eV) 30 0,402 1,432E+18 0,279 0,681 50 0,407 1,456E+18 0,279 0,686 70 0,409 1,673E+18 0,278 0,687

100 0,411 1,681E+18 0,278 0,689 200 0,421 1,693E+18 0,277 0,698 300 0,465 1,712E+18 0,277 0,742 400 0,471 1,734E+18 0,276 0,747 500 0,488 1,769E+18 0,275 0,763 700 0,532 1,813E+18 0,274 0,806 1000 0,631 1,890E+18 0,274 0,905 2000 0,645 1,911E+18 0,274 0,919 3000 0,685 1,988E+18 0,272 0,957

Figure3. Current–voltage characteristics for Cd/CdS/n-GaAs/In sandwich structure at different frequencies in the range 30-3000 kHz

Figure 4. C-2-V graph of Cd/CdS/GaAs/In sandwich structure

Fig. 5 Series resistance values as a function of frequency

Table I. The parameters obtained from reverse bias C-2 -V characteristics of the Cd/CdS/n-GaAs/In structure as a function of frequency.