cicc 2001 - reducing multiple design flow support requirements with ola

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Philips Semiconductors

2001 Custom Integrated Circuits Conference

CICC 2001 - Wednesday May 9thALF/OLA Panel Discussion

OLA: A New Standard in the EDA World or another car wreck on the side of the EDA road(map)

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Multiple Design Flows:Reducing Support Requirements

with OLA

Timothy J. Ehrler, Senior Principal

ASIC Technical Programs Manager

Design Technology Group


[email protected]

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• Must support many design flows

– flows are driven by design applications

• ASIC high performance

• mixed signal, analog

• low power (wireless)

• RF design

– different design flows require different sets of tools

• Must support many tools within a design flow

– many tools within the sub-flows (synthesis, etc.)

– multiple tools => multiple file formats

Current Plight of the ASIC Vendor

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• Information comes from a variety of sources

– multiple characterization tools with different file formats

– internal general/specific library packages

– internal/external (3rd party) memories, complex cores, IP

• Must support many libraries

– multiple technologies and processes

– multiple sets of libraries

• core, I/O, memories

• high- and low- VT

• protected and unprotected

• complex cores (embedded processors, DSP, etc.)

• specialty, IP

Current Plight of the ASIC Vendor (2)

TunnelRX TX

DTL Conc

TX RXTunnel

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Impact on Design Flow Support

• Many formats required to enable supported tools

– multiple sources for characterization/view information

– not necessarily 1st generation views from available information

– inconsistent interpretation/view by tools from same vendor

• multiple library “flavors” required by different vendor tools

• Qualification process for each tool/library combination

– verification of tool/library interoperability

– consideration of impact on subsequent tools in flow

– preliminary and tactical libraries may not be fully qualified

• resource availability may restrict/reduce verification

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Impact on Design Flow Support (2)

• Support and qualification requirements ever increasing

– new technologies and processes constantly being introduced

– new tools, or additional capabilities therein, always added

– additional design flows may be required as applications dictate

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Typical Design Flow

SPECContents:RTL Simulation

Architectural AnalysisBus interfaces

Software code developmentRSP platform (Velocity™, Nexperia™)

Feasibility: Performance, Area,

Power, Clocking, Test management

IPBehavioral RTL

Design

RTL DescriptionContents:Block level synthesis

Create top level design (CPU, DSP,

analog, memory, IP templates (HDLi™), I/O, schematics)

DFT (scan insertion, MBIST, JTAG, padring)

Floorplanning

Library Models

Functional Design

Structural Netlist

Contents:Delay Calculation

Static Timing AnalysisGate-level Simulation

Power EstimationNetlist Screener

Verification of specification

Layout

Logic & TimingVerification

Library Models

Test ProgramGeneration

SDB

Contents:Cell and Block P&R

Timing driven extensions

LDB

Ref Libs Layout:Cell & Block

Ref Libs

Contents:Hierarchy planning

Automatic flatten for P&R

pre-route P/G, clock nets

Area estimation

Partitioning &Floorplanning

LDB

Ref LibsLayout:

Chip AssemblyDesign Finishing

LDB GDS-IILib Rules,

Timing,Package

Contents:Insert core & pad fillers

Symbolic verification

Bond diagram

Verification

Contents: DRC, LVS, Plots, Extraction, Circuit

Simulation, Back-annotation & Timing Analysis

To Factory Finishand Mask Making

multiple & proprietary file formatsmultiple & proprietary file formats

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OLA Support of Design Flow

OLA(API)

OLA(API)

OLACompliant

Library

includesTiming

andPower

CalculationRoutines

Synthesis

Static Timing

Design for Test

Floorplanning

Place & Route

Semiconductor Sign-Off

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OLA Impact on Design Flow Support

• Major Reduction in Supported File Formats

– corresponding reduction of generation/verification requirements

• eliminate generation/translation tool requirements

• reduce generation & verification resources (h/w, personnel, time)

• Even Greater Savings for Multiple Libraries

– relative to OLA Replaceable/Deleteable numbers

• 16 libraries per technology ~= 16-fold reduction

• dependent on tool set choices and interfaces

Design Process Tools Standard /Proprietary

Formats

TotalFormats

OLAReplaceable/

Deleteable

TotalFormats

FormatReduction

RTL Development/Analysis 5 3/0 3 2/0 2 33%Design Synthesis 7 4/6 10 4/1 6 40%

Logic/Timing Verification 17 5/11 16 6/5 6 63%Partitioning & Floor Planning 11 3/9 12 5/0 8 33%

Layout & Chip Finishing 21 4/15 19 6/2 12 37%

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Multiple Design Flows

RTL Development/AnalysisRTL Development/Analysis

Sub-FlowSub-Flow

Sub-FlowSub-Flow

Sub-FlowSub-Flow

Sub FlowSub Flow

Sub-FlowSub-Flow

Sub-FlowSub-Flow

Sub-FlowSub-Flow

Sub-FlowSub-Flow

Sub-FlowSub-Flow

Sub-FlowSub-Flow

Sub-FlowSub-Flow

Sub-FlowSub-Flow

Sub-FlowSub-Flow

Des

ign

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IP

Flow A Flow B Flow C

Design SynthesisDesign Synthesis

Logic/Timing VerificationLogic/Timing Verification

Partitioning & Floor PlanningPartitioning & Floor Planning

Layout & Chip FinishingLayout & Chip Finishing

• Define Methodologies

– design requirement driven

– drives design processes

• Define Specific Flows

– design application driven

– drives sub-flow tool types

• Determine Specific Tools

– drives library requirements

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OLA Impact on Multiple Design Flows

• Significant Reduction in Supported File Formats

– proportional generation/verification savings

• impacted by number of libraries

• dependent on sub-flow tool choices

• Easier Introduction of Subsequent Flows & Tools

– reduced/eliminated generation/verification requirements

• great impact on tool evaluation requirements and resources

• Faster Introduction of Additional Libraries

– efforts focused primarily on library validation, not tools

• eliminates many flow-dependent verification processes

• Reduced Impact on Previously Released IP

– eliminates IP package updates for additional flows & tools

– ensures stability of released IP during design development

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Summary & Conclusion

• OLA allows the ASIC vendor to be more productive

– reduced number of supported file formats

– reduction in qualification time

– allows easier and faster introduction of new technologies

– encourages 3rd party IP generation

• OLA provides EDA vendor easier entry into design flows

– OLA compliant tools don’t require exhaustive library verification

– ASIC vendor doesn’t need to generate/qualify “another format”

– consistent “behavior” of library eliminates convergence issues

• The OLA standard is a WIN-WIN for ASIC and EDA vendors

cicc 2001 - reducing multiple design flow support requirements with ola

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