cjtag: enhancement to ieee 1149.1 uses concurrent test to...

1Board Test Workshop 2006

CJTAG: Enhancement to IEEE 1149.1 uses concurrent test to reduce test times

CJTAG: Enhancement to IEEE 1149.1 uses concurrent test to reduce test times

CJ Clark is the President and CEO of Intellitech Corporation.

He was the elected chairperson of the IEEE 1149.1 JTAG working group from 1996 to 2002. He has been active in other IEEE working groups and has presented at International Test Conference, TECS (Testing Embedded Cores-Based Systems) Workshop, the Board Test Workshop, Ottawa Test Workshop and VLSI Test Symposium.

CJ serves on the University of New Hampshire College of Engineering and Physical Science (CEPS) Advisory Board. He also serves on the UNH Department of Electrical Engineering Advisory Board. He is co-inventor on two US, two Canadian, one Taiwanese patent with others pending world-wide. His first job in test was in 1978 with Plantronics/Wilcom.

CJ Clark is the President and CEO of Intellitech Corporation.

He was the elected chairperson of the IEEE 1149.1 JTAG working group from 1996 to 2002. He has been active in other IEEE working groups and has presented at International Test Conference, TECS (Testing Embedded Cores-Based Systems) Workshop, the Board Test Workshop, Ottawa Test Workshop and VLSI Test Symposium.

CJ serves on the University of New Hampshire College of Engineering and Physical Science (CEPS) Advisory Board. He also serves on the UNH Department of Electrical Engineering Advisory Board. He is co-inventor on two US, two Canadian, one Taiwanese patent with others pending world-wide. His first job in test was in 1978 with Plantronics/Wilcom.

Board Test Work Shop 2006

ASICU2

FPGAU1

U3 FPGA

+

+

1.8V

LVDS

SerialEEPROMFACBERT

BERT

GigabitSerial

FAC

FLASH

TemporarilyDownloadedAnd accessed via 1149.1

TemporarilyDownloadedAnd accessed via 1149.1

=

DDRRAMFCRAM Mem

BIST

Problem: 1149.1 Data Volume required for test continues to growProblem: 1149.1 Data Volume required for test continues to grow

Not just high-volume products are a problem.Low volume products with fast turn-aroundLow volume products which require 1149.1 During burn-in or ESS

Stand-alone 1149.1 test when 1149.1 on ICT isn’t appropriate for cost and speed reasons

Not just highNot just high--volume products are a problem.volume products are a problem.Low volume products with fast turnLow volume products with fast turn--aroundaroundLow volume products which require 1149.1 Low volume products which require 1149.1 During burnDuring burn--in or ESSin or ESS

StandStand--alone 1149.1 test when 1149.1 on ICT alone 1149.1 test when 1149.1 on ICT isnisn’’t appropriate for cost and speed reasonst appropriate for cost and speed reasons


TT = 10 sec TT = 10 sec TT = 10 sec

TRSTTCKTMSTDITDO

1149.1 Controller

Total TCKs = 1x108 + 1x108 + 1x108 = 3x108

30 seconds at 10Mhz

TDI TMS TCK TDOTRST* TDI TMS TCK TDOTRST* TDI TMS TCK TDOTRST*

Can perform ‘concurrent test’ with traditional 1149.1- However it is 0% efficient, test times increase linearly

IEEE 1532 “Concurrent Programming” is ‘Concurrent Waiting’ not concurrent test”

Can perform ‘concurrent test’ with traditional 1149.1- However it is 0% efficient, test times increase linearly

IEEE 1532 “Concurrent Programming” is ‘Concurrent Waiting’ not concurrent test”


Goals: Goals: Shorten test times of systems with multiple PCBs & standShorten test times of systems with multiple PCBs & stand--alone PCBsalone PCBs

--without cost of multiple software/PC/hardwarewithout cost of multiple software/PC/hardware-- Performing concurrent test with onPerforming concurrent test with on--boardboardCPU/CPU/eTBCeTBC and stored patterns (flash) not lightweightand stored patterns (flash) not lightweightand not suitable for small PCBs or onand not suitable for small PCBs or on--PCB FLASH PCB FLASH programmingprogramming-- enable PCBenable PCB--toto--PCB interconnect tests for systemsPCB interconnect tests for systems

Enable concurrent test/Enable concurrent test/progprog for multiple circuits on a single PCBfor multiple circuits on a single PCB

Make light weight Make light weight –– for Wafer level DIE/IC testfor Wafer level DIE/IC test-- small enough so solution can fit in thesmall enough so solution can fit in thescribe lines of wafer if necessaryscribe lines of wafer if necessary

--Single interface from external ATESingle interface from external ATE

Preserve individual UUT accessPreserve individual UUT access

Make data transmission medium independent for large systemsMake data transmission medium independent for large systems-- use with wires, USB, Ethernet, SERDESuse with wires, USB, Ethernet, SERDES


TRSTTRSTTMSTMSTCKTCKTDOTDOTDITDI

System Level Scan Chain Design1149.5 dead, withdrawn from IEEEMust use so called ‘multi-drop’ 1149.1 bus

TDI and TDO are bussed and common to all PCBsOpen slots do not break scan chain‘address-able’ IC on each PCB to control which PCB is using TDO

System Level Scan Chain DesignSystem Level Scan Chain Design1149.5 dead, withdrawn from IEEE1149.5 dead, withdrawn from IEEEMust use so called Must use so called ‘‘multimulti--dropdrop’’ 1149.1 bus1149.1 bus

TDI and TDO are bussed and common to all PCBsTDI and TDO are bussed and common to all PCBsOpen slots do not break scan chainOpen slots do not break scan chain‘‘addressaddress--ableable’’ IC on each PCB to control which PCB is using TDOIC on each PCB to control which PCB is using TDO


TDI TMS TCK TDO

ADDR

LFSR

TRST*

ScanBridge/ASP

TDI TMS TCK TDO

ADDR

LFSR

TRST*

ScanBridge/ASP

TDI TMS TCK TDO

ADDR

LFSR

TRST*

ScanBridge/ASP

TT = 10 sec TT = 10 sec TT = 10 sec

Total Test Time= 30 sec

1 2 3TDOTCKTMSTDITRST

1149.1 Controller

LSP1 LSP2 LSPN

Early Commercial Addressable IC or Early Commercial Addressable IC or ‘‘GatewaysGateways’’-- some attempts to solve the concurrent test problemsome attempts to solve the concurrent test problem-- ‘‘apply onlyapply only’’ broadcast mode & LFSRbroadcast mode & LFSR

SB/ASP/look-alikes don’t have intelligence- they continue to program a FLASH or run

an interconnect on the board regardless offailures encountered.


Total Test Time = ~10 sec = 10secs plus failure extraction time (if any)

TDOTCKTMSTDITRSTEXPMASK

CJTAG Controller

1

ADDR

CJTAG IC

TT = 10 sec

LSP1 LSP2 LSPN

ADDR

CJTAG IC

TT = 10 sec

LSP1 LSP2 LSPN

ADDR

CJTAG IC

TT = 10 sec

LSP1 LSP2 LSPN

2 N

CompareCircuit

CompareCircuit

CompareCircuit

Parallel Test Bus

Support for “Broadcast” mode – TDO = Z1149.1 control of Compare Circuit1149.1 (FAC) access to Results“Brake” to shut off paths on failures or At end of test (SVF for instance) to preservediagnostics

Support for “Broadcast” mode – TDO = Z1149.1 control of Compare Circuit1149.1 (FAC) access to Results“Brake” to shut off paths on failures or At end of test (SVF for instance) to preservediagnostics


MASK

TRST*

SAD[7:0]

TAD[7:0]

Instruction Register

BOUNDARY

TDI

EXP

BypassDevice ID

Results

Enable

MDIEDI ADI

PATH SELECT

CJTAG_ON*

SHIFTIR*SHIFTDR* Enable

Enable

SLOT_ADDR

TAPController

ClockIRUpdateIRShiftIR*Reset*SelectTDOENShiftDR*UpdateDRClockDR

TMS

TCK

TDO

LSP0 LSP1 LSPN

UUT_TYPE_ADDRALIAS/GROUP_ADDRCJTAG_CFG/CMP CNTRL

FAILSHIFTIR*SHIFTDR* LSP

TLRSHIFTIR*SHIFTDR* LSP

TLR

. . .

CMP

Local Scan Path Matrix

Path Select

TDOTDI Brake

TRST* TMS TCK


In Multi-drop 1149.1, TDO is not active during Shift-DR, Shift-IR

And Asynchronous TRST pin is unused during Shift-DR, Shift-IR

In MultiIn Multi--drop 1149.1, TDO is not active during Shiftdrop 1149.1, TDO is not active during Shift--DR, ShiftDR, Shift--IRIR

And Asynchronous TRST pin is unused during ShiftAnd Asynchronous TRST pin is unused during Shift--DR, ShiftDR, Shift--IRIR

Test-Logic-Reset

Run-Test/Idle Select-DR-Scan Select-IR-Scan

Capture-DR

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

Update-DR

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Exit2-IR

Update-IR

1

0

0 111

0

0

0 1

0

1

1

01

1

0

0

0

1

0

1

1

01

0

01

00

1 1


•• 5 Wire multi5 Wire multi--drop 1149.1 bus drop 1149.1 bus --still compatible ASP & Scan Bridgestill compatible ASP & Scan Bridge••SB and CJTAG device have to have same IR lengthSB and CJTAG device have to have same IR length

•• TDO pin becomes Bidirectional (normally triTDO pin becomes Bidirectional (normally tri--state output)state output)•• Similar PCBs tested and configured In parallelSimilar PCBs tested and configured In parallel

If the PCB test/programming time is 2 minutesIf the PCB test/programming time is 2 minutesThen six similar PCBs in the system would be 2 minutesThen six similar PCBs in the system would be 2 minutestest time, not 12 minutes as it would be with ASP ortest time, not 12 minutes as it would be with ASP orScanBridgeScanBridge

•• Scan Out data always compared locally, not sent back to controlScan Out data always compared locally, not sent back to controllerlerUnless Unless …… in single PCB mode.in single PCB mode.

•• Parallel Access, but individual access preservedParallel Access, but individual access preserved–– Program unique serial numbersProgram unique serial numbers

Make CJTAG 5 1149.1 signal compatibleMake CJTAG 5 1149.1 signal compatible


Total Test Time = ~10 sec TDO becomes bidirectionalTotal Test Time = ~10 sec TDO becomes bidirectional

TDO/EXPTCKTMSTDI

TRST/MASK

1

ADDR

CJTAG IC

TT = 10 sec

LSP1 LSP2 LSPN

2

ADDR

CJTAG IC

TT = 10 sec

LSP1 LSP2 LSPN

N

ADDR

CJTAG IC

TT = 10 sec

LSP1 LSP2 LSPN

CompareCircuit

CompareCircuit

CompareCircuit

Parallel Test Bus

CJTAG Controller


MASKTRST*

SAD[7:0]

TAD[7:0]


BOUNDARY

TDI

EXP

BypassDevice ID

Results

EnableMDI EDI

ADI

PATH SELECT

CJTAG_ON*

SHIFTIR*SHIFTDR*

SLOT_ADDR

TAPController


TMS

TCK

TDO

LSP0 LSP1 LSPN

UUT_TYPE_ADDRALIAS/GROUP_ADDRCJTAGCFG/CMPCF/LINK

FAIL SHIFTIR*SHIFTDR* ATL

TLRSHIFTIR*SHIFTDR* ATL

TLR

CMP


Path Select

TDOTDIBrake

TRST* TMS TCK

EnableOR

TRST*

TDOEN1

TDOEN1

Enable


MultiMulti--drop bus major disadvantage is that as PCBsdrop bus major disadvantage is that as PCBsAre added, each PCB is seen as a capacitive load.Are added, each PCB is seen as a capacitive load.

Each Each ‘‘addressaddress--ableable’’ IC has IC has ‘‘stubstub’’(trace length from IC to Backplane connector )(trace length from IC to Backplane connector )

Connector capacitance, pitch etc. affect JTAG signal Connector capacitance, pitch etc. affect JTAG signal integrity and max TCK frequencyintegrity and max TCK frequency

Beyond 4Beyond 4--8 PCBs, TCK rates drop, affecting throughput and 8 PCBs, TCK rates drop, affecting throughput and increasing total test timeincreasing total test time

-- testing two testing two UUTsUUTs at at ½½ max TCK is no bettermax TCK is no betterthan one at the max TCK.than one at the max TCK.

Anecdotal evidence shows large systems with ASP/Scan Anecdotal evidence shows large systems with ASP/Scan Bridge on 20+ PCBs have TCK rates < 10Mhz, sometimes < Bridge on 20+ PCBs have TCK rates < 10Mhz, sometimes < 2Mhz2Mhz


CJTAG approach enables MultiCJTAG approach enables Multi--Drop SegmentationDrop Segmentation

••Higher TCK ratesHigher TCK rates••rere--synchronization of 1149.1 signals reduce skewsynchronization of 1149.1 signals reduce skew

••Minimize loads Minimize loads –– as few as one load per driveras few as one load per driver••As you choose to implementAs you choose to implement

••Extends and repeats CJTAG busExtends and repeats CJTAG bus……as much asas much asaddressing size will allow. 8bits = 255 addressing size will allow. 8bits = 255 UUTsUUTs,,Address = N, then 2**N Address = N, then 2**N UUTsUUTs

Synchronizer is controlled by CJTAG addressSynchronizer is controlled by CJTAG addressto determine when TDO must be enabled to sendto determine when TDO must be enabled to sendData back to controllerData back to controller


MASKTRST*

SAD[7:0]

TAD[7:0]


BOUNDARY

TDI

EXP

BypassDevice ID

Results

EnableMDI EDI

ADI

PATH SELECT

CJTAG_ON*

SHIFTIR*SHIFTDR*

SLOT_ADDR

TAPController


TMS

TCK

TDO

LSP0 LSP1 LSPN

UUT_TYPE_ADDRALIAS/GROUP_ADDRCJTAGCFG/CMPCF/LINK

FAIL SHIFTIR*SHIFTDR* ATL

TLRSHIFTIR*SHIFTDR* ATL

TLR

CMP


Path Select

TDOTDIBrake

TRST* TMS TCK

EnableOR

TRST*

TDOEN1

Enable

TDOEN1

TCK

TDI

TMS

TDO/EXP

TDI_LINK

TMS_LINK

TRST*/MASK_LINK

TDO/EXP_LINK

TCK_LINK

SYNCTRST*/MASK_LINK

TDO/EXP

ATL_LINK


TCK

TDI

TMS

TRST*/MASK

TDO/EXP

SRC_REG LNK_REG TDI_LINK

TMS_LINK

TRST*/MASK_LINK

TDO/EXP_LINK

TCK_LINKEnable

Enable

D Q

D Q

D Q

D Q

D Q

D Q

D Q

D Q

Q DQ D

TCK

TDI

TMS

TRST*/MASK

TDO/EXP

SRC_REG LNK_REG TDI_LINK

TMS_LINK

TRST*/MASK_LINK

TDO/EXP_LINK

TCK_LINKEnable

Enable

D Q

D Q

D Q

D Q

D Q

D Q

D Q

D Q

Q DQ D


PATH0

PATH1

PATHN

PATH0

PATH1

PATHN

ADDR

ADDR

6

… …

TRST TMS TCK TDITDO TRST TMS TCK TDITDO TRST TMS TCK TDITDO

PATH0

PATH1

PATHN

PATH0

PATH1

PATHN

ADDR

ADDR

3 4

… …

TRST TMS TCK TDITDO

CJTAG ICTRST TMS TCK TDITDO TRST TMS TCK TDITDO

Segmented PTB Bus in BackplaneSegmented PTB Bus in Backplane

CJTAG IC CJTAG IC CJTAG IC

1 2 3 4

1 TCK delay fromPCB 1 & 21 TCK delay fromPCB 1 & 2


Advantages:PCB are not physically far from the 1149.1 driver – in this caseno more than 1 slot awayIn this design no more than two loads seen by 1149.1 driver(s)Easier to achieve propogation time of < 1/2TCK period


N

Some added benefits:PCBs do not go through UPDATE-DR at the same timeWe get concurrent test, without the major disadvantage Of traditional concurrent test and that is in-rush current requirements

Some added benefits:PCBs do not go through UPDATE-DR at the same timeWe get concurrent test, without the major disadvantage Of traditional concurrent test and that is in-rush current requirements

Aha! But now the scan-chain is broken if a card is missing!-Can be overcome with DFT – using ‘sync’ onFixed slots (known card is present)-In practice dummy cards are usedSystems today: point-to-point (SERDES) not Large passive parallel bplaneMany have mechanical/Cooling requirements to have the slot populated with something

Aha! But now the scan-chain is broken if a card is missing!-Can be overcome with DFT – using ‘sync’ onFixed slots (known card is present)-In practice dummy cards are usedSystems today: point-to-point (SERDES) not Large passive parallel bplaneMany have mechanical/Cooling requirements to have the slot populated with something


PATH0

PATH1

PATHN

PATH0

PATH1

PATHN

ADDR

ADDR

6

… …

TRST TMS TCK TDITDO TRST TMS TCK TDITDO TRST TMS TCK TDITDO

PATH0

PATH1

PATHN

PATH0

PATH1

PATHN

ADDR

ADDR

3 4

… …

TRST TMS TCK TDITDO

CJTAG ICTRST TMS TCK TDITDO TRST TMS TCK TDITDO

Segmented PTB Bus in BackplaneSegmented PTB Bus in Backplane

CJTAG IC CJTAG IC CJTAG IC

1 2 3 4





N


ResultsResults

$5.8374%123s476s*W=105s, R=14 s

10Mhz16AFlashProgramming system

D

$6.4584%69s456sS=1, I=65s

10Mhz1S + 7IcPCI system

C

$1.8074%41s152s*38secs5Mhz16TTelecom PCB in‘mockup’ backplane

B

$4.5681%64s338sS = 25s, I = 36s

20Mhz2S + 8ITelecom System

A

Est. Cost savings per test

run

Test Time Reduction

CJTAG Test Time

1149.1Test Time

Test/ConfigTime per

PCB

TCK Freq.

PCB Configuration(board types)

System Description

$5.8374%123s476s*W=105s, R=14 s

10Mhz16AFlashProgramming system

D

$6.4584%69s456sS=1, I=65s

10Mhz1S + 7IcPCI system

C

$1.8074%41s152s*38secs5Mhz16TTelecom PCB in‘mockup’ backplane

B

$4.5681%64s338sS = 25s, I = 36s

20Mhz2S + 8ITelecom System

A

Est. Cost savings per test

run

Test Time Reduction

CJTAG Test Time

1149.1Test Time

Test/ConfigTime per

PCB

TCK Freq.

PCB Configuration(board types)

System Description

S = System Board I = I/O Board T=Telecom A= Automotive

* Note: Test Time using 1149.1 controller with four independent scan-chains

4 Port Controller could not perform diagnostics in‘concurrent’ mode. Some failures could not be repeated.On re-running the test.

4 Port Controller could not perform diagnostics in‘concurrent’ mode. Some failures could not be repeated.On re-running the test.


TDO/EXPTCKTMSTDI

TRST/MASK

CJTAG Controller

DDRDDRDDR

DSP

DDRDDRDDRDDR

DSP

DDRDDRDDRDDR

DSP

DDR

DDRDDRDDR

DSP

DDR

DDRDDRDDR

DSP

DDR

DDRDDRDDR

DSP

DDR

DDRDDRDDR

DSP

DDR

DDRDDRDDR

DSP

DDR

CJTAG IC

CJTAG for concurrent test/programming on a single PCBCJTAG for concurrent test/programming on a single PCB


ATL TLRATL TLR

ATL TLRATL TLRMASK

TRST*

SAD[7:0]


BOUNDARY

TDI

EXP

BypassDevice ID

Results[n:1]

EnableMDI

EDIADI[n:0]

PATH SELECT

CJTAG_ON*

SHIFTIR*SHIFTDR*

SLOT_ADDR

TAPController


TMS

TCK

TDO

LSP0 LSP1 LSPN

ATL_ADDR[n:0]CJTAGCFG/CMPCF

FAIL[n:0] SHIFTIR*SHIFTDR* ATL0

TLRATL0 TLR

CMP

Path Select

TDO

TDIBrake[n:0]

TRST* TMS TCK

EnableOR

TRST*

TDOEN1

TDOEN1

Enable


ATL0

ATL_ADDR[n:0]

ATL1 ATLN


1149.1 Controller

1149.1 Controller

1149.1 Controller

Shared Fixed Bandwidth of Host

Fixed Bandwidth

Some controllersw/o diagnostics

CJTAGController

PTB

Fixed Bandwidth of Host

Fixture/Test Equipment Add-on

1149.1 Controller

Scalable Bandwidthw/ Diagnostics

NthCJTAG

IC


1

ADDR

CJTAG IC

LSP1 LSP2 LSPN

ADDR

CJTAG IC

LSP1 LSP2 LSPN

ADDR

CJTAG IC

LSP1 LSP2 LSPN

WirelessTransceiver

WirelessTransceiver

WirelessTransceiver

2 N

TRST

TMS

EXP

MASK

TDI

Broad architecture – not wires can implement in Ethernet, PCI bus, USB, I2C or wireless as technology permits


Thank You!

Thanks to my co-inventor Mike Ricchetti

Thanks to Bill Eklow for the opportunity to present

Thanks to Chen-Huan Chiang for paper review

Now for Questions

Thank You!Thank You!

Thanks to my coThanks to my co--inventor Mike inventor Mike RicchettiRicchetti

Thanks to Bill Eklow for the opportunity to Thanks to Bill Eklow for the opportunity to presentpresent

Thanks to ChenThanks to Chen--HuanHuan Chiang for paper reviewChiang for paper review

Now for QuestionsNow for Questions

cjtag: enhancement to ieee 1149.1 uses concurrent test to...

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