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Copyright © 2016 PCI-SIG® - All Rights Reserved

o Rubaiyat Islam

o AMD

PCIe® Electrical Basics


2Copyright © 2016 PCI-SIG® - All Rights ReservedPCI-SIG Developers Conference 2016

Topics

o PCI Express® Overview

o Enhancements for 8GT/s

o Target Channels for the Specification

o Electrical Signaling

o Transmitter

o Receiver

o Reference Clock

o Card Electro-mechanical (CEM) Spec



Electrical Features

o Data rates 2.5GT/s, 5GT/s, 8GT/s and 16 GT/s

o 10-12 bit error ratio

o AC coupled

o Link widths 1, 2, 4, 8, 16, 32 lanes

o Hot swap capable

o 2.5 and 5GT/s scrambled + 8b10b

o 8GT/s, 16 GT/s scrambled + 128/130

o Power management



Doubling from 5GT/s

o Major goal was to make PCIe® 3.0 evolutionary• Support existing usage models

• Preserve Common Reference Clock and Data Clocked modes

• Re-use of 5GT/s reference clock generators

• Re-use of silicon PHY architectures

o Evaluated channels at 10GT/s and 8GT/s• 10GT/s would have allowed 8b10b coding to be preserved

o Shown that a non-linear increase in difficulty to reach 10GT/s• Increased channel improvement cost

• Increased power in silicon

• Increased difficulty for eco-system

o Concluded the cost of changing encoding acceptable• A new scrambled encoding scheme was developed

• Efficiency 20% better than 8b10b



8GT/s Enablers

o Receiver equalization required

o Introduce statistical channel analysis• Channel compliance & simulation with behavioral Tx/Rx

o Mitigate baseline wander & crosstalk• Polynomial choice of 128/130 code on individual lanes

• Baseline wander:

• LFSR offsets between adjacent lanes reduces simultaneous switching

time

lan

e

Red: vict+2aggr; pink: vict+1aggr; black: vict only



Target Channels



PCI Express® Channels

o Channel specification• No formal spec for 2.5 and 5GT/s

• Channel budget implied

• 8GT/s introduces time domain spec

• Card Electromechanical (CEM) spec sets limits and measurement points

o Two worst case models assumed• Client CEM

• Short to medium length (3-12”), reflection and crosstalk dominated

• Server CEM

• Medium to long (20”) loss dominated



Client Channel

Typical Client Topology

4-layer microstrip 3-7” with PTH via stubs

Add in card 3-4”



Server Channel

Typical Server Topology

6- 8 layers, 20”, 1 or 2 connectors

Stripline with via stubs



High Speed Channel Simulation

Challenges

o Channel response at >4GHz is affected by

large number of features in the channel

• Pre-layout evaluation of topology choices is a complicated

multi-dimensional problem

• Need to be able to quickly build and test many different

options

• Large number of HVM permutations need to be evaluated

to determine robustness of solution

o Seasim has been developed to allow EWG

members to efficiently evaluate these options



Electrical Signaling



Transceiver and Channel

Channel

Optional

on-die AC coupling for

8b10b

8GT/s allows floating

Rx common-mode

Rx term

Tx EQ

2-tap 2.5/5GT/s,

3-tap 8GT/s

AC Coupled ChannelRx Detect

Tx

Tx

Rx

Rx

Tunable Rx EQ

8GT/s



Transmit De-Emphasis

VTx-Diff-PP

VTx-De-Emph-PP

FD Insertion Loss

Transmitter circuits use De-Emphasis

to equalize the frequency response of

the channel in order to minimize inter-

symbol interference

Available Equalization Settings:

2.5GT/s: [-3.5dB]

5.0GT/s: [-3.5dB, -6dB]

8.0GT/s: [-3.5dB, -6dB, pre-cursor]

* 10-presets

* Coefficient tuning space



De-Emphasis Pulse & Frequency

Domain Response

Inter Symbol

InterferenceReduced smearing into

next symbol UI

Flatened “equalized” response

263mV0.76UI 0.845UI282mV



Transmitter



Transmitter Reference Plane

o Reference plane is DUT pin

• Most convenient manufacturing boundary

o For 2.5 and 5GT/s

• Package losses are part of Tx performance

o For 8GT/s die pad, package route and package

pin interactions are more significant

• Makes fixture de-embedding inaccurate

• Tx EQ and jitter measurements inaccurate

o Use data-dependent jitter separation

• Effectively measure Tx jitter at die pad

• Use LF measurement technique for presets at pin



Transmitter

o Differential ~100ohm transmitter• FS: 800-1200mV, HS: 400-800mV

• 0.75UI eye opening

o 2.5/5GT/s 2-tap EQ• FS: -3.5dB and -6dB, HS: 0dB

o 8GT/s 3-tap EQ• 10 presets, min boost 8dB, coefficient tuning space

o AC coupled channel series capacitor• 2.5/5GT/s 75-265nF

• 2.5/5/8GT/s (Rev 3.0) 176-265nF

o Return Loss• SDD11 -10dB 2.5GT/s, -8dB 5GT/s, -4dB 8GT/s (differential)

• SCC11 -6dB, -3dB 8GT/s (common-mode)



Receiver



Receiver

o 2.5/5GT/s open eye specification, validated at device pin, package included in device budget• Eye height 175/120mV 2.5/5GT/s

• Eye width 0.4/0.32UI 2.5/5GT/s

• AC common-mode 300mV pk-pk

o 8GT/s closed eye at pin, specified after applying behavioral receiver• Defines minimum Rx EQ performance

• Used for both Rx stressed eye calibration and channel compliance

• Eye height 25mV 8GT/s

• Eye width 0.3UI 8GT/s

• AC common-mode 150mV pk-pk (EH<100mV) 250mV (EH>=100mV)



Receiver Cont.

o Termination

• 100ohm differential

• 50ohm common-mode

• 0v common-mode for detect

• At 8GT/s Rx allowed to float common-mode

• Requires LTSSM changes to avoid dead-locks

o Differential-mode return loss

• 10dB 2.5GT/s, 8dB 5GT/s, 5dB 8GT/s

o Common-mode return loss

• 6dB 2.5/5GT/s, 5dB 8GT/s



Behavioral Rx DFEBlock diagram of CTLE and 1-tap DFE

CTLE

Z-1d1

V-T Eye

Xk

Yk

Y*k



Rx Linear EQ

1 1 2 2

1 1 2 1 2 2 3

2

1 2

1 2

2

1 2

1 21

1 1 2

1

1 1

2

2 3

1( )

1

11

( )

1 1

1

1

Z

P P

DC

P

Z DC P

P

sC R R RH s

sC R R R R sC R

s

RH s

s sR R

RG

R R

R R

C R R

GC R

C R

R1 R2

C1

C2

R3Closer pole1 is to

4GHz the more

attenuation at bit

rate

Fully specified by

DCGAIN (dB)

FPOLE1 (Hz)

FPOLE2 (Hz)

8GT/s Tuning Range

1dB step size

8GT/s reference EQ params



CEM Specification



PCI Express 3.0 CEM Goals

o Same channel reach as for PCIe 2.0• Client: 14 inch, one connector

• Server: 20 inch, two connectors

o Full backwards interoperability with PCIe 1.x, PCIe2.0

o No required changes to the connectors, card form factors, or material

o Minimal or no changes to the measurement methodologies from those used in the PCIe 1.x/2.0 specifications • Use eye diagrams (jitter/voltage margin requirements).

Minimize additional new requirements



PCI Express 3.0

Channel Analysis

o Client• Motherboard and adapter• 1 PCIe connector• No vias other than connector• Routed as mstrip• Channel length: ~14”

o Server• Motherboard, riser card, and

adapter• 2 PCIe connectors• Several vias on motherboard• Routed primarily as stripline• Channel length: ~20”

o Channel analysis includes corner cases

Seg Description

A MCH PKG (transmitter)

B Break Out

C MB Main 7”

D MB post cap

E Add in card main 3”

F Add in card PKG Break out

G Add in card PKG (receiver)

ACB

DE

G

FTypical Client topology

2 Connector Server topology

PCIe 3.0 targets support for the same channels and lengths as PCIe 2.0



CEM Spec – TX Path

TXT

X

RX

RX

PCE

Conne

ctor

AC Coupling

Caps

System Board Add-in CardSystem Board TX

Add-in Card TXComponent

CEM Spec Defines TX Requirements for Chip + InterconnectNo Separate TX Chip Or Interconnect Only Requirements.



CEM Simulation Details

o Channels

• Worst case 2 connector 16” server MB

• Worst case 1 connecter 10” client MB

• 4” microstrip Add-in card.

o TX jitter following base spec limits

o Base spec package models for TX and RX packages

o Equalization

• Adaptive 2-tap (pre/post) TX LE

• Reference Equalizer - 1st order Adaptive RX CTLE + 1 Tap DFE

o Pass/Fail Decision for End To End (ETE) Simulations

• Base Spec RX test stressed eye (25 mV and .3 UI)



PCIe 3.0 CEM Simulation Method

Step 1: End to End (E2E) Simulations

o Perform E2E simulations• Use target 1 connector and 2 connector solutions

• Eye height (EH) and eye width (EW) examined after reference equalizer at eye pad

• CTLE + 1 tap DFE and base spec package structure.

• Pass/fail determined by base spec RX test stressed eye

• Statistical tools used for all simulations

o For each set of MB parameters determine worst case eye across expected add-in card solution space

o Repeat with many motherboards

Create a statistically significant

number of MB descriptions. (Vary

channel lengths, Tx params, etc.)

Various MB descriptions

Sweep add-in

card parameters

over reasonable

solution space



PCIe 3.0 CEM Simulation Method

Step 2: Test Fixture Simulations

o Choose a test fixture• 2.0 CLB Test Fixture Used For Initial Investigation

• CEM spec pathfinding work showed better correlation with worst case E2E results with fixture with package model vs 2.0 CLB

o Repeat previous MB simulations with test fixture • Determine an eye mask at compliance Test Point

• Find correlation between EH and EW at Test Point vs. E2E results

• Use TX presets only to match expected compliance test

o Optimize number of False Passes and False Fails

Text fixture with SMP

Connectors to ‘scope (CLB 3.0)

Statistically significant number of MB

Descriptions (same as E2E simulations)



Interpreting Simulation Results

Passing

Results

Failing

Results

“False

Failures”

“False

Passes”

Source: Intel Corporation



Client Tx E2E to CLB Eye

Height Correlation

Source: Intel Corporation

o E2E threshold at 25.0mV

o CLB threshold range

• 43 mv. No False Passes

• 27 mv. No False Failures



CEM TX Limits at 8 GT/s

o Test Channels

• MB TX Test Channel

• 4” 85 ohm trace + reference RX package

• AIC TX Test Channel

• 16” and 2 connectors + reference RX package

o CTLE + 1 Tap DFE reference Equalizer

o BER E-12 Limits (Same for AIC and MB)

• 34 mV

• .33 UI

o BER E-6 (Same for AIC and MB)

• 46 mV

• Informative – for simplified lab measurement use


Copyright © 2016 PCI-SIG® - All Rights ReservedPCI-SIG Developers Conference 2016

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Backup



Bidir TDR of 2-Connector Server

Channel

FCLGA Package

LGA SocketBGA Package

Connector transitions clearly visible in TDR data



8.0GT/s Statistical Channel Analysis

Statistical ISI

Analysis

ToolTx jitter

distribution

Lossy RxTx

Rx Sampling ClockTx Clock

Channel impulse

response

Equalization

coefficientsXtalk impulse

responses

Rx sample timing &

voltage uncertainty

distributions

5 10 15 20 25 30 35 40 45 500.02

0.04

0.06

0.08

0.1

0.12

0.14

0.16

Sample Time (psec)

Sa

mp

le V

olt

ag

e (

V)

Bit-error rate eye w ith transmit jitter (10X)

-20

-18

-16

-14

-12

-10

-8

-6

-4

-2

0

Pre-aperture

BER eye

Post-aperture

BER eye

5 10 15 20 25 30 35 40 45 500.02

0.04

0.06

0.08

0.1

0.12

0.14

0.16

Sample Time (psec)

Sam

ple

Vo

ltag

e (

V)

Bit-error rate eye with transmit jitter (10X)

-20

-18

-16

-14

-12

-10

-8

-6

-4

-2

0

8.0GT/s

specification

plane



Tx FIR EQ Definitions

0 0

is output voltage and the peak voltage

is number of Tx coefficients

is vector of +1 and -1 for logic 1 and 0

is the index into the bit stream

For a 3 tap Gen

and 1

TX PK

k k

n m n nTX PKn n

V V

k

d

m

V V c d c

1

0 2

0 0 1 1 2 2

0 1 2

0 1 2

0 1 2

0 1 2

0 1 2

3 FIR is positive and

and are negative

data is delayed by 1UI

For data stream 00010111

1 and ; ;

000

001

011

111

110

PK

c

c c

V t c t c t c

t t t

t t t

t t t Va

t t t Vb

t t t Vc

preshoot

deemphasis

Va

VbVc

VPK

10

10

20log

20log

Vbdeemphasis

Va

Vcpreshoot

Vb



PCIe 3.0 Tx Jitter

PWJ = PWmax-PWmin

Edge Jitter DJ= PWJ_DJ/2

Edge Jitter RJ = PWJ_RJ/√2

o PCIe 3.0 Tx jitter is separated into two categories• Data Dependent: package loss, reflections, ISI

• Uncorrelated Jitter: PLL jitter, power supply, duty cycle error

o Pulse Width Jitter (PWJ)• PWJ is a subset of uncorrelated jitter

• PWJ is amplified by channel loss

• Edges are assumed to be independent

o Relationship between pulse width jitter and edge jitter• Important for measurement and channel simulation tools



Receiver Compliance Testing

Stressed eye calibrated at pin reference plane

Error rate measured using loopback

Pass BER 10-12



8GT/s Calibration Channels

Frequency domain mask used for ISI stress to match tuning range of Rx EQ



8GT/s Receiver Jitter

Tolerance Testing

Validates that Rx can track LF jitter from refclk and Tx



Reference Clock



Common Reference Clock

Refclk SSC and LF jitter common-mode to Tx and Rx



Jitter Transfer Functions

o Bounds jitter for common reference clock architecture

• Data clocked architecture must operate with this jitter definition

o Multiplying PLL Tx/Rx bandwidth specified

• 2.5GT/s 1.5-22MHz 3dB peaking

• 5GT/s 5-16MHz 1-3dB peaking

• 8GT/s 2-5MHz 1-2dB peaking

o CDR bandwidths

• 2.5GT/s 1.5MHz 3dB HPF

• 5GT/s 1.5MHz brickwall HPF + SSC separation

• 8GT/s 10MHz 3dB HPF

o Transport delay

• ±12ns



Reference Clock Filtering

o A scope record of reference clock waveform is captured

• Record needs to include >10 SSC cycles

• Post processing calculates zero crossing times and phase demodulates against an ideal fitted clock

o Phase jitter record is filtered with the system jitter transfer functions and jitter measured

o Reference clock jitter spec after filtering using common-refclk jitter transfer functions

• 2.5GT/s: 108ps pk-pk (7.7ps RMS for spectrally flat jitter)

• 5GT/s: 3.1ps RMS

• 8GT/s: 1ps RMS

• Jitter reduction come mostly from improved system jitter transfer functions



Reference Clock

Jitter Filtering

As data rate increases

more of the refclk jitter

is rejected by system

jitter transfer functions

Refclk’s for 8GT/s

must be tested against

all combinations of PLL

bandwidths and jitter

peaking



Independent SSC Clocking ECN



Dual Port ConceptCEM MB Tx Testing

o How Does System Look With A Worst Case Spec Receiver?• Assume Common Clock Receiver

• Assume worst case legal receiver PLL and add-in card delay

o Can test with/without SSC

ChannelRefclk

Tx latch

Tx

PLL

Compliance

pattern

Motherboard under test

Channel

Worst Case

Spec Receiver

Use dual port to remove any issue testing with real clock or SSC



Package Test Fixture

Topology 4” test fixture

CEM spec pathfinding work showed better correlation with worst case E2E results with

fixture with package model on test fixture

Parameters shown for current CEM 3.0 CLB fixture proposal

S parameters for fixtures used in CEM simulations are published

CPAD

.8 pfCPIN

.25 pf

Package Parameters

CPAD = .8 pf

CPIN = 0.25 pf

Len = 1.3”

Z0 = 85 Ohms

T-line defined by

length, Z0, fixed/unit length loss

Base Spec RX Package Structure



PCIe 3.0 CBB Model

Name Description Name Description

cbb_conn1 Connector cbb_via Via

cbb_rt5 4.0” Riser cbb_rt7 10.0”, Main routing

cbb_conn2 Connector cbb_rt8 0.8”, Package Breakout

cbb_rt60.2”, Connector Breakout

rx_spkg Package, 1.3”

cbb_via

cbb_rt6

cbb_rt7

rx_spkg

cbb_conn2

cbb_rt8

RX SMP

cbb_rt

5cbb_rt

5

cbb_conn1TX SMP

Main Board

Riser Board



AIC RX Long

Channel Test Calibration

rx_spkg

cbb_conn2

RX SMP

cbb_conn1TX SMP

Test

Equipment

CLB 3.0

Post Processing S/W

(Embed RX pkg + use

behavioral EQ)

Signal

Generator

Sj + Rj +

Diff Noise

TXRX

o Calibration performed with optimal TX EQ for reference equalizer

o Calibration performed to MB TX EQ limits• Differential noise and Rj adjusted

to match eye

o No AC common mode• CEM test simplification

o Separate short channel test with PCIe 2.0 CLB/CBB



Proposed AIC RX

Long Channel Test

rx_spkg

cbb_conn2

RX SMP

cbb_conn1TX SMP

Error

Detector

AIC Under Test

Signal

Generator

Sj + Rj +

Diff Noise o Add-in card can request alternate TX EQ setting• Signal generator switches

without recalibration

o If test setup (single lane in loopback) does not produce worst case crosstalk – must compensate

o Test performed with direct path to loopback



Derivation of Coefficients

0 1 2 1 0 2

0 1 2 0 2

0 1 2 0

0 1 2 2

0 1 2 0 2

2

0

2 0

0 0 0

0 0

0

;

1; 1

1 2 2

1 2

1 2

1 2 2

1 2

1 2

2 1 1 2

1 2 1 1 2 2

1 2 1 2

2

PK

PK

PK

PK

Vb VcDE PS

Va Vb

t t t t t t

V t t t t tDE

V t t t t

V t t t tPS

V t t t t t

tDE PS

t

t DE PS t

t DE PS t tDE DE PS

t t

t

0

0 0 0

0

0

0

1 2

2 2 2

2 1

21

( 1)

2 2 ( 1)

DE PS DE t

t DE PS DE t DE t DE PS

t DE DE PS DE PS DE

DE PS DEt

DE PS DE

DE PSt

DE PS

2 0

2 0

2

2

2

2 2

2

2

2 1 1 2

2 1 2

( 1)2 1

1 ( 1)

1 ( 1) 1 ( 1)2

1 ( 1)

1 ( 1) ( 1) ( 1)2

1 ( 1)

12

1 ( 1

t DE PS t

t DE PS DE PSt

DE PSt DE PS DE PS

DE PS

DE PS DE PS DE PS PSt

DE PS

DE PS DE PS DE PS PS DE PS PSt

DE PS

DE PS DE PS DEt

DE PS

2

)

1

2 2 ( 1)

DEt

DE PS

PS

DE c0 c1 c2 c0 c1 c2 c0 c1 c2 c0 c1 c2 c0 c1 c2

0 0.000 1.000 0.000 -0.054 0.946 0.000 -0.103 0.897 0.000 -0.146 0.854 0.000 -0.185 0.815 0.000

-1 0.000 0.946 -0.054 -0.049 0.902 -0.049 -0.094 0.862 -0.044 -0.134 0.826 -0.040 -0.171 0.793 -0.036

-2 0.000 0.897 -0.103 -0.044 0.862 -0.094 -0.085 0.829 -0.085 -0.123 0.799 -0.077 -0.159 0.771 -0.070

-3 0.000 0.854 -0.146 -0.040 0.826 -0.134 -0.077 0.799 -0.123 -0.113 0.774 -0.113 -0.146 0.750 -0.103

-4 0.000 0.815 -0.185 -0.036 0.793 -0.171 -0.070 0.771 -0.159 -0.103 0.750 -0.146 -0.135 0.730 -0.135

-5 0.000 0.781 -0.219 -0.032 0.763 -0.205 -0.064 0.745 -0.191 -0.094 0.728 -0.178 -0.124 0.712 -0.165

-6 0.000 0.751 -0.249 -0.029 0.736 -0.235 -0.057 0.722 -0.221 -0.086 0.708 -0.207 -0.113 0.694 -0.193

-7 0.000 0.723 -0.277 -0.026 0.712 -0.262 -0.052 0.700 -0.248 -0.078 0.689 -0.234 -0.104 0.677 -0.219

-8 0.000 0.699 -0.301 -0.023 0.690 -0.287 -0.047 0.680 -0.273 -0.071 0.671 -0.258 -0.094 0.661 -0.244

-9 0.000 0.677 -0.323 -0.021 0.670 -0.309 -0.042 0.662 -0.295 -0.064 0.655 -0.281 -0.086 0.647 -0.267

-10 0.000 0.658 -0.342 -0.019 0.652 -0.329 -0.038 0.646 -0.316 -0.058 0.640 -0.302 -0.078 0.633 -0.289

0 1 2 3 4

Tx FIR Coefficients

click to edit master title style · created date: 6/24/2016 11:49:05 am

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