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Clock and Asynchronous Signals Z. Jerry Shi Computer Science and Engineering University of Connecticut University of Connecticut Thank John Wakerly for providing his slides and figures.

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Page 1: Clock and Asynchronous Signals

Clock and Asynchronous Signals

Z. Jerry ShiComputer Science and Engineering

University of ConnecticutUniversity of Connecticut

Thank John Wakerly for providing his slides and figures.

Page 2: Clock and Asynchronous Signals

Functional timing

Page 3: Clock and Asynchronous Signals

Delays in state machines

Setup-time margin = t_clk – t_ffpd_max – t_comb_max – t_setup > 0Hold-time margin = t_ffpd_min + t_comb_min – t_hold > 0

Page 4: Clock and Asynchronous Signals

Clock Skew

• Clock signal may not reach all flip-flops simultaneously• Output changes of flip-flops with “early” clock may reach D

inputs of flip-flops with “late” clock too soon

Reasons for slowness:(a) wiring delays( ) g y(b) capacitance(c) incorrect design

Page 5: Clock and Asynchronous Signals

Clock-skew calculation

tffpd(min) + tcomb(min) – thold > tskew(max)

tff d( i ) + t b( i ) > t k ( ) + th ldtffpd(min) + tcomb(min) > tskew(max) + thold

• Clock skew should be smaller than the hold-time marging• Compensating for clock skew:

– Longer flip-flop propagation delay– Explicit combinational delays– Shorter (even negative) flip-flop hold times

• Long delay inside flip-flopLong delay inside flip flop

Page 6: Clock and Asynchronous Signals

Example of bad clock distribution

Page 7: Clock and Asynchronous Signals

Clock distribution in ASICs

• This is what a typical ASIC router will do if you don’t lay out• This is what a typical ASIC router will do if you don t lay out the clock by hand.

Page 8: Clock and Asynchronous Signals

“Clock-tree” solution

• Often laid out by hand (H-tree)y ( )• Wide,fast metal (low R ==> fast RC time constant)

Page 9: Clock and Asynchronous Signals

Gating the clock

• Definitely a no no• Definitely a no-no– Glitches possible if control signal (CLKEN) is generated by

the same clock– Excessive clock skew in any case

Page 10: Clock and Asynchronous Signals

If you really must gate the clock...

Page 11: Clock and Asynchronous Signals

Control unit and data unit

• Divide large state machines into smaller machines• Data unitData unit

– Data processing• Storing, moving, combing, etc.

– Registers, specialized functions (adder, shifter), memory• Control unit

Starting stopping actions in data units– Starting, stopping actions in data units– Testing conditions– Deciding what to do next

Page 12: Clock and Asynchronous Signals

Synchronous System Structure

Everything is clocked by the same commonsame, common clock

Page 13: Clock and Asynchronous Signals

Typical synchronous-system timing

• Outputs have one complete clock period to propagate to inputs• Must take into account flip-flop setup times at next clock period

Page 14: Clock and Asynchronous Signals

Simplified PowerPC core block diagram

InstructionU it MMUUnit

Load/Store Unit

LSU

GPR File

ALU

Page 15: Clock and Asynchronous Signals

Abstract view of instruction execution unit for MIPS

Page 16: Clock and Asynchronous Signals

Datapath

n

n

Register

File

Mul ALU Shifter

nn

Page 17: Clock and Asynchronous Signals

Asynchronous inputs

• Not all inputs are synchronized with the clock• Examples:Examples:

– Keystrokes– Sensor inputs– Data received from a network (transmitter has its own clock)

• Inputs must be synchronized with the system clock before being applied to a synchronous systemsystem clock before being applied to a synchronous system

Page 18: Clock and Asynchronous Signals

A simple synchronizer

Page 19: Clock and Asynchronous Signals

Only one synchronizer per input

Page 20: Clock and Asynchronous Signals

Even worse

• Combinational delays to the two synchronizers are likely to be different

Page 21: Clock and Asynchronous Signals

The way to do it

O h i i• One synchronizer per input• Carefully locate the synchronization points in a system• But still a problem -- the synchronizer output may becomeBut still a problem the synchronizer output may become

metastable when setup and hold time are not met

Page 22: Clock and Asynchronous Signals

Synchronizer failure

• Synchronizer failure: a system uses a synchronizer output while the output is still in the metsastable statep– Use input signals that meet the published specification– Wait “long enough” so FF comes out of metastability on its own

• Metastability resolution time – The maximum time that the output can remain metastable without

causing synchronizer failure, e.g., g y , g ,tr = tclk – tcomb – tsetup

Page 23: Clock and Asynchronous Signals

Recommended synchronizer design

• Hope that FF1 settles down before “META” is sampled– In this case, “SYNCIN” is valid for almost a full clock period

C l l t th b bilit f “ h i f il ” (FF1 till– Can calculate the probability of “synchronizer failure” (FF1 still metastable when META sampled)

Page 24: Clock and Asynchronous Signals

Metastability decision window

Page 25: Clock and Asynchronous Signals

Metastability resolution time

Page 26: Clock and Asynchronous Signals

Flip-flop metastable behavior

• Probability of flip-flop output being in the metastable state is an exponentially decreasing function of tr (time since clock edge, a.k.a. “resolution time”)

• Mean time between synchronization failures (MTBF):

etMTBFrt

=/

)(τ

where

afTtMTBF r ⋅⋅

=0

)(

τ and T0 are parameters for a particular flip-flopf is the clock frequency, anda is the number of asynchronous transitions / sec y

Page 27: Clock and Asynchronous Signals

Typical flip-flop metastability parameters

/

afTetMTBF

rt

r ⋅⋅=

0

/

)(τ

MTBF = 1000 yrs.f 25 MHf = 25 MHza = 100 KHztr = ?

Page 28: Clock and Asynchronous Signals

Is 1000 years enough?

• If MTBF = 1000 years and you ship 52,000 copies of the product, then some system experiences a mysterious failure every weeky p y y

• Real-world MTBFs must be much higher• How to get better MTBFs?

– Use faster flip-flops• But clock speeds keep getting faster, thwarting this approach

– Wait for multiple clock ticks to get a longer metastabilty resolution– Wait for multiple clock ticks to get a longer metastabilty resolution time• Waiting longer usually doesn’t hurt performance

l h i i i l “ d i ” h d h k• …unless there is a critical “round-trip” handshake

Page 29: Clock and Asynchronous Signals

Multiple-cycle synchronizer

• Clock-skew problemp

Page 30: Clock and Asynchronous Signals

Deskewed multiple-cycle synchronizer

• Necessary in really high-speed systems• DSYNCIN is valid for almost an entire clock period


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