cm44-10123-1et1 errata - fujitsu.com · 1/25 cm44-10123-1et1 errata f2mc-16lx 16-bit...

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CM44-10123-1ET1

Errata F2MC-16LX 16-BIT MICROCONTROLLER MB90435 Series HARDWARE MANUAL

2004.10.6 Page Item Description

2 1.1 Table 1.1-1 was corrected as indicated by the shading below. • Error

Features MB90V540G MB90F438L(S)/F439(S) MB90437L(S)*1/438L(S)/

439(S)

ROM capacity External Flash memory MB90F438L(S): 128 Kbytes MB90F439(S): 256 Kbytes

MB90437L(S)*1: 64 Kbytes MB90438L(S): 128 Kbytes MB90439(S): 256 Kbytes

RAM capacity 8 Kbytes MB90F438L(S): 4K bytes MB90F439(S): 6K bytes

MB90437L(S) *1: 2 Kbytes MB90438L(S): 4 Kbytes MB90439(S): 6 Kbytes

Clocks Two clocks/One clock system

MB90F438L/F439: Two clocks system MB90F438LS/F439S: One clock system

MB90437L*1/438L/439: Two clocks system MB90437LS*1/438LS/439S: One clock system

Package PGA-256 QFP100, LQFP100 Emulator- specific power supply *2

None -

*1: Under development *2: It is setting of DIP switch S2 when Emulation pod (MB2145-507) is used.

Please refer to the MB2145-507 hardware manual (2.7 Emulator-specific Power Pin) about details. • Correct

Features MB90V540G MB90F438L(S)/F439(S) MB90437L(S)

/438L(S)/439(S)

ROM capacity External Flash memory MB90F438L(S): 128 Kbytes MB90F439(S): 256 Kbytes

MB90437L(S) : 64 Kbytes MB90438L(S): 128 Kbytes MB90439(S): 256 Kbytes

RAM capacity 8 Kbytes MB90F438L(S): 4K bytes MB90F439(S): 6K bytes

MB90437L(S) : 2 Kbytes MB90438L(S): 4 Kbytes MB90439(S): 6 Kbytes

Clocks Two clocks system*1

MB90F438L/F439: Two clocks system MB90F438LS/F439S: One clock system

MB90437L /438L/439: Two clocks system MB90437LS /438LS/439S: One clock system

Package PGA-256 QFP100, LQFP100 Emulator- specific power supply *2

None -

*1: When One clock system is used, provide the clock from the tool side at X0A and X1A pins. *2: It is setting of DIP switch S2 when Emulation pod (MB2145-507) is used.

Please refer to the MB2145-507 hardware manual (2.7 Emulator-specific Power Pin) about details.

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Page Item Description

5 1.3 Figure 1.3-1 was corrected as indicated by the shading below. • Error

16-bit Reload

Timer 2ch

8/16-bit PPG 4ch

Inte

rnal

dat

a bu

s

TIN0, INT1

TOT0, TOT1

PPG0 to PPG3

• Correct

16-bit Reload

Timer 2ch

8/16-bit PPG 4ch

Inte

rnal

dat

a bu

s

TIN0, TIN1

TOT0, TOT1

PPG0 to PPG3


Pin No. LQFP QFP

Pin name

Circuit type Function

P20 to P27

General-purpose I/O ports with programmable pull-up function. These functions can be used in single-chip mode. 99 to 6 1 to 8

A16 to A23

I I/O pins for A16 to A23 of external address bus. These functions can be used when the external bus is enabled.

• Correct

Pin No. LQFP QFP

Pin name

Circuit type Function

P20 to P27

General-purpose I/O ports with programmable pull-up function. Functions as the general-purpose input/output port in the external bus mode if the bit corresponding to external address output control register (HACR) is set to "1". 99 to 6 1 to 8

A16 to A23

I Output pins for A16 to A23 of external address bus. Functions as the output pin of an address in the external bus mode if the bit corresponding to external address output control register (HACR) is set to "0".

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15 1.7.1 The Circuit type "A" of the table was changed as the following figure. • Error

• Correct

18 1.8 The summary was added as indicated by the shading below.

When handling devices, be careful about the following.

Preventing latch-up Stabilization of power supply voltage Treatment of unused pins • • •

18 1.8 The following item was added to "1.8 Precautions for Device Handling" as indicated by the shading

below.

Stabilization of power supply voltage

If the power supply voltage varies acutely even within the operation assurance range of the VCC power supply voltage, a malfunction may occur. The VCC power supply voltage must therefore be stabilized. As stabilization guidelines, stabilize the power supply voltage so that VCC ripple fluctuations (peak to peak value) in the commercial frequencies (50 to 60 Hz) fall within 10% of the standard VCC power supply voltage and the transient fluctuation rate becomes 0.1 V/ms or less in instantaneous fluctuation for power supply switching.

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20 1.8 The following description of " Use of the subclock" in " Handling the Device " was corrected as indicated by shading below. • Error

Use of the subclock

Use the one clock system parts when the subclock is not used. In that case, pull-down the pin X0A and leave the pin X1A open. When using the one clock system parts, a 32 kHz oscillator has to be connected to the X0A and X1A pins.

• Correct

Use of the subclock

Use the two clock system parts when the subclock is not used. In that case, pull-down the pin X0A and leave the pin X1A open. When using the one clock system parts, a 32 kHz oscillator has to be connected to the X0A and X1A pins.

50 3.3 Table 3.3-1 was corrected as indicated by shading below.

• Error

Software interrupt

instruction

Vector address L

Vector address M

Vector address H

Mode register

Interrupt No.

Hardware interrupt

INT 36 FFFF6CH FFFF6DH FFFF6EH Not used #35 16-bit reload timer 1 INT 37 FFFF68HH FFFF69H FFFF6AH Not used #36 UART 0 receive INT 38 FFFF64H FFFF65H FFFF66H Not used #37 UART 0 transmit INT 39 FFFF60H FFFF61H FFFF62H Not used #38 UART 1 receive INT 40 FFFF5CH FFFF5DH FFFF5EH Not used #39 UART 1 transmit INT 41 FFFF58H FFFF59H FFFF5AH Not used #40 Flash memory INT 42 FFFF54H FFFF55H FFFF56H Not used #41 Delayed interrupt INT 43 FFFF50H FFFF51H FFFF52H Not used #42 None

• Correct

Software interrupt

instruction

Vector address L

Vector address M

Vector address H

Mode register

Interrupt No.

Hardware interrupt

INT 36 FFFF6CH FFFF6DH FFFF6EH Not used #36 16-bit reload timer 1 INT 37 FFFF68H FFFF69H FFFF6AH Not used #37 UART 0 receive INT 38 FFFF64H FFFF65H FFFF66H Not used #38 UART 0 transmit INT 39 FFFF60H FFFF61H FFFF62H Not used #39 UART 1 receive INT 40 FFFF5CH FFFF5DH FFFF5EH Not used #40 UART 1 transmit INT 41 FFFF58H FFFF59H FFFF5AH Not used #41 Flash memory INT 42 FFFF54H FFFF55H FFFF56H Not used #42 Delayed interrupt INT 43 FFFF50H FFFF51H FFFF52H Not used #43 None

56 3.4 The description in Attachment 1 was added as Section 3.4.3.

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74 4.1 The following description of " Notes on Clock Generator" was corrected as indicated by shading below. • Error

Notes on Clock Generator

When the operating voltage is 5 V, the OSC source oscillation can be between 3 MHz and 5 MHz. When an external clock source is used, its frequency can be between 3 MHz and 16MHz. The highest operating frequency for the CPU and peripheral resource circuits is 16 MHz, however. Normal operation is not guaranteed if a multiplication factor resulting in a higher frequency than 16 MHz is specified. For example, if the external clock frequency is 16 MHz, only 1 can be specified as the multiplication factor. • • •

• Correct

Notes on Clock Generator

When the operating voltage is 5 V, its frequency can be between 3 MHz and 16MHz. The highest operating frequency for the CPU and peripheral resource circuits is 16 MHz, however. Normal operation is not guaranteed if a multiplication factor resulting in a higher frequency than 16 MHz is specified. For example, if the external clock frequency is 16 MHz, only 1 can be specified as the multiplication factor. • • •

78 4.2 Table4.2-2 was corrected as indicated by shading below.

• Error

CKSCR WTC LPMCR Type of reset WS1 WS0 WDCS CS1 CS0 WDCS CG1 CG0

Main mode × × × × × × Ο Ο

HST________

+RST________

Sub mode (*1) Ο Ο Ο Ο Ο Ο Ο Ο

• Correct

CKSCR WTC LPMCR Type of reset WS1 WS0 MCS CS1 CS0 WDCS CG1 CG0

Main mode × × Ο × × × Ο Ο

HST________

+RST________

Sub mode (*1) Ο Ο Ο Ο Ο Ο Ο Ο

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79 4.2 Figure 4.2-2 was corrected as indicated by the shading below.

(RST, HST+RST) Reset input

A. Oscillation status

Status

Status

Only RSTused(HST ="H")

Oscillating

Oscillating

Oscillating

OscillatingHST + RSTused

HST plus RST used

Stopped

Oscillating Stopped

Main

Sub

Oscillating

Main

Sub

Main

Sub

Waiting for mainclock oscillation

stabilization

Waiting for mainclock oscillation

stabilization

Main clock operation enabled

Main clock operation enabled

Oscillation stabilizationtime set before reset input

Oscillation stabilization timeof 218main clock cycles

B. Execution timing (L: Stop, H: Start)

[Operation Transition by Reset Input]

Main clock mode

Subclock mode

Main mode

Sub mode

Waiting for subclockoscillation stabilization

Subclock operationenabled

Waiting for subclockoscillation stabilization

Subclock operationenabled

216 cycles of subclock oscillation (32 kHz) (about 2 s)

216 cycles of subclock oscillation (32 kHz) (about 2 s)

Vcc (power supply)

Only RST used (HST ="H")

Power-on reset

When sub mode is requested,main clock operation is enabled.During the main clock operation,writing to SCS bits is possible.

When sub mode is requested,main clock operation is enabled.During the main clock operation,writing to SCS bits is possible.

Power-onreset

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80 4.3 The note of Table 4.3-1 was corrected as indicated by the shading below. • Error Notes:

In stop mode, input of the external pin reset signal allows an oscillation stabilization wait time to be set. The oscillation stabilization time for a power-on reset and hardware standby is fixed to 218 cycles of source oscillation. For other types of reset, the oscillation stabilization wait time is determined by WS1 and WS0 of the clock selection register.

• Correct Notes:

In stop mode, input of the external pin reset signal allows an oscillation stabilization wait time to be set. The oscillation stabilization wait time for a power-on reset is fixed to 218 cycles of the source oscillation. Also, the oscillation stabilization wait time of the hardware standby reset in the subclock mode is fixed to 217 cycles of the source oscillation. For other types of reset, the oscillation stabilization wait time is determined by WS1 and WS0 of the clock selection register.

85 5.1 The following description of " Switching between main clock and PLL clock" in " Main Clock

Oscillation Stabilization Wait Time" was corrected as indicated by shading below. • Error

• • • When the MCS bit is changed from 1 to 0, the PLL clock takes over from the main clock after the PLL clock oscillation stabilization wait time (212 machine clock cycles). • • •

• Correct

• • • When the MCS bit is changed from 1 to 0, the PLL clock takes over from the main clock after the PLL clock oscillation stabilization wait time (213 machine clock cycles). • • •

85 5.1 The following description of "❍ Switching between main clock and subclock " in "■ Switching between

Machine Clocks " was corrected as indicated by shading below. • Error ❍ Switching between main clock and subclock

In the two clocks system parts, data is written to the SCS bit of the clock selection register (CKSCR) to switch between the main clock and subclock. If the SCS bit is changed from 1 to 0, the operation is switched from the main clock to subclock when the next edge of the subclock signal is detected. • • •

• Correct ❍ Switching between main clock and subclock

In the two clocks system parts, data is written to the SCS bit of the clock selection register (CKSCR) to switch between the main clock and subclock. If the SCS bit is changed from 1 to 0, the operation is switched from the main clock to subclock synchronizing the subclock (approx. 130µs).

• • •

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85 5.1 The following description of " Initializing the machine clock" in " Switching between Machine Clocks " was added as indicated by shading below.

Initializing the machine clock

The MCS bit and SCS bit are not initialized by a reset using an external pin or RST bit. These bits are initialized to 1 by any other reset. Note:

When tune on the power or hardware standby mode or stop mode is released, the subclock oscillation stabilization time (about 2 seconds) is generated. In the meantime, when switching from the main clock mode to the subclock mode, the oscillation stabilization time is generated. In attempting to switch the clock mode, do not attempt to switch to another clock mode or low-power consumption mode until the first switching is completed. The MCM and SCM bits of the clock selection register (CKSCR) indicate that switching is completed. If the mode is switched to another clock mode or low-power-consumption mode before completion of switching, the mode may not be switched.

85 5.1 The following description of "■ PLL Clock Multiplication Function" was corrected as indicated by

shading below. • Error ■ PLL Clock Multiplication Function

The CS1 and CS0 bits are used to set the multiplication factor of the PLL clock to 2, 4, 6, and 8. This clock is divided by two and used as a machine clock signal.

• Correct ■ PLL Clock Multiplication Function

The PLL clock multiplication factor can be selected from 1, 2, 3, and 4 by setting the CS1 and CS0 bits.

90 5.3.1 Table5.3-2 was corrected as indicated by shading below.

• Error MOV io,#imm8 MOV dir,#imm8 MOV eam,#imm8 MOV eam,#immRi

MOV io,A MOV dir,A MOV addr16,A MOV eam,A

MOV RLi+dip8,A MOVP addr24,A

MOVW io,#imm16 MOVW dir,#imm16 MOVW eam,#imm16 MOVW eam,RWi

MOVW io,A MOVW dir,A MOVW addr16,A MOVW eam,RWi

MOVW RLi+dip8,A MOPW addr24,A

SETB io:bp SETB dir:bp SETB addr16:bp

• Correct MOV io,#imm8 MOV dir,#imm8 MOV eam,#imm8 MOV eam,Ri

MOV io,A MOV dir,A MOV addr16,A MOV eam,A

MOV @RLi+disp8,A

MOVW io,#imm16 MOVW dir,#imm16 MOVW eam,#imm16 MOVW eam,RWi

MOVW io,A MOVW dir,A MOVW addr16,A MOVW eam,A

MOVW @RLi+disp8,A

SETB io:bp SETB dir:bp SETB addr16:bp

CLRB io:bp CLRB dir:bp CLRB addr16:bp

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92 5.3.2 The following descriptions of "[bits 13 and 12] WS1 and WS0" in "■ Clock Selection Register (CKSCR)" were corrected as indicated by shading below. • Error

• • • These bits are not initialized by a reset except a power-on reset and hardware standby release. Therefore, at power-on, the oscillation stabilization wait time is about 218 counts of source oscillation. These bits can be read and written. Table 5.3-3 "WS Bit Setting" lists the WS bit setting.

• Correct

• • • These bits are not initialized by a reset except a power-on reset*. Therefore, at power-on, the oscillation stabilization wait time is about 218 counts of source oscillation. These bits can be read and written. Table 5.3-3 "WS Bit Setting" lists the WS bit setting. *: These bits are initialized by a hardware standby reset in the subclock mode.

92 5.3.2 Table 5.3-3 was deleted as indicated by the shading below.

WS1 WS0 Oscillation stabilization wait time (at 4 MHz source oscillation)

1 1 Approx. 32.77 ms (217 counts of source oscillation)

Approx. 65.54 ms (218 counts of source oscillation) at power-on reset and hardware standby only

93 5.3.2 The following descriptions of "[bits 9 and 8] CS1 and CS0" in " Clock Selection Register (CKSCR)"

were corrected as indicated by shading below. • Error

These bits determine the multiplication factor of the PLL clock. These bits are initialized to 00 by a reset due to power-on and hardware standby. • • • Table 5.3-4 "CS Bit Setting" lists the settings of the CS bits.

Note: When the operating voltage is 5 V, the OSC source oscillation can be between 3 MHz and 5 MHz. When an external clock source is used, its frequency can be between 3 MHz and 16MHz. Since the highest operating frequency for the CPU and peripheral resource circuits is 16 MHz, however, normal operation is not guaranteed if a multiplication factor resulting in a higher frequency than 16 MHz is specified. For example, if the external clock frequency is 16 MHz, only 1 can be specified as the multiplication factor. • • •

• Correct

These bits determine the multiplication factor of the PLL clock. These bits are not initialized by an external pin, RST bit, watch-dog or hardware standby *reset. These bits are initialized to "00B" by only a power-on reset . • • • Table 5.3-4 "CS Bit Setting" lists the settings of the CS bits. *: These bits are initialized by a hardware standby reset in the subclock mode.

Note: When the operating voltage is 5 V , the source oscillation can be between 3 MHz and 16MHz. Since the highest operating frequency for the CPU and peripheral resource circuits is 16 MHz, however, normal operation is not guaranteed if a multiplication factor resulting in a higher frequency than 16 MHz is specified. For example, if the external clock frequency is 16 MHz, only 1 can be specified as the multiplication factor. • • •

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96 5.4 The note of " Status Transition for Clock Selection " was added as indicated by the shading below. Note:

In attempting to switch the clock mode, do not attempt to switch to another clock mode or low-power consumption mode until the first switching is completed. The MCM bit of the clock selection register (CKSCR) indicates that switching is completed. If the mode is switched to another clock mode or low-power-consumption mode before completion of switching, the mode may not be switched.

99 6.1 The note of " Low-Power Consumption Modes" was added as indicated by the shading below.

Note:

In attempting to switch the clock mode, do not attempt to switch to another clock mode or low-power consumption mode until the first switching is completed. The MCM and SCM bits of the clock selection register (CKSCR) indicate that switching is completed. If the mode is switched to another clock mode or low-power-consumption mode before completion of switching, the mode may not be switched.

100 6.1 Table 6.1-1 was corrected as indicated by the shading below.

• Error

Status Transition condition

Subclock oscillation

Main oscillation

Machine clock

CPU Peripheral Pin Release method

Hardware standby HST

________

=L Stopped Stopped Stopped Stopped Stopped HI-Z HST________

=H

*1: Watch prescaler, timebase timer, and external interrupt *2: Watch prescaler and external interrupt *3: External interrupt • Correct

Status Transition condition

Subclock oscillation

Main oscillation

Machine clock

CPU Peripheral Pin Release method

Hardware standby HST

_______

=L Stopped Stopped Stopped Stopped Stopped HI-Z HST_______

=H

*1: Watch timer, timebase timer, and external interrupt *2: Watch timer and external interrupt *3: External interrupt

109 6.2 The following description of " Transition Conditions in Low-Power Consumption Mode" was corrected as indicated by shading below. • Error

Transition Conditions in Low-Power Consumption Mode

The meanings of symbols used in the table and figure are explained below: MCS: MCS bit (clock selection register) (PLL clock mode selected when MSC=0) SCS: SCS bit (clock selection register) (subclock mode selected when SCS=0)

• • • • Correct

Transition Conditions in Low-Power Consumption Mode

The meanings of symbols used in the table and figure are explained below: MCS: MCS bit (clock selection register) (PLL clock mode selected when MCS=0) SCS: SCS bit (clock selection register) (subclock mode selected when SCS=0)

• • •

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118 6.3 The note of " Status Transition Diagram for Low-Power Consumption Mode (Two Clocks System Parts)" was added as indicated by the shading below. Note:

In attempting to switch the clock mode, do not attempt to switch to another clock mode or low-power consumption mode until the first switching is completed. The MCM and SCM bits of the clock selection register (CKSCR) indicate that switching is completed. If the mode is switched to another clock mode or low-power-consumption mode before completion of switching, the mode may not be switched.

121 6.3 The note of " Status Transition Diagram for Low-Power Consumption Mode (One Clock System

Parts)" was added as indicated by the shading below. Note:

In attempting to switch the clock mode, do not attempt to switch to another clock mode or low-power consumption mode until the first switching is completed. The MCM bit of the clock selection register (CKSCR) indicates that switching is completed. If the mode is switched to another clock mode or low-power-consumption mode before completion of switching, the mode may not be switched.

133 7.2.3 The summary was corrected as indicated by the shading below.

• Error

The external address output control register (HACR) controls the external output of addresses (A19 to A16). The bits correspond to addresses A19 to A16, which control address output pins, as shown in Figure 7.2-4 "External Address Output Control Address Configuration".

• Correct

The external address output control register (HACR) controls the external output of addresses (A23 to A16). The bits correspond to addresses A23 to A16, which control address output pins, as shown in Figure 7.2-4 "External Address Output Control Address Configuration".

133 7.2.3 The following description of " External Address Output Control Register (HACR)" was corrected as

indicated by shading below. • Error

• • • The HACR register controls output of addresses (A23 to A16) to the external circuit. The address output pin is controlled as follows with the eight bits that correspond to address bits A32 to A16. • • •

• Correct • • • The HACR register controls output of addresses (A23 to A16) to the external circuit. The address output pin is controlled as follows with the eight bits that correspond to address bits A23 to A16. • • •

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Interval (match clock: 4 MHz) WDCS WT1 WT0

Minimum Maximum 1 0 0 About3.58ms About4.61ms 1 0 1 About14.33ms About18.43ms 1 1 0 About57.23ms About73.73ms 1 1 1 About458.75ms About589.82ms

0*1 0 0 About0.457s About0.576s 0*1 0 1 About3.584s About4.608s 0*1 1 0 About7.167s About9.216s 0*1 1 1 About14.336s About18.432s

*1: Only the two clocks system parts. • Correct

Interval * WDCS WT1 WT0

Minimum Maximum 1 0 0 About3.58ms About4.61ms 1 0 1 About14.33ms About18.43ms 1 1 0 About57.23ms About73.73ms 1 1 1 About458.75ms About589.82ms 0 0 0 About0.457s About0.576s 0 0 1 About3.584s About4.608s 0 1 0 About7.168s About9.216s 0 1 1 About14.336s About18.432s

*: For a source oscillation of 4 MHz. For a sub-oscillation clock of 32 kHz.

161 10.2 The note of "[bits 1 and 0] WT1 and WT0" was corrected as indicated by shading below. • Error Note:

The maximum interval assumes that the timebase counter is not reset during watch-dog operation. • Correct Note:

The interval time uses the carry signal of the timebase timer or watch timer as a count clock. If the timebase timer or watch timer is cleared, the interval time of the watchdog timer may become long. The time-base timer is also cleared by writing zero to the timebase timer counter clear bit (TBR) in the time-base timer control register (TBTC); transition from main clock mode to PLL clock mode; transition from subclock mode to main clock mode; and transition from subclock mode to PLL clock mode.

13/25


166 11.2 The following descriptions of "[Bit 7] WDCS" in "■ Watch Timer Control Register (WTC)" were corrected as indicated by shading below. • Error [Bit 7] WDCS

The WDCS bit is used to specify whether the clock signal of the watch timer or timebase timer is used as the input clock of the watch-dog timer when the main clock or PLL clock is selected as the machine clock. When WDCS=0, the clock signal of the watch timer can be selected. When WDCS=1, the clock signal of the timebase timer can be selected. When 1 is set in WDCS, the function that selects the main clock or PLL clock uses the timebase timer output. Functions that include the subclock use output from the watch timer. This bit is initialized to 1 by a power-on reset.

Note:

If WDCS is set to 1, the watch-dog timer counter may be incremented because the timebase timer output and watch timer output are asynchronous. If WDCS is set to 1, the watch-dog timer must be cleared before and after the clock mode is changed.

• Correct [Bit 7] WDCS

The WDCS bit is used to specify whether the clock signal of the watch timer or timebase timer is used as the input clock of the watch-dog timer. <For the main clock or PLL clock mode>

WDCS 1 : Timebase timer clock 0 : Watch timer clock

<For the subclock mode> WDCS : This bit must be written to "0".

This bit is initialized to 1 by a power-on reset.

Note:

If WDCS is set to 1, the watch-dog timer counter may be incremented because the timebase timer output and watch timer output are asynchronous. If WDCS is set to 1, the watch-dog timer must be cleared before and after the clock mode is changed. If the timebase timer is used as the input clock of the watch-dog timer in the subclock mode (WDCS="1"), the watch-dog timer stops. The clock signal of the watch timer must be selected as the input clock of the watch-dog timer (WDCS="0"), when the watch-dog timer is used in the subclock mode.

14/25


168 11.3 The following descriptions of "■ Watch Timer" were corrected as indicated by shading below. • Error ■ Watch Timer

The watch timer consists of a 15-bit counter that counts oscillation inputs generated by the subclock. While the subclock is input, the watch timer keeps counting. The watch timer is cleared by a power-on reset or writing 0 to the WTR bit of the watch timer control register (WTC). The watch-dog counter and an interval interrupt using the watch timer output are affected by clearing of the timer counter.

• Correct ■ Watch Timer

The watch timer consists of a 15-bit counter that counts oscillation inputs generated by the subclock. While the subclock is input, the watch timer keeps counting. The watch timer is cleared by a power-on reset or writing 0 to the WTR bit of the watch timer control register (WTC). Note:

• Clearing the watch counter affects the watchdog counter and interval interrupts that use watch timer output.

• To clear the watch timer by writing "0" to the WTR bit in the watch timer control register (WTC), set the WTIE bit to "0" and set the watch timer to interrupt inhibited state. Before permitting an interrupt, clear the interrupt request issued by writing "0" to the WTOF flag.

168 11.3 The following item was added to "11.3 Watch Timer Operation" as indicated by the shading below.

■ Setting Operation Clock for Watchdog Timer The clock source of the watchdog timer can be set by the WDCS bit in the watch timer control register (WTC). When the sub-clock is used for the machine clock, select the watch timer output with the WDCS setting to "0". If the mode transits to the sub-clock mode with the WDCS bit setting to "1", the watchdog timer stops.

193 13 The following term in this chapter was corrected as follows:

TOUT --> TOT (total: 15 points)

194 13.1 The following descriptions of " Outline of 16-bit Reload Timer (with Event Count Function)" were corrected as indicated by shading below. • Error

Outline of 16-bit Reload Timer (with Event Count Function)

The output pin (TOUT) outputs a toggle output waveform in reload mode and outputs a square waveform indicating counting in one-shot mode. The input pin (TIN) is used for event input in event count mode, and can be used for trigger input or gate input in internal clock mode. MB90435 series products have two 16-bit reload timers.

• Correct

Outline of 16-bit Reload Timer (with Event Count Function)

The output pin (TOT) outputs a toggle output waveform in reload mode and outputs a square waveform indicating counting in one-shot mode. The input pin (TIN) is used for event input in event count mode, and can be used for trigger input or gate input in internal clock mode. MB90435 series products contain two 16-bit reload timers.

15/25

Page Item Description 195 13.1 The following item was added to " 13.1 Outline of 16-Bit Reload Timer (with Event Count Function)".

■ Pin Name of 16-bit Reload Timer 16-bit reload timer contains two timers, timer 1 and timer 2, and the input pin name (TIN) and output pin name (TOT) of each timer are shown below.

input pin (TIN) output pin (TOT) Timer1 TIN0 TOT0 Timer2 TIN1 TOT1

217 14.3.3 The following description of "[bits 7 to 5] PCS2 to 0 (PPG count select): Count clock selection bit" in

"■ PPG0, 1 Clock Selection Register (PPG0/1)" was corrected as indicated by shading below. • Error

PCS2 PCS1 PCS0 Operation mode

1 0 1 Clock input from the timebase timer (128 µs, 4 MHz source oscillation)

• Correct

PCS2 PCS1 PCS0 Operation mode


218 14.3.3 The following description of "[bits 4 to 2] PCM2 to 0 (PPG count mode): Count clock selection bit" in

"■ PPG0, 1 Clock Selection Register (PPG0/1)" was corrected as indicated by shading below. • Error

PCM2 PCM1 PCM0 Operation mode


• Correct

PCM2 PCM1 PCM0 Operation mode


220 14.4 Table 14.4-1 was corrected as indicated by the shading below.

• Error

Reload operation Pin output change PRLH --> PCNT PPG0/1 [0 --> 1] ↑ Rise PRLL --> PCNT PPP0/1 [1 --> 0] ↓ Fall

• Correct

Reload operation Pin output change PRLH --> PCNT PPG00/10 [0 --> 1] ↑ Rise PRLL --> PCNT PPP00/10 [1 --> 0] ↓ Fall

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221 14.4 Figure 14.4-1 was added as indicated by the shading below.

PEN

PPG 00/10

(Start)

T (L+1) T (H+1) L : PRLL value

H : PRLH value

T : Input from peripheral clock (

or timer base counter (depending on the

clock selection by PPGC)

Output pinStarts operation based on PEN (from Lside).

Output pin


• Error

Ph0 Pl0

PPG0

PPG1

• Correct

Ph0 Pl0

PPG00

PPG10

225 14.8 The following descriptions of "❍ <Registers>" in "■ Initial Values of 8/16-bit PPG Hardware" were corrected as indicated by shading below. • Error ❍ <Registers>

PPGC0 --> 0X000001B PPGC1 --> 00000001B PPG10 --> XXXXXX00B

• Correct ❍ <Registers>

PPGC0 --> 0X000XX1B PPGC1 --> 0X000001B PPG10 --> XXXXXX00B

239 16.5 The summary was deleted as indicated by the shading below.

Note carefully the following items when using DTP/external interrupts:

Conditions on the externally connected peripheral when DTP is used Recovery from standby External interrupt/DTP operation procedure External interrupt request level

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240 16.5 The following descriptions of "❍ External interrupt request level" in "■ Notes on Using DTP/External Interrupts" were corrected as indicated by shading below. • Error • • • As shown in Figure 16.5-1 "Clearing the Cause Hold Circuit Upon Level Set", when the request input level is related to the level setting, a request that is input from an external device to the interrupt controller is kept active even if the request is later canceled because a cause hold circuit has been installed. To cancel the request to the interrupt controller, the cause hold circuit must be cleared as shown in Figure 16.5-2 "Interrupt Cause and Interrupt Request to the Interrupt Controller While Interrupts are Enabled". • Correct • • • As shown in Figure 16.5-1 "Clearing the Interrupt Request Flag Bit (EIRR:ER) Upon Level Set", when the request input level is related to the level setting, a request that is input from an external device to the interrupt controller is kept active while the interrupt request is enable (ENIR:EN=1), even if the request is later canceled. To cancel the request to the interrupt controller, the interrupt request flag bit (EIRR:ER) must be cleared as shown in Figure 16.5-2 "Interrupt Cause and Interrupt Request to the Interrupt Controller While Interrupts are Enabled".


Figure 16.5-1 Clearing the Cause Hold Circuit Upon Level Set

Level detection Cause F/F (cause hold circuit)

The cause is kept held unless cleared.

Enable gate To interruptcontrollerInterrupt cause

• Correct

Figure 16.5-1 Clearing the interrupt request flag bit (EIRR: ER) Upon Level Set

Level detection interrupt request flag bit

The cause is kept held unless cleared.

Enable gate To interruptcontrollerInterrupt cause (EIRR:ER)

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240 16.5 Figure 16.5-2 was corrected as indicated by the shading below. • Error Figure 16.5-2 Interrupt Cause and Interrupt Request to the Interrupt Controller While Interrupts are Enabled

Interrupt cause

Interrupt request to

H level

Set inactive when the cause F/F is cleared. the interrupt controller

• Correct Figure 16.5-2 Interrupt Cause and Interrupt Request to the Interrupt Controller While Interrupts are Enabled

Interrupt cause

Interrupt request to Canceled Interrupt cause

Set inactive when the interrupt request flag bit (EIRR:ER) is cleared. the interrupt controller

(At the high level detection)


• Error A/D control status register (upper)

15 14 13 12 11 10 9 8 ←Bit No. Address: 000035H BUSY INT INTE PAUS STS1 STS0 STRT Reserved ADCS1

Read/write → (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value → (0) (0) (0) (0) (0) (0) (0) (0)

• Correct A/D control status register (upper)


Read/write → (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (W) (R/W) Initial value → (0) (0) (0) (0) (0) (0) (0) (0)

247 17.3.1 The note of " [bits 5, 4, and 3] ANS2, ANS1, and ANS0 (Analog start channel set):" was added as indicated

by the shading below. Note:

* Read During A/D conversion, the current conversion channel is read from these bits. If the system is stopped in the stop mode, the last conversion channel is read. And before A/D conversion starts, the previous conversion channel will be read even if these bits have already been set to the new value.

* Upon a reset, these bits are initialized to "000".

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249 17.3.2 Figure 17.3-4 was corrected as indicated by the shading below. • Error A/D control status register (upper)


Read/write → (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value → (0) (0) (0) (0) (0) (0) (0) (0)

• Correct A/D control status register (upper)


Read/write → (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (W) (R/W) Initial value → (0) (0) (0) (0) (0) (0) (0) (0)

251 17.3.2 The following descriptions of "[bit 9] STRT (Start):" in "■ A/D Control Status Register (ADCS1)" were

added as indicated by shading below. [bit 9] STRT (Start):

A/D conversion is activated when "1" is written to this bit. The byte/word command reads "1". The read-modify-write series commands read "0". To reactivate A/D conversion, write "1" to this bit again. Upon a reset, this bit is initialized to "0". In the stop mode, a reactivation during the operation is not supported. Check the BUSY bit before writing "1". Do not perform a forced stop and activation by software simultaneously. (BUSY=0, STRT=1)

253 17.3.3 The following description of "[bits 12 and 11] CT1 and CT0 (Compare time):" in "■ Data Registers

(ADCR1 and ADCR0)" was corrected as indicated by shading below • Error • • • Do not set to "00" unless the machine clock is 8MHz. Otherwise the conversion accuracy is not guaranteed. Reading these bits always returns "00". • Correct • • • Set these bits to "00" (CT1=CT0=0) while the machine clock is 8MHz or less. Conversion accuracy is not guaranteed when the machine clock is more than 8MHz. Reading these bits always returns "00".

292 19.1 The following descriptions of "■ Features of UART1" were corrected as indicated by shading below. • Error

UART provides the following features. • • • • On-chip dedicated baud rate generator At internal machine clock speeds of 6, 8, 10, 12, 16MHz.

• Asynchronous: 9615/31250/4808/2404/1202 bps • • •

• Correct UART provides the following features. • • • • On-chip dedicated baud rate generator At internal machine clock speeds of 6, 8, 10, 12, 16MHz.

• Asynchronous: 62500/38460/31250/19230/9615/4808/2404/1202 bps • • •

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15 8 7 0

SCR1 SMR1

SSR1 SIDR1(R)/SODR1(W)

– U1CDCR

(R/W)

(R/W)

(R/W)

8bit 8bit • Correct

15 8 7 0

SCR1 SMR1

SSR1 SIDR1(R)/SODR1(W)

– CDCR

(R/W)

(R/W)

(R/W)

8bit 8bit

294 19.3 Figure 19.3-2 was corrected as indicated by the shading below. • Error Prescaler control register

7 6 5 4 3 2 1 0 ←Bit No. Address: 000028H MD - - - DIV3 DIV2 DIV1 DIV0 U1CDCR

Read/write → (R/W) (-) (-) (-) (R/W) (R/W) (R/W) (R/W) Initial value → (0) (-) (-) (-) (1) (1) (1) (1)

• Correct Prescaler control register

15 14 13 12 11 10 9 8 ←Bit No. Address: 000028H MD - - - DIV3 DIV2 DIV1 DIV0 CDCR


298 19.3.2 The following description of "[bit 10] REC (Receiver Error Clear)" in "■ Serial Control Register 1 (SCR1)"

was corrected as indicated by shading below. • Error [bit 10] REC (Receiver Error Clear)

This bit clears the error flags (PE, ORE, FRE) in the SSR1 register. A write value of "1" is not valid, and the read value is "1" at all times.

• Correct [bit 10] REC (Receiver Error Clear)

Writing "0" to this bit clears the error flags (PE, ORE, FRE) in the SSR1 register. A write value of "1" is not valid, and the read value is "1" at all times.

302 19.3.5 The summary was deleted as indicated by the shading below.

The prescaler control register (U1CDCR) controls the machine clock frequency divider. The UART1 operating clock signal can be generated by dividing the machine clock signal pulse. The prescaler is designed to enable constant baud rates from a variety of machine clock speeds. The output from the prescaler is used by the I/O expanded serial interface.

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302 19.3.5 The following descriptions of "■ UART1 Prescaler Control Register (U1CDCR) " were corrected as indicated by shading below • Error

■ UART1 Prescaler Control Register (U1CDCR) The U1CDCR register has the following bit configuration.

Prescaler control register

15 14 13 12 11 10 9 8 ←Bit No. Address: 000028H MD - - - DIV3 DIV2 DIV1 DIV0 U1CDCR


• Correct

■ UART1 Prescaler Control Register (CDCR) The CDCR register has the following bit configuration.

Prescaler control register

15 14 13 12 11 10 9 8 ←Bit No. Address: 000028H MD - - - DIV3 DIV2 DIV1 DIV0 CDCR


306 19.4 The following descriptions of "❍ Internal timer" in "■ UART1 Clock Selection" were corrected as indicated

by shading below • Error

• • • When selecting the internal timer (16-bit timer0) as the baud rate clock source, note that the 16-bit timer0 output signal TOUT0 is already connected to the MB90435 controller internally. Therefore, it is not necessary to make an external connection from the 16-bit timer0 external output pins TOUT0 to the UART1 external clock input pin SCK1. Also, this means that unless used in some other fashion, the timer pins are available for use as I/O port pins.

• Correct

• • • When selecting the internal timer (16-bit timer0) as the baud rate clock source, note that the 16bit timer0 output signal TOT0 is already connected to the MB90435 controller internally. Therefore, it is not necessary to make an external connection from the 16-bit timer0 external output pins TOT0 to the UART1 external clock input pin SCK1. Also, this means that unless used in some other fashion, the timer pins are available for use as I/O port pins.

22/25



E2PROMMCU

F2MC16LX

SIN (UART)Pull-up resister

Connector

• Correct

E2PROMMCU

F2MC16LX

SIN

374 23.7.4 Figure 23.7-2 was corrected as indicated by the shading below.

N

Y

0

1

N

Y

N

Y

N

Start erasing

FMCS: WE (bit 5) Enable flash memory erase

Erase command sequence (1) FxAAAA <-- XXAA (2) Fx5554 <-- XX55 (3) FxAAAA <-- XX80 (4) FxAAAA <-- XXAA (5) Fx5554 <-- XX55

Sector EraseCompleted?

(6) Sector address <--Erase code (30H)

Another erase sector

Read internal address 1

Read internal address 2 Next sector

Toggle bit (DQ6) data 1(DQ6) = data 2(DQ6)

Timing limit (DQ5)



Toggle bit (DQ6) data 1(DQ6) = data 2(DQ6)

Erase error Final sector

FMCS: WE (bit 5) Disable flash memory erase

Complete erasing

Confirm with the hardware sequence flags.

Y

N

Y

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Oscillation or External clock

frequency

Maximum serial clock frequency that can be

input for the microcomputer

Maximum serial clock frequency that can be set

with AF220/AF210/ AF120/AF110

Maximum serial clock frequency that

can be set with AF200

4MHz 500kHz 500kHz 500kHz 8MHz*1 1MHz 850kHz 500kHz 16MHz*1 2MHz 1.25MHz 500kHz

*1: External clock only

• Correct

Oscillation or External clock

frequency

Maximum serial clock frequency that can be

input for the microcomputer

Maximum serial clock frequency that can be set

with AF220/AF210/ AF120/AF110

Maximum serial clock frequency that

can be set with AF200

4MHz 500kHz 500kHz 500kHz 8MHz 1MHz 850kHz 500kHz 16MHz 2MHz 1.25MHz 500kHz

401 APPENDIX

A Table A-1 was corrected as indicated by the shading below. • Error

Address Register Abbrevia

-tion Access Resource Initial value

000028H UART1 prescaler control

register U1CDCR R/W UART1 0---1111B

• Correct

Address Register Abbrevia

-tion Access Resource Initial value

000028H UART1 prescaler control

register CDCR R/W UART1 0---1111B

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Attachment 1 [Addition: Section 3.4.3]

3.4.3 Time Required to Start Interrupt Processing The time for terminating the currently executing instruction plus the interrupt handling time is required from generation of the hardware interrupt request to execution of the interrupt-processing.

■ Time Required to Start Interrupt Processing

The interrupt request sampling wait time and the interrupt handling time (time required for preparation for interrupt processing) are required from generation of the interrupt request and acceptance of interrupt, to execution of the interrupt processing. Figure 3.4-4 "Interrupt Processing Time" shows the interrupt processing time.

Figure 3.4-4 Interrupt Processing Time

Operation of CPU

Interrupt wait time

Execution of normal instruction Interrupt handling Interrupt processing

Interrupt request sample wait time

Interrupt handling time(θ machine cycle)∗

Interrupt request generated

: Last instruction cycle when sampling interrupt request.

: One machine cycle is equal to one clock cycle of the machine clock (φ).∗

Interrupt request sampling wait time

It indicates a time from the generation of the interrupt request to the termination of the currently executing instruction. Whether the interrupt request is generated or not is determined by sampling the interrupt request in the last cycle of each instruction. The CPU cannot recognize the interrupt request during execution of each instruction, as a result wait time occurs.

Reference: The interrupt request sampling wait time is longest when the interrupt request is generated

immediately after starting execution of the POPW, RW0,...RW7 instructions with the longest execution cycle (45 machine cycles).

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Interrupt handling time (θ machine cycles)

The CPU requires an interrupt handling time of θ machine cycles to save the dedicated registers to the system stack and fetch the interrupt vector table address after accepting the interrupt request. The interrupt handling time (θ) is obtained using the following equations.

θ = 24 + 6 x Z machine cycles (Z: compensation value of interrupt handling time) The interrupt handling time depends on the address set by the stack pointer. Table 3.4-2 "Compensation Value (Z) of Interrupt Handling Time" shows the compensation value (Z) of the interrupt handling time.

Table 3.4-2 Compensation Value (Z) of Interrupt Handling Time

Address Set by Stack Pointer Compensation Value (Z) For external area (8-bit address) +4 For external area (even address) +1 For external area (odd address) +4 For internal area (even address) 0 For internal area (odd address) +2

Reference: One machine cycle is equal to one clock cycle of the machine clock (φ).

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