cmos 1.8ghz vco
TRANSCRIPT
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8/17/2019 CMOS 1.8GHz VCO
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Low-Voltage,
Low-Power
and Highly-Tunable
1.8GHz CMOS LC
Voltage
Controlled Oscillator
L.
ouzerara,
M.T. elaroussi
Microelectronics and Nanotechnologies Division, Centre deEveloppement
des
Technotogies Avancks
Cite 20 Aofit 1956,
BP. 17,16303,
Baba Hassen,
Algiers,
ALGERIA
[email protected], [email protected]
Ahtruct-
A
fully integrated 1.8
CHz
low phase noise
LC-tank
W O
s presented
and analyzed.
Tho
phase noise
of
the oscillator
has been greatly reduced by means of integrated source
degeneration inductors.
The
phase noise achieved
is
-105,
-123
and -138
d W H z
at 100 KHz, 600 KHz and
3
MHz offs ts
respectively from the carrier frequency of 1.6 CHz w i t h 1.8 V
power supply volfage
and
giving a low p o w e r
consumptionof only
2.8
mW by
considering the
p r o w VCO
topology, which
consumes less power than the conventional differential
transconductor
pair.
A
15.8 broad
tuning
range
has
been
achieved by
using
the
standard mode
PMOS
vnroctors in
the
designed voltage tontrollod oscillator architecture.
The
tunability
of
the
designed VCO covers 290 MHz, from 1.69
CH2 up
to 1.98
CHz w i ~
VCO
gain
Kvco
of
320
MHzN.
I. INTRODUCTION
The fast emerging
of
modem telecommunication systems,
such as
DCS-1800,
GSM-celldar telephones, and the DECT
cordless telephones, has caused an increase in the demand for
low cost and
hi&
performance integrated radio-frequency
transceivers.
Of
all RF building blocks, voltage-controlled
oscillators are considered as the key element and have gained
the
most
attention in recent years.
Although
most commercial
designs
use
bipolar
or
GaAs technologies,
CMOS
is
a
promising candidate for full integration of RF front-ends,due to
its relatively low production cost. The design of high
performance monolithic VCOs in standard
CMOS
processes
has been
the
topic of several active research efforts [1-81. The
principal aim
is
to design a very low phase noise and low power
VCO
With high tuning range, able to fulfill
the
tight
specifications of
most
RF portable communication systems. A
major
challenge
in
the design of CMOS transceiver systems i s
the Phase-Locked-Loop Frequency synthesizer that generates
the local oscillator carrier signal. The 'phase noise of the
synthesizer is the
most critical parameter
for
the
quality and
reliability of the information transfer. It
is
well known that the
phase
noise
performance
of a PLL
is
essentially determined by
the phase noise
of
the VCO. Due to the vety narrow
communication
channel
spacings,
the
output signal
of
the
PLL
must be a very pure sinusoid.
t
is therefore of
major
importance
to
design a low power, low-phase-noise oscillator.
L C - d
voltage-controlled oscillator is a better choice than relaxation
or
ring oscillators
to
fulfill the stringent
high
frequency and noise
specifications
[ I , 21, [6-8]. A monolithic LC-tank VCO
requires
the
integration
of high quality
passive components
such
as inductors
and
varactors
in
standard
CMOS
echnology. The
design becomes more challenging, when a hgh hming range is
n e c e s q to provide the required frequency band over process
varktions. The
cambination
of
a Wide
tunkg
range
and low
power supply voltage requires a high VCO gain,which makes
the oscillator
much
more sensitive
to
voltage noise
induced
phase noise. The use of integrated degeneration inductors
h a s
proven very effective to reduce
the
phase
noise
of
the oscillator
[4, 51. The present work applies the above idea to the
sy me tn ca l architecture-of he LC-tank
VCO.
In
t h i s paper, llly integrated l.8GHz voltage
~ ~ n t r ~ l l e d
oscillator, tuned by
PMOS
varactors, is presented and analyzed
that combines a
wide
t g range at very low power supply
voltage
with a low phase
noise performance and stdl achieves
the
specifications necessary for DCS-1800, GSM and DECT
mobile communication 'systems. Among
major
issues
in
designing a voltage controlled oscillator is its power
consumption. It is therefore imperative that the' power
consumption
of
the
VCO
be
minimized
to lower overall power
consumption
of
low power wireless systems. For this purpose,
the proposed VCO topology exploits the concept of new linear
and low
power
differentialtransconductor architectures
[9,
101,
connected
to
act as negative resistors, wtuch consume
less
power than the classical
LC
oscillator using,theconventional
differential transconductor pair. The paper is organized as
follows: in section 2, the
propoxd
designed VCO circuit is
presented
and
analyzed.
In
section
3,
the obtained results are
depicted while in last section, are presented the conclusions and
perspectives.
11.
.ANALYSISF HE DESIGNEDMOS
LC VCO
Generally, the quality factor of an
LC
oscillator, which
is
mainly determined
by
the inductor in
the
resonator,
is
especialIy
important
due
to its effect on the
globat
pbse
noise
performance
of
the voltage controlIed oscillator. A simplified
equation
for
oscillator phase noise presents the relation between
the
quality factor and the output
power
of
the signal
produced
by the
oscillator,
to
the
normalized
single side-band
noise
spectral density
[
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current in the inductor which flow in the opposite direction in
the substrate.
I
I
0x1O p x O . 3 5 V
[
3ox
ouxo 35u
I
1
0.7nH
Figure
1. The
designed VCO
topology.
This effect reduces the effective inductance and increase the
effective series resistance so that the quality factor is reduced.
The other is the skin effect which forces the current in the
inductor to flow on the outside of the spiral. Ths makes the
inner turns
of
the spiral less effective than the outer
tuns
and
the effective series resistance higher. The optimal layout of an
inductor depends
on
the inductance value, the particular
process, and the frequency of operation. t radio-frequency,
quality factors r a n p g from 3 to
20
have been reported in
recent publications [4, 15,
16,
171.
111. SIMULATION RESULTS AND DISCUSSiON
Predicted performance has been confmed by simulations using
Eldo-RF and IC-Layout tools from Mentor Graphics.
All
simulations are
based
on
0.35pm
CMOS TSMC technology
(three
metal layers, two poly layers, twin tub, Ve0.46V,
VTp=4.61V,
Lx=7
m .The VCO operates at 1.8 V power
supply voltage with a bias current of I .55 mA
by
using a
simple
resistor and giving a power dissipation of only 2.8
mW,
obtained by means of R new linear and low power differential
transconductor
topology
[IO] connected to act as a negative
resistor
in
the proposed
VCO
topology, thus
consuming
less
power than the classical LC
VCO
using the conventional
differential ransconductor pair which consumes 5.5mW.
The phase noise of the proposed VCO achieved is -105, -123
and
-138
dBc/Hz
at IO0 KHz, 600 K f i and 3 MHz offsets
respectively from the carrier frequency of 1.8 GHz. The phase
noise performance of the VCO is shown in figure 2. This figure
shows
clearly the effect of
the
inductive degeneration on the
phase noise performance of the oscillator where
the phase
noise
of
the
VCO is -102,
-I20
and -135 dBc/Hz at 1 KHz, 600
KHz and 3 MHz offsets respectively, Without the two
degeneration inductors.
The
oscillator’s tuning range is 15.8
1.69GHz-1.98GHz)s depicted in
figme 3 ,
and havlng a gain
of 320 MHzN This
value
corresponds to a control voltage
ranging from to 1 .W .
In
th ls design,
ASITIC
software has been used to optimize the
design of circular inductors in 0.35pm
CMOS
technology with
three Metal layers, by lowering
their
series resistances.
A
wide
Metal 3 turns have been used to achieve the quality factors
given in
the
table
1 .
The geometrical characteristics and
parameters of the designed circular inductors
are
listed in table
1.
The VCO, presented and analyzed
in
h s paper, addresses the
problem of
fully
tunable, low
power
consumption oscillator,
designed in standard
0.35pm
CMOS
TSMC
process. s we
have seen, the standard mode
PMOS
varactors used in the
VCO, allow a
hgh
tuning range wth the moderate contribution
of the transistors M,, A and degeneration transistormq sed
in
the proposed
VCO
topology. For a maximal varactor quality
factor, a
minimum
channel length of 0.35pm should be
preferred to minimize the resistive paths
in
the
channel. A
high
Q varactor helps
filter
phase
noise and a high linearity
prevents
modulation of the varactor by the R signal, which up-converts
bias noise. Each varactor
is
laid
out
with
200
fingers which are
IOpm wide and
0.35pm
ong.
In the VCO archtecture, multi-fingers
MOS
iransistors have
been considered in simulations and analysis, for “ a 1 gate
resistance and low
noise
devices
(with
aminimal channel length
of 0.35pm).
-50
-85
z
s
z
- 1 2 0
E
P
UI
z
n
-155
-190
i ,E 03 1 , E 0 4 l . E O S
i,E 06
,E+07 . E O B I .E 0 9
Offset f requency, Hz
Figure
2. Sindated
phase
noise performance for VCO
at
1.8
GHz carr~er
frequency
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290 MHZ
obtained by using
the
standard-
mode PMOS
varactors
in
the
proposed
VCO architecture. Such
a
designed
voltage controlled oscillator topolojy, t a n d s as an interesting
arrangement
to
dissipate
less
power and to get more
linear
oscillator than the standard
LC
VCO
which
uses the
’
conventjonal differential transconductor pair. The proposed
VCO could
be
a
good
and promising candidate for the
implementation
of
low
power
and
low
cost frequency
synthesizers
used
in DCS-1800, GSM and
DECT
mobile
communication sys t ems .
REFERENCES
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J.
C ~ h c k x ,
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steyaett,
“A 1.8
HzCMO S Low-Phase Noise Voltage
Controlled Oscillator Wth h c a l d ’ , IEEE Journal of Solid-state
Circuits, vol . 30, No.
12,
pp
1474-1482, December 1995.
J.
Craninckx,
M .
steyaerl, “A 1.8 GHz CMOS Low-Phase Noise
CMOS
VCO Using Optimized Hollow SpiraI Inductom’:, EEE Journal of Solid-
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Deantani and R. Castello, “A
1.3GHz
Low-Phase Noise
Fully Tunable CMOS LC
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Journal
of
Solid-Statc Circuits,
E.
Hegwi.
H.
Sjoland and
A . A
Abidi,
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Filtering Technique to Lower
LC Oscillates Phase Noise”, IEEE Joumal of Solid-state Citcuits, Vol.
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N0.12 pp.
1921-1930, Deoemba2001.
P. Andreani and
H. Sjoland,
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Current
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CMOS VCOs”, IEEE Journal
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Soiid-State C/rcuits, Vol.
37,
NO.3, pp.
342-348,
March 2002
T.I. Ahrens, A. Hajimiri and T.H. Lee, “A 1.6
GHz 0.5
m W CMOS LC
Low Phase Noise VCO. Using Bond wire Inductance”, 1st International
Workshop on Design of Mixed-Mode Integrated Circuits and
Applications,Mexico,
p- 69-71,
July 1997.
L. Bouzerara,
M.T.
Belaroussi, A.
Ziouohe,
’‘
A 2
G k
Low Power.
Highly Tunable and Low
Phase
Nolse Monolithic LC VCO in 0 . 3 5 ~
CMOS Technology”,
16th
International Conference on M icroe~ec tronics,
ICM’04,
Tunisia,pp. 21 1-214, December 2004.
T.I. Ahrens
snd T.H. Lee, “ A
1.4
GHz
3 mW
CM O S
LC
Low
Phase
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Bond
wire InductMces”, International
Symposium
on
Low Power Electronics and Design, California, pp. 16-19,
August 1998.
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H. Rem Sadr
M.
N,
A
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0th
IEEE
hternational Conference
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Electronics, Circuits and Systems
ICECS
2003,
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pp.
412-415,
December
2003.
[ I O ]
H.
R e a
Sadr M: N, “A
Novel Approach to
the
Linearization
of
the
Differential Transconducton
”,
IEEE
International
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Circuils and Systems,
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Noise:
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D.B.
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A. M.
Niknejad,
and R.
G.
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of Spiral Inductors and Transformers for Si RF IC’s,” IEEE J. Solid-state
Cirouits, vol. 33, no. O . pp-
1470-1481.
Oct. 1998.
[I41
J. Crols, P. Kinget,
J.
Craninckx, and M. .
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[4]
[S ]
[61
[7]
[SI
U
E
e
1.65
0.3 0 6 0,Q 1.2
1 5 1.8
Tun ing
Voltage,
V
Figure 3. Simulated
tuning
range of he proposed VCO
TABLE
L
GEOMETRICAL
HARACERISTICS
AND
PPARAMETERS OFTHEDESIGNEDCIRCULAR NWCTORS
Radius
(pm) ’ [ 200 I[ 115 I
Figure 4.
Layout
of the
proposed
VCO
v. CONCLUSIONS
AND PERSPECTIVE S
A 1 8 GHz
fully
integrated voltage controlled oscillator has
been
designed,
analyzed and simulated using
0.35pm
CMOS
technology. The use of the inductive degeneration allows a
considerable reduction
of
the tail
current
noise, which is the
main cause of phase noise in a CMOS differential VCO As a
result the VCO exhibits a good phase noise performance of -
1 2 3 d B c f i at 600 KHz
offset from
the camer
o f 1.8 GHz
while
the
tunability is 15.8
of the
central frequency or else
390