cmos analog integrated circuits: models, analysis, & design
DESCRIPTION
CMOS Analog Integrated Circuits: Models, Analysis, & Design. Dr. John Choma, Jr. Professor of Electrical Engineering University of Southern California Department of Electrical Engineering-Electrophysics University Park; Mail Code: 0271 - PowerPoint PPT PresentationTRANSCRIPT
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CMOS Analog Integrated Circuits:
Models, Analysis, & Design
CMOS Analog Integrated Circuits:
Models, Analysis, & Design
EE448
MOS Circuit Level Models
Fall 2001
Dr. John Choma, Jr.Professor of Electrical Engineering
University of Southern California Department of Electrical Engineering-Electrophysics
University Park; Mail Code: 0271Los Angeles, California 90089-0271
213-740-4692 [OFF] 626-915-7503 [HOME]
626-915-0944 [FAX][email protected] (E-MAIL)
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Lecture Overview Lecture Overview
2
•Static ModelCutoff RegionOhmic (Triode) Region ModelSaturation Region ModelSubthreshold Model
•Short Channel Effects In SaturationChannel Length ModulationSubstrate/Bulk PhenomenaMobility DegradationCarrier Velocity Saturation
•Small Signal Model In SaturationForward TransconductanceBulk TransconductanceCapacitances
•Sample Circuit Analysis (Inverter)GainBandwidth
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N–Channel MOSFET
N–Channel MOSFET
3
Is = Id + Ig + Ib
Ig 0
Ib 0, for Vbs < 0
I s Id
Vds = Vgs – Vgd
Silicon Dioxide
B
L
Tox
S DG
N+
Sourc
e N+
D
rain
LdLd
WXd
P–Type Substrate (Concentration = ND cm-3 )
Id
D
G
S
Vds
B
Vbs
Vgs
Vgd
Ig
Is
Ib
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P–Channel MOSFET
P–Channel MOSFET
4
Is = Id + Ig + Ib
Ig 0
Ib 0, for Vsb < 0
I s Id
Vsd = Vsg – Vdg
D
G
S
Vsd
B
Vsb
Vdg
Ig
Is
Ib
Id
Vsg
Silicon Dioxide
B
L
Tox
S DG
P+
Sourc
e P+
D
rain
LdLd
WXd
N–Type Substrate (Concentration = ND cm-3 )
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Characteristic Curves: Cutoff And Ohmic Regimes
Characteristic Curves: Cutoff And Ohmic Regimes
Cutoff Regime: Threshold Voltage, Function Of Bulk–Source Voltage
Ohmic Regime:
(Hundreds Of µmhos/Volt)
Comments W/L Is Gate–Channel Aspect Ratio, A Designable Parameter
Temperature Effects (Holes And Electrons):
Resistance For Small Drain–Source Voltage:
5
Vgs < Vhn
I d = 0
Vhn
I d = K n W L
Vds Vgs – Vhn – Vds 2
Kn = µn Cox = µn ox Tox
Vds = Vgs – Vgd < Vgs – Vhn Implies Vgd > Vhn
µ(T) µ(To)
To T
3 / 2
Vgs – Vhn – Vds
Vgs – Vhn – Vds
2
Vgs Vhn and Vds < Vgs – Vhn
Id
Vds 1
Rds = Kn
W L
Vgs – Vhn – Vds = Id
Vds
Id
Vds
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Characteristic Curves: Saturated Regime
Characteristic Curves: Saturated Regime
Saturation Regime:
Comments Square Law Voltage–Controlled Current Source Drain Current Shows Negative Temperature Coefficient
Because Of Its Proportionality To Mobility Differential Current Of Two Matched Devices Is Linear With
Differential Gate–Source Voltage , Provided Common Mode Gate–Source Voltage Is A Constant
6
Vgs Vhn & Vds Vgs – Vhn
I d = K n 2
W L
Vgs – Vhn 2
Vdss Vgs – Vhn Drain Saturation Voltage
Idss = Kn 2
W L
Vdss 2 Drain Saturation Current
I d1 – I d2 = K n 2
W L
Vgs1 – Vhn 2 – Vgs2 – Vhn
2
I d1 – I d2 = K n W L
Vgs1 + Vgs2
2 – Vhn Vgs1 – Vgs2
I d1 – I d2 = K n W L
VCM – Vhn VDM
VDM VCM
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Simple Differential Pair
Simple Differential Pair
6a
Vgs1 = VCM + VDM
2
Vgs2 = VCM – VDM
2
Vgs1 + Vgs2 = 2 VCM
c
R
c
Id2Id1
M1 M2
R
+VDDc
Vo +–
+
–
VDM2
–
+
VDM2
+
–
VCM
c Vgs1 – Vgs2 = VDM
I d1 – I d2 = K n W L
VCM – Vhn VDM
Vo = R I d1 – I d2 = K n R W L
VCM – Vhn VDM
Inputs
Response
Note Differential Output Current And Voltage Are Linear With Respect To Differential Input Voltage Without Invoking Small Signal Approximation
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Characteristic Curves: Subthreshold Regime
Characteristic Curves: Subthreshold Regime
7
Subthreshold Regime:
Comments Bipolar Type I–V Action Indigenous To Subthreshold Regime Subthreshold Operation Corresponds To Gate–Channel Interface Potentials Lying Between One And Two Fermi Potentials Useful Only For Low Speed, Low Power Applications
Vgs < Vhn + 2 n VT & Vds 3 VT
VT = k T q
= 26 mV @ 27 8C
1.2 < n < 2.0
Id = 2 Kn W L
n VT
2
e( Vgs – Vhn ) / n VT
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Sample Simplified MOS Static Characteristics
Sample Simplified MOS Static Characteristics
Drain-Source Voltage (volts)
0
100
200
300
400
500
600
700
0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4 4.8
Gate-Source Voltage = 2 volts
3 volts
4 volts
5 volts
DrainSaturation
Current
SaturationRegime
OhmicRegime
Drain Current (microamperes)
K n W
L = 80 µmho/volt
Vhn = 1.2 volts
8
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Depletion
Zero Current
Voltage Across Oxide
Interface Potential
Vds
P–Type Substrate
DEPLETION LAYER, V 0ds
SiO 2 Id
S D
Gc
Vgs
N+
D
rainN
+
Sourc
e
DEPLETION LAYER, V = 0ds
B
Vbs
Fixed Immobile Charges
Vds 0
0 < Vgs < Vhn
Vbs 0
Vgs = Vox + Vy
Vox
Vy
Cutoff Regime
Cutoff Regime
9
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Channel Inversion: Ohmic Regime
Channel Inversion: Ohmic Regime
10
Vgs > Vhn
Vds = 0
Vgs > Vhn
0 Vds Vgs – Vhn
Vgd > Vhn
N+ Drain
P–Type Substrate
N+
Sour
ce
N+ Drain
P–Type Substrate
N+
Sour
ce
L
L' DL
DVds
Metal or Polysilicon
Silicon Dioxide
Inversion Layer
Depletion
DSG
DSG
Vdss
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Channel Inversion: Saturation Regime
Channel Inversion: Saturation Regime
11
Vgs > Vhn
0 Vds = Vgs – Vhn
Vgd Vhn
Vgs > Vhn
0 Vds > Vgs – Vhn
Vgd < Vhn
N+ Drain
P–Type Substrate
N+
Sour
ce
N+ Drain
P–Type Substrate
N+
Sour
ce
L
L' L
Vds
Metal or Polysilicon
Silicon Dioxide
Inversion Layer
Depletion
DSG
DSG
Vdss
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Channel Length Modulation
Channel Length Modulation
Modified Saturation Regime Current
12
Id | Vds > Vdss
= Idss L
L – L =
Kn 2
W L
Vgs – Vhn 2
1 + Vds – Vdss
V
V = L 2
q
NA
s
Vds
– Vdss
+ Vj
Vdss = Vgs – Vhn
V j =
k T q
ND
NA
N iB 2
ln (Typically Under 20 Volts And As Small As 1/3 Volt For Deep Submicron MOSFETs)
Channel Modulation Voltage
N+ DrainN+
So
urce
L' DL
Vds
DSG
Vdss
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Channel Length Modulation Parameters
Channel Length Modulation Parameters
13
Parameters Average Substrate Impurity Concentration Dielectric Constant Of Silicon (1.05 pF/cm) Electronic Charge Magnitude Channel Length Modulation Voltage Built In Substrate–Drain/Source Junction Potential
Note Large Channel Length Reduces Channel Modulation Small Substrate Concentration Increases Channel Modulation
NAesq
Vl
Vj
Modified Saturation Regime Current
Id | Vds > Vdss
= Idss L
L – L =
Kn 2
W L
Vgs – Vhn 2
1 + Vds – Vdss
V
V = L 2
q
NA
s
Vds
– Vdss
+ Vj
Vdss = Vgs – Vhn
V j =
k T q
ND
NA
N iB 2
ln
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Substrate/Bulk Phenomena
Substrate/Bulk Phenomena
Effect On Threshold Voltage
Parameters Fermi Potential; Renders Channel Surface Intrinsic Intrinsic Carrier Concentration In Substrate Dielectric Constant Of Silicon Dioxide (345 fF/cm)
Note Small Oxide Thickness Reduces Threshold Modulation Small Substrate Concentration Reduces Threshold Modulation
VFNiB
14
(High Hundreds Of µVolts)
(Few Tenths Of Volts)
ox
Id = Kn 2
W L
Vgs – Vhnc 2
1 + Vds – Vdss
V
V = q NA s
Cox 2
= q NA s Tox ox
2
VF = VT ln NA N iB
Vh = Vho + 2
V
VF
– VT
1 –
Vbs
2 VF – VT
– 1
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Threshold Voltage Modulation
Threshold Voltage Modulation
Threshold Correction (volts)
Bulk–Source Voltage, Vbs (volts)15
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
-6 -5 -4 -3 -2 -1 0
Oxide Thickness = 1,500 A
750 A
100 A
50 A
N iB = 1010 cm–3 ; NA = (10)14 cm–3
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Mobility Degradation Due To Vertical Field
Mobility Degradation Due To Vertical Field
16
Electric Field Problems Thin Oxide Layers Conduce Large Gate -To- Channel Fields
For Even Small -To- Moderate Gate–Source Voltages These Enhanced Fields Impart Increasing Energies To Carriers,
Thereby Causing More Carrier Collisions And Degraded Mobilities
Mobility:
Parameters Effective Carrier Mobility In Channel
Vertical Field Degradation Voltage Parameter
Crude One Dimension Approximation To Two Dimensional Problem in MKS Units Yields In Volts
µneff
Tox VE
VE
µneff µn
1 + Vgs – Vhnc
VE
VE (500)(10 6 ) Tox (Low Hundreds Of Volts)
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Impact Of Mobility Degradation
Impact Of Mobility Degradation
17
Static Drain Current
Other Effects Reduced Bandwidth And Increased Carrier Transit Time Smaller Current For Given Gate–Source Bias Reduced Forward Transconductance
Kn = µn Cox Kneff = µneff Cox
Id = Kn 2
W L
Vgs – Vhnc
2 1 +
Vds – Vdss V
1 + Vgs – Vhnc
VE
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Mobility Degradation Due To Lateral Field
Mobility Degradation Due To Lateral Field
18
Electric Field Problems Short Channels Conduce Large Drain -To- Source Fields
For Even Small -To- Moderate Drain–Source Voltages These Enhanced Fields Impart Increasing Energies To Carriers,
Thereby Causing More Carrier Collisions And Degraded Mobilities At Very Large Horizontal Fields, Carrier Velocities Ultimately
Saturate To A Value Of , Which Is About 0.1 µm/pSEC Saturation Occurs When Horizontal Field, ,Equals Or Exceeds A
Critical Value, , Which Is About 5 V/µm
Mobility And Field
vsatEh
Ec
µne µn
1 + Eh E c
=
vsat E c + Eh
vsat = µn E c
v = µne Eh µn Eh
1 + Eh E c
E h Vgs – Vhn
L
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Velocity – Mobility – Field Relationships
Velocity – Mobility – Field Relationships
18a
Lateral Electric Field (V/µm)
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.1
0 5 10 15 20 25 30 35 40 45 50
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1Carrier Velocity (µm/psec) Normalized Carrier Mobility
Carrier Velocity
Normalized Mobility
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Mobility And Lateral Field
Mobility And Lateral Field
19
Mobility And Field
Electric Field Problems Crude Approximation For Horizontal Field, Free Carriers Exist Only Over Channel Where Voltage With
Respect To The Source Is At Most Channel Length, L, Should Be Effective Channel Length, L',
But This Shrinkage Is Already Accounted For By Channel Length Modulation Voltage Parameter,
Is About 1.75 Volts For L = 0.35 µm
Eh
V
E h Vgs – Vhnc
L =
Vdss L
µne µn
1 + E h E c
µn
1 + Vgs – Vhnc
L E c
= µn
1 + Vdss L E c
Vdss = Vgs – Vhnc
L Ec
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Volt–Ampere Impact Of High Lateral Field
Volt–Ampere Impact Of High Lateral Field
Static Drain Current
Very High Fields
Comments Drain Current Scales Approximately With W, As Opposed
To W/L Drain Current Almost Linear W/R To Gate–Source Voltage
20
Kn = µn Cox Kneff = µneff Cox
Id = K n 2
W L
(Vgs – V )hnc 2
1 + Vds – Vdss
V
1 + Vgs – Vhnc
L E c
Vgs – Vhnc >> L E c
Id W Cox vsat
2 Vgs – Vhnc 1 +
Vds – Vdss Vl
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MOS Large Signal Model
MOS Large Signal Model
Gate-Drain Capacitance
Gate-Source Capacitance
Drain-Bulk Capacitance
Source-Bulk Capacitance
Drain Overlap Capacitance
Source Overlap Capacitance
DBD Bulk-Drain Diode
DBS Bulk-Source Diode
21
Cgd
Cgs
Cdb
Csb
Cold
Cols
c c
c
c
c
c
c
DBD
id
B
S
D
G
Id
rdb
DBS
c
Csb
cc cc
Cgd
Cols
Cgs
Cold
Cdb
rbbrsb
rdd
rss Drain Ohmic Resistancerdd
Source Ohmic Resistancerss
Bulk Ohmic Resistancerbb
Bulk Spreading Resistancersb
Bulk Spreading Resistancerdb
Static Drain Current
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Device Capacitances In Saturation
Device Capacitances In Saturation
22
c c
c
c
c
c
c
DBD
id
B
S
D
G
Id
rdb
DBS
c
Csb
cc cc
Cgd
Cols
Cgs
Cold
Cdb
rbbrsb
rdd
rss
Drain-Bulk Junction Area
Source-Bulk Junction Area
Zero Bias Depletion Capacitance Density
Ad
As
Cjo
Cgd + Cold Cold = W Ld Cox
Cgs = W L Cox 2 3
+ L d L
Cdb = Ad C jo
1 – Vbd
V j
Csb = As + W L C jo
1 – Vbs
V j
Cols = W L d Cox
Large (Hundreds Of fF)Cdb
Large (Hundreds Of fF)Csb
Moderate (High Tens Of fF)Cgs
Cgd , Cold , Cols Small (Tens Of fF)
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Approximate (Long Channel) Small Signal Model
Approximate (Long Channel) Small Signal Model
23
cc
cc
c
B
D
G
gmf vga go
vba + vga
Cold
+
cc
Cgd
c
c
gmb vba
Cgs
Cdb
c
Csb
Colsc
S
Assumptions All Series Ohmic Resistances Are Negligible Transistor Operates In Saturation Regime "Long Channel" Approximation Invoked For Static Drain Current Model To Be Used As A Precursor To Computer–Based Studies
gmf
Id
Vgs | Q
2 Kn W
L
IdQ
gmb Id
Vbs
| Q
= b gmf
b = V
/ 2 2 VF – VT – VbsQ
go
Id
Vds
| Q
IdQ
V + Vds – Vdss
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Short Channel Small Signal Model
Short Channel Small Signal Model
24
Drain Current:
Intermediate Parameters:
Forward Transconductance:
Bulk Transconductance:
Output Conductance:
Id = Kn 2
W L
Vgs – Vhnc 2
1 + Vds – Vdss
V
1 + Vgs – Vhnc
L E c
f = Vds – Vdss
V f c =
Vdss L E c
gmf = 2 K n W
L
I dQ
gmfs = gmf 1 + f
1 + f c
1 – Vdss /2 V
1 + f
– f c /2
1 + f c
gmbs = b gmfs
go = IdQ
V + Vds – Vdss
b = V
/ 2 2 VF – VT – VbsQ
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Hypothetical Device
Hypothetical Device
25
Physical ParametersNA = 5 (10) 14 cm –3
ND = 5 (10) 20 cm –3
N iB = (10) 10 cm –3
s = 1.05 pF/cm
ox = 345 fF/cm
µn = 400 cm 2 / volt-sec
Ec = 4 volts/ µm
Device ParametersTox = 50 Angstroms
L = 0.35 µm
Vhn = 0.65 volts
T = 300 8K
W / L = 5
Circuit ParametersVds = 2 volts
Vgs = 1.2 volts
Vbs = –3 volts
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Static Performance
Static Performance
Peripheral Calculations
26
VF = 280.0 mV (Fermi Potential)
Vj = 917.4 mV (Junction Potential)
Vu = 176.4 µV (Body Effect Potential)
Vhnc = 685.2 mV (Compensated Threshold) Vhn = 35.2 mVVdss = 514.8 mV (Drain Saturation Voltage)
V = 669.7 mV (Channel Length Voltage)L Ec = 1.4 volts (Lateral Field Voltage)
Kn = 276.0 µmho / volt (Transconductance Parameter)f = 2.218 (Channel Length Parameter)f c = 0.368 (Lateral Field Parameter)
I d = 182.9 µA (Long Channel Drain Current)
I d = 430.2 µA (Short Channel Drain Current)
Static Drain Current Note Short Channel -To- Long Channel Ratio of 2.35; Ratio Is
Generally Between 1.5 And 3.0
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Small Signal Parameters
Small Signal Parameters
27
Forward Transconductance Note Short Channel -To- Long Channel Ratio of 1.14; Ratio Is
Generally Between 0.5 And 2.0
Bulk Transconductance Note Bulk Transconductance Is About 200 Times Smaller
Than Forward Transconductance
Drain–Source Conductance Corresponds To Shunt Output Resistance Of About 5 K Mandates Conductance Enhancement Strategies When
Designing High Performance Transconductors
gmf = 1.09 mmho (Ignoring Short Channel Effects)
gmf = 1.25 mmho (Incorporating Short Channel Effects)
(10) –3b = 5.02 (Bulk Parameter)
gmb = 6.25 µmho (Incorporating Short Channel Effects)
go = 199.7 µmho (Incorporating Short Channel Effects)
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Device Unity Gain Frequency
Device Unity Gain Frequency
Comments Unity Gain Frequency Is Good Device Figure Of Merit;
Crude Circuit Performance Figure Of Merit Result Assumes T Cgd << gmf
AC Short Circuit
28
iout iin
= gmf – s Cgd + Cold
s Cgs + Cols + Cgd + Cold
T gmf
Cgs + Cols + Cgd + Cold
µn Vgs – Vhn
L
2 2 3
+ 3 Ld L
c
c
c
BS
D
G
gmf
v1
gmb
v2
go
v2 + v
1+
c
c
Vdd
c
Ibias Cbig
c
iouti in i in
c
iout
Cgd Cold+
Cgs Cols+
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Common Source Inverter
Common Source Inverter
29
VDDML
MD
LC
Vo
Vs
VGG
MD
LC
Vos
RLeff
Schematic Diagram AC Schematic Diagram
RLeff
c
+
+
–
–Vs
+
–
c
c
cc
c
c
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Inverter Load Resistance Calculations
Inverter Load Resistance Calculations
30
ML
IxVx
rol
rbblrssl
rddl
vba
c
c
+
–
gmfl vga
vga+ –
IxVx
+
–
gmbl vba
+–
c
c c c
vga = vba = – Vx + rssl I x
Vx = rssl + rddl I x + rol I x + gmfl vga + gmbl vba
RLeff Vx Ix
= rssl + rddl + rol
1 + 1 + bl gmfl rol
1
1 + bl gmfl
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Inverter Gain Calculations
Inverter Gain Calculations
31
gmbdvbarod
rbbd
vba +–vga
rssd
rddd
+ –gmfd vga
LC
Vos
Vs
+
–
RLeff
RoutR '
Ignore For Low
Frequencies
c
cc
cc
cMD
LC
Vos
RLeff
c
Vs
+
–
c
c
Av = Vos
Vs = –
gmfd RLeff
1 + 1 + bd gmfd rssd + RLeff + rddd + rssd
rod
– gmfd RLeff – gmfd
1 + bl gmfl
Av – 1
1 + bl
Wd
/ L
W l / L
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Inverter Bandwidth Calculations
Inverter Bandwidth Calculations
32
IxVx
+
–
gmbdvbarod
rbbd
vba +–vga
rssd
rddd
+ –gmfd vga
R '
c cc
c
R/ =
Vx Ix
= rddd + rssd + 1 + 1 + bl gmfd rssd rod
B3dB 1
RLeff CL
1 + bl gmfl
CL
B3dB = 1
Rout CL =
1
R/
| RLeff CL
1
RLeff CL
GBP Av B3dB = gmfd
CL