cmos analogue switches structure and specifications

Application Note

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CMOS Analogue Switches – Structure and Specifications

Introduction CMOS analogue switches are the solid state equivalent of mechanical switches (toggle, pushbutton and relay). Unlike their mechanical equivalents, CMOS analogue switches have no moving parts and are free of contact bounce, contact deterioration, and fatigue induced lifetime limits. CMOS switches require very low power to operate, are able to switch in tens of nanoseconds or faster, and naturally support analogue swings up to and including the power rails. Unlike their mechanical equivalents, CMOS analogue switches have variable on resistance, temperature sensitive leakage currents, and significant current handling limits. The following is an overview of analogue switch structure, operation and the designer specifications that are used to describe the overall operation.

The Basic Switch CMOS (complementary metal-oxide semiconductor) combines P-channel and N-channel enhancement mode FETs (Field Effect Transistors) on a common substrate. P-channel devices have a negative threshold, and require at least a volt between gate and source in order for current to flow between drain and source. N-channel devices require a positive voltage between gate and source for current to flow between drain and source. When a P-channel device is used as a switch, the gate is taken to the most negative voltage, and the device is low resistance for analogue swings over most of the dynamic range set by the gate source voltage. As the analogue signal approaches the gate-source threshold, on resistance rises steeply until the device is no longer conducting. The N-channel device behaves in a complementary manner. Fig 1 illustrates this characteristic. Fig 1: Resistance versus Gate-Source Voltage for N-channel and P-Channel FETs

Source Voltage-V +V

Resistance

VTH (N)VTH (P)

-V +VD

S

G

DN-ChannelP-Channel

S

G

Composite Resistance Curve

P-ChannelResistance

N-ChannelResistance

The problem of single polarity on resistance variation is overcome by connecting an N-channel device in parallel with a P-channel device. The N-channel gate is tied to the positive rail, and is turned on the most when the source (analogue signal path), is most negative. The composite on-resistance curve of parallel connected P- and N-channel devices is shown in Fig 1. A CMOS switch “cell” including the control circuitry is shown in Fig 2. It is assumed that the complementary VCONTROL voltages are generated from level shifters that provide rail-to-rail voltage swings to the gates of Q1 and Q2.


Fig 2: CMOS Switch with control Circuitry

VCONTROL

VCONTROL

+V

-V

Analogue Signal Input

Analogue Signal Output

Q1

Q2

Q3 Q4

Q5

Logic Level Threshold and Level

Shifter

+VSUPPLY

0V

Control

When VCONTROL is HIGH, the transmission path is ON. The equivalent circuit is shown in Fig3A. The N-channel gate is taken to a high state and the P-channel gate to a low state. The substrates of Q1 and Q2 are joined together by the auxiliary switches Q3, Q4, and Q5. Q3 and Q4 are OFF when Q5 is ON. This helps to keep the overall switch resistance from being a function of the analogue signal potential. When VCONTROL is LOW, the transmission path is OFF, and has the equivalent circuit shown in Fig 3(B). The bulks of the N- and +-channel have been taken to –V and +V respectively since Q3 and Q4 and ON and Q5 is OFF. This ensures that the OFF state will be maintained, since VBULK-SOURCE is strongly reversed biased and this results in a much increased threshold voltage of the local FET. Fig 3: (A): ON-state and (B): OFF-state

The structure of an N-channel and P-channel MOS transistor using an example P-well technology is shown in Fig 4.The P device is formed with two heavily doped p+ regions diffused into a lighter doped n- material called the substrate (or bulk). The two p regions are called drain and source, and are separated by a distance L, known as the device length. At the surface between drain and source lies a gate electrode that is separated from the silicon by a thin insulating layer of silicon dioxide. Similarly, the N device is formed by tow heavily doped n+ regions within a lightly doped p- well or tub (for p processes). It also has a gate electrode on the surface between drain and source.


Fig 4: Physical Structure of a PMOS and NMOS transistor in P-Well CMOS Technology

The on-resistance of each device is geometry related. For a given “length” (L), on resistance is reduced by increasing the dimension “width” (W) of the device. As the ratio W/L is increased, so the on-resistance is reduced. Leakage and stray capacitances increase as the ratio W/L is also increased. For a given on-resistance, the P channel geometry will be larger than that for the N-channel device. This is because the conductance of N-doped silicon is some 2.5-2.8 times greater than that of equally doped P-type material.

Switch Architecture Like their mechanical counterparts, analogue switches are offered in a variety of architectures, choice of which depends on the application. Fig 5 shows examples of common switch arrangements. Fig: 5 Switch Arrangements

AS1741: Dual SPST (Single Pole Single Throw), NO (Normally Open) switches. AS1742: Dual SPST (Single Pole Single Throw), NC (Normally Closed) switches.

AS1743: Dual SPST (Single Pole Single Throw), 1 x NC and 1 x NO switches. Normally open switches are OFF when the logic command is LOW. Normally closed switches are ON when the logic command is LOW. Note that power must be applied to the switches for these conditions to be true.


DC Measurements

Analogue Signal Range This specification identifies the limits of signal swing that can be handled by the switch. The limits are determined by the power supplies, since the gate and bulk connections are clamped to positive and ground (in single rail operation). Refer to Fig 2 and Fig 3. Signal excursions beyond the power rails will be clamped through low impedance paths to the power rails. Care should be exercised to reduce the peak currents to below the limits identified in the absolute maximum ratings for latch-up immunity.

On-Resistance This is the core specification and is the starting point for selection purposes. On resistance determines the signal transmission loss between input and output when the switch is closed and feeding a particular load resistance. On resistance is measured with a current flowing from source to drain, and with the channel biased at mid supply voltage. Figures are given for 25°C and the full temperature range. Resistance increases with temperature.

ΔRON This is a measure of the on-resistance matching between channels in a given IC. The matching is measured at a number of channel bias voltages for a fixed channel current and power supply.

On-Resistance Flatness This is a measure of how the on-resistance varies across the analogue signal range. The parallel combination of P-and N-channel devices does not produce a perfectly flat resistance characteristic. The flatness measure allows designers to estimate the effects of signal dependent transmission loss on the system performance (dB loss and distortion) for a given load impedance. Fig 7 shows a typical on-resistance characteristic across the analogue signal and temperature ranges. Fig 6: Example On-Resistance Specifications (AS1741-3)

Fig 7: On-Resistance Flatness (AS1741-3)


Leakage Currents Temperature dependent leakage currents are to be found at the drain and source terminals by virtue of pn junction effects, and are specified with a switch in the ON and OFF conditions with various static voltages on the transmission path. To help identify the leakage current paths, an equivalent circuit of two adjacent switches surrounded by capacitances and leakage current sources, is shown in Fig 8. Fig 8: Equivalent Circuit of Two Adjacent CMOS Switches

Leakage currents cannot be made equal because of geometry differences between P-channel (+ILKG) and N-channel (-ILKG). As a result, there is a net leakage of either polarity at the drain and source terminals. Specifications usually specify typical and limits over temperature. Fig 9 shows a typical leakage characteristic. When the switch is OFF, separate leakage currents are specified for the source and drain terminals. When the switch is ON, leakage currents are measured at the drain terminal. Fig 9: Example Leakage Specification (AS1741-3)

NB: COM = drain or output terminal. NO or NC are normally open or closed inputs. Leakage and on-resistance effects allow the designer to estimate offsets and transmission losses for ON and OFF switch conditions. Referring to Fig 10 for the DC ON switch model:


Transmission Loss due to RON, Source and load resistances is:

⎟⎟⎠

⎞⎜⎜⎝

⎛++

=SOURCEONSOURCE

LOADSOURCEONOUT RRR

RVV _1

Fig 10: ON-Switch DC Performance

ON switch output offset due to leakage current into the load resistance is:

( )⎟⎟⎠

⎞⎜⎜⎝

⎛++

+=

LOADONSOURCE

SOURCEONLOADLKGONOUT RRR

RRRIV _2

Total On switch DC is therefore: VOUT = VOUT1 + VOUT2. The simple conclusion from this is that for a given source and on resistance, minimum transmission loss is ensured by connecting a high value impedance at the output. This also reduces the effect of on resistance variation with signal swing. In other words, transmission distortion is reduced. Referring to Fig 11 for the DC OFF switch model:

LOADLKGOUT RIV ×= Fig 11: OFF-Switch DC Performance

+ILKG = ICOM(OFF)RSOURCE

VSOURCE

D

RLOAD

+VSUPPLY

OFF-SWITCH


AC Measurements

Switching Times How fast the switch reacts to a fast rising logic signal is given by TON, turn on time, and TOFF, turn off time. Both these time specifications also include the propagation delay of the logic command through the logic driver circuits. Referring to Fig12, the fast logic signal propagates through the internal circuitry before activating the transmission path. A mid voltage is applied to the transmission path, and it is the rise and fall time of this voltage that is measured at the output pin(s) loaded with a 50Ω||35pF combination. Fig 12: Simple Model for Charge Injection and Switching Time

Referring to Fig 12 and Fig 13, overall switching time is given by:

( )DRAINLOADLOADPROPON CCRTT ++= 303.2 for 90% settling to final value ( )DRAINLOADLOADPROPOFF CCRTT ++= 303.2 for 90% settling to final value

Fig 13: Actual Data Sheet Switching Time Measurements


Fig 14: Example Switching Time Specifications (AS1741-3)

An additional specification is also identified in Fig 14. This is “break-before-make”, and specifies the difference between on and off times in switches wired as changeover units (AS1743). This timing difference ensures that no two switches are on together. Fig 15: Break-Before-Make Timing Measurement

Charge Injection Charge injection is a consequence of the action of the logic control signal acting upon the switch cell. Capacitances between gate and drain, and gate and source couple the enable rising and falling edges into the signal path at source and drain. The simplified model in Fig 13 models the injection path as CCHARGE. The result of charge injection is a change of output voltage. This in turn is dependent upon the size of the internal capacitances, and the load capacitance used to store the charge effects long enough for accurate measurements. Charge injection relationship is:

LOADOUTJ CVQ ×Δ= Charge injection varies with voltage applied to the transmission channel between the power supply limits. This is because the capacitances associated with the switch are formed by pn junctions and capacitance varies as the reverse voltage varies on the transmission path. In real life, charge injection signals show fast rise and fall times and amplifiers have to be specified to cope with these wide bandwidth signals.

Settling Time After a switch closure, when will a measurement be accurate? This is the question behind settling time. Settling time is a function of the switch on-resistance, source resistance, and effective load capacitance and resistance. A single pole response is a good approximation, and the values of capacitance and resistance found in the data sheet, and required by the application are used to calculate the settling time.


Referring to Fig 12, settling time (off to on) is given by:

( ) ( ) ⎟⎠⎞

⎜⎝⎛−+⎟⎟

⎠

⎞⎜⎜⎝

⎛++

++=− 100

%ln ErrorCCRRRRRR

TT DRAINLOADLOADSOURCEON

LOADSOURCEONONONSETOFF

Settling time (on to off) is given by:

( ) ⎟⎠⎞

⎜⎝⎛−++=− 100

%ln ErrorCCRTT DRAINLOADLOADOFFoffSETon

% Error is determined by the overall application and may be driven in part by system ADC accuracy (ie 10b, 12b, 16b).

Bandwidth Once the switching action is complete, steady state signal bandwidth is an important specification. Switch parasitic capacitances, on-resistance, source-resistance, load-resistance and load capacitance all affect the overall bandwidth. Fig 16 identifies the individual components. Fig 16: ON State and OFF State Bandwidth Model

The ON state bandwidth consists of a DC “gain”, followed by a main -3dB pole, and small “zero” caused by the interaction of RON and CDS.

( )

ONSOURCELOAD

ONSOURCELOADONDC RRR

RRRA

+++

=_

( )( )DLOADDCONdB CCA

F+

=− π21

_3 ( )DSONONZERO CR

Fπ2

1_ =

The OFF state isolation bandwidth falls away at 20dB/decade, followed by a “zero” after which the attenuation flattens off somewhat, before the attenuation continues to increase as CLOAD and CDRAIN begin to contribute.

( )DSSOURCEOFFZERO CR

Fπ2

1_ = ( )( )LOADDRAINLOAD

OFFPOLE CCRF

+=

π21

_


In reality, the switch on-resistance and drain capacitance are distributed components, not single “lumped” components as shown in the simplified models. This is implied by reference to Fig 4, where the on-resistance is proportional to the dimension W. For more detailed bandwidth estimation, a ladder model of the on-resistance and capacitance will be a better approach. Fig 17: Ladder Representation of On-Resistance

Summary Knowledge of the DC and AC characteristics of analogue switches is necessary to ensure successful practical implementation. DC and AC models have been described to help identify the background reasons for the data sheet specifications.

cmos analogue switches structure and specifications

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