Int. J. Electron. Commun. (AE) 66 (2012) 1032 1037

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International Journal of Electronics andCommunications (AE)

journa l h o me pa ge: www.elsev ier .co

CMOS-based active RC sinusoidal oscillator with and sin law

Abhirup a 36-B, J and K b Department o ech Re

a r t i c l

Article history:Received 26 JaAccepted 21 M

Keywords:Analog circuitActive RC sinuSingle-resistan

OS rhe osnditiod wh

on tBBs, fers aransial prly vo

1. Introduction

Sinusoidal oscillators are very important analog circuits and ndnumerous applications in communication, control systems, signalprocessing,and referenindependenthe frequendent FO tunto devise thSRCOs. Therizations of Srecent publite ABBs, eaor its compand currentamplier anfor the SRCavailability

Many ofmethod of

CorresponE-mail add

(N. Herencsar)URLs: http

http://www.u

a decade ago and researched well by several authors [16,17]. Thus,several of the recent works in SRCO design, instead of creating anovel oscillators/topologies with improved features for integrationin mainstream CMOS, rather create a novel ABB and employ the

1434-8411/$ http://dx.doi.o instrumentation, and measurement systems (see [1]ces cited therein). Active RC sinusoidal oscillators witht tuning laws for the condition of oscillation (CO) andcy of oscillation (FO) are very desirable for indepen-ing and consequently a lot of research has been donee so called single-resistance-controlled oscillators ore have been numerous publications dealing with real-RCOs using variety of active building blocks (ABBs). Theications in the eld [215] use wide variety of compos-ch of which is of some type of current conveyor (CC)osite (basically employing unity gain voltage followers

followers) and/or cascade of CC and transconductanced every work aims to provide a novel implementationO with improved features like reduced ABB count,of quadrature outputs, etc.

the recent works are based on integrator-in-loopdesigning SRCOs, which has been proposed more than

ding author.resses: lahiriabhirup@yahoo.com (A. Lahiri), herencsn@feec.vutbr.cz.://www.publicationslist.org/lahiriabhirup (A. Lahiri),tko.feec.vutbr.cz/herencsar/ (N. Herencsar).

already known SRC design equations (or state variable method,e.g. [16,17]) to devise the oscillator. Some of the recent works alsoprovide new oscillator topologies to realize different CO and FOtuning laws [18,19] (including SRC); but there is hardly any expla-nation on to the use of these novel oscillator topologies over thealready established topologies. The authors believe that althoughthe focus of the researchers working in this eld since the last sev-eral years has been to realize minimum ABB circuit solutions and todemonstrate the concept and/or devise novel topologies, it is alsoimportant to use the already established circuit theory in realizingreduced transistor count circuit solutions consuming much lesserpower (as compared to ABB based design approach) and thus makethe proposed circuit solutions in this eld more attractive for main-stream CMOS integration [20]. The authors, of course, do not ruleout the advantage(s) of ABB based design approach in creating newcircuit solutions and devising additional useful approaches to cre-ate the circuit solutions, but believe that having realized a compactABB based circuit solution, the focus should be on compact CMOSrealization of the solution for monolithic integration.

A comparison with recently reported ABB based SRCOs withthe proposed CMOS SRCO is provided in Table 1. This list doesnot include the active-C oscillators that use operational transcon-ductance ampliers (OTAs) (e.g. circuits in Fig. 2 of [21,22]) toactively simulate resistors and are based on the same/similar

see front matter 2012 Elsevier GmbH. All rights reserved.rg/10.1016/j.aeue.2012.05.008gle-resistance-controlled (SRC) tuning

Lahiri a, Norbert Herencsarb,

Pocket, Dilshad Garden, Delhi, Indiaf Telecommunications, Brno University of Technology, Purkynova 118, 612 00 Brno, Cz

e i n f o

nuary 2012ay 2012

ssoidal oscillatorce-controlled (SRC)

a b s t r a c t

This paper proposes a very compact CMing four quadrature voltage outputs. Tin loop. The governing laws for the cosingle-resistance-controlled (SRC) anSRC-based sinusoidal oscillators basedat reducing the number of employed Ator count circuit and consequently ofSRC oscillators in terms of number of texample, a 160.2 kHz oscillator (typicin 65 nm CMOS technology with suppm/locate /aeue

four-phase quadrature outputss

public

ealization of active RC sinusoidal oscillator capable of generat-cillator is based on the cascade of lossless and lossy integratorsn of oscillation (CO) and the frequency of oscillation (FO) are

ich allow independent FO tuning. Unlike previously reportedhe active building block (ABB) based approach and which aimthis direct CMOS realization provides a much reduced transis-

low power solution. A comparison with previously reportedstors and current consumption has been provided. As a designocess, T = 27 C) with 82 W power consumption is designedltage of 0.5 V.

2012 Elsevier GmbH. All rights reserved.

A. Lahiri, N. Herencsar / Int. J. Electron. Commun. (AE) 66 (2012) 1032 1037 1033

Table 1Comparative study with previously reported SRCOs.

Ref. ABB typea No. ofABBs

No. oftransistors

Frequency ofoperation (kHz)

Tuning range [maxfreq min freq]

Amplitude ofoscillation mV or

THD (%) Powerconsumption (mW)

[2] [3][4] [5] [6] [7] 300[8] 1 [9][10] [11] 210 [12] 10.6 [13] 11.5[14] 3.6 [15] 46.6Proposed 104.

: not mentiona Refer Appeb Each CDBAc AD844 IC vd Different ae Topology 1f Uses zero

principle ofIt is clearlypaper enjoycompared ton ABB bas[3] can be aferential amin [15] duetor designscount and rsidering thbandwidth also true inthe transistoperating fthe numbertakes cognireported CMquencies is not providecreating SRtor in loop, power consthe underlylies in bringused previoSRCO.

2. Propose

The protransistors body effectintegrator, a pseudo lsource degwhere M1linearity Vout loss ofconvertors of [24]). C

nce ators ro6||2

the g int

creat chartors

igherd wittive rck domper

posgn.itionals Vegrat owat n(kHz)

CCII 2 D 30 9FDCCII 1 60 1725 FDCCII 1 60 2240 CFOA 2 D 15.92 64 9CFOA 2 D CDBAb 2 D 974.4 974.4 CDBAb 2 D 15.92 47 1ICCIIe 2 18 VF/CFf 76 950 VF/CFf 38 930 1600 DBTA 1 D 15.61 46.3 DBTA 1 D 15.88 36.2 GCFTA/UGVF 2 24 15.92 24.2 PCA 3 96 138 296.4 22/26 160.2 175.1 ed; D: discrete ICs used.ndix A for nomenclature of the ABBs.

created using two AD844 CFOA ICs, see Fig. 1 [7].oltage supply used was 12 V.mplitudes of quadrature outputs., circuit 3.

systematic offset voltage follower of Palumbo and Pennisi [25].

provide SRC tuning laws as already pointed in [16,17]. evident from Table 1 that the proposed circuit in thiss low transistor count and low power consumption aso many recently reported sinusoidal oscillators baseded design approach. The large power consumption inccounted for large tail biasing current used for the dif-pliers to provide large bandwidth to the ABB and

to more number of ABBs. Thus, ABB based oscilla- should focus optimally on both the reduction of ABBeduction/optimization of ABB power consumption con-e FO and tuning range of interest to achieve optimaland port characteristics of ABB. Power optimization is

CMOS oscillator design wherein the biasing current ofors needs to be chosen appropriately for the desiredrequency range and effort should be made to reduce

of current branches between the supplies. Our designtion of this point. It should also be noted that recentlyOS quadrature RC oscillator [23] suitable for RF fre-

based on the two-integrator in loop method, but it does SRC tuning. Based on the already known technique of

resistatransis2ro5||2acrosslookinwhiching theTransisvide hbe useif negafeedbaage, teremainin desi

Addterminthe intcurrennote thCOs, which is the cascade of lossless and lossy integra-this paper proposes a reduced transistor count and lowumption CMOS SRCO. The authors believe that althoughing principle is already known [16,17], but the noveltying the already known circuit theory (which has beenusly to create ABB based SRCO) to create this CMOS

d circuit

posed CMOS SRCO circuit is shown in Fig. 1. Allhave source and body tied together to eliminate

on threshold voltage. Transistors M1M8 form anwhich in the operating frequency range simulatesossless integrator: VI conversion is performed byenerated differential amplier comprising of M1M4,M2 and M3M4 are matched transistors and for highI conversion it is required that gm1,gm2 1/R1. With-

generality, several other high linearity CMOS VIcould be employed, e.g. cross-quad (see Chapter 13ross coupled transistors M6M7 simulate negative

to effectiveonly makesmuch largebe the caseimum lengwidths so thincreasinglthis would external caphave very lited to 2rMfundamenttively simurange. Simitheir currenof resistor Rand M13Msame transcrequiremen

In prediquency of A

V-262 1.4 118.09I-70 V-8399c 2.47 V-5400

1034 A. Lahiri, N. Herencsar / Int. J. Electron. Commun. (AE) 66 (2012) 1032 1037

11

9

VDD

IO

M6 M7 M8

MX2

M5

MX1 MX4

M1

MX3

M22

M21

r with

(assumptio1, negative and M17Mtiplied Cgd, and R2 = R3.be given as:

CO : R4

FO : f0 =

It is evidFO can be cSRCO.

The curr

(i) The cho 1/R1primarcontrolis derivof tranresistotransisbiased tance foIDM9 =

(ii) Increaswould of MX1rents oIDMX4 =

(iii) Also, torequire

atio o

stors

10, M12

8, M177, M1812, M

4

21

X4

ign strategy and simulation results

circuit in Fig. 1 is designed in 65 nm CMOS technology0.5 V supply and with typical NMOS VTH = 450 mV and PMOS00 mV. The aspect ratios of the transistors in Fig. 1 arein Table 2. All the transistors are biased well into satura-cept the main transistors of the diff-pairs M1M2, M13M14,9M10 which are biased in sub-threshold region to provideansconductance. Moreover, biasing these transistors in sub-old make their VGS much less than VTH (by about 100 mV)hich helps keep the tail currents of the diff-pair well intoion.M3 M4 M

M1 M2 M

VSS

R1

C1

V1A V1B V1A

V2B V2A V1B

Fig. 1. CMOS four-phase quadrature oscillato

ns should be made true through design), that gm1ro1 resistancepositive resistance cancellation in M5M820 is perfect, all parasitic capacitances (Cgs, miller mul-etc.) are lumped into external capacitance C1 and C2

With these assumptions the simplied CO and FO can

1gm9

+ R2, (1)

12

1

C1C2(R1 + 1/gm1)(R2 + 1/gm9)

12

1

C1C2R1R2.

(2)

ent from (1) and (2) that CO can be controlled by R4 andontrolled by R1 and thus the proposed oscillator is an

ent consumption of the oscillator depends on:

Table 2Aspect r

Transi

M9, MM1, MM5, MM6, MM11, MM3, MM20, MMX1M

3. Des

Thewith VTH = 4given tion exand Mlarge trthreshand wsaturatice of biasing current to provide transconductance gm1and gm9 1/R2. This condition is required so that FO

ily depends on the resistance value and hence be wellled with temperature variations unless the current biased from a constant-gm circuit such that the inverse

sconductance is servo to scaled value of a low-tempcor in the current generation circuit. Considering the maintors of the diff-pairs M1M2, M13M14, and M9M10 arein sub-threshold region to provide large transconduc-r a given bias current, we get IDM1 = IDM2 nVT/R1 and

IDM10 = IDM13 = IDM14 nVT/R2.e in tail current to increase the transconductance gm1also require a proportional increase in the bias currentsMX2. Similar increase is also required for the bias cur-f MX3MX4. This design chooses IDMX1 = IDMX2 = IDMX3 =

0.8IDM3. ensure the same DC bias point at V1A, V1B, V2A, V2B it isd that IDM11 = IDM12 = IDM13 = IDM14 = 0.5IDM3 = 0.5IDM4.

Current ers M3Mlength (5 current mirtors, whichwidths alsovoltages arin saturatiocurrent mirtransistors for tail curr

The chocuit functiosize as in cuear metal23 [fF/monly by misnant role if controlled. M12M15 M16

M10M13 M14

R3

R4

R2

C2

M18 M19 M207

V1BV2A V2B

V1A

IO

SRC tuning law.

f the transistors.

W/L (m/m)

3, M14 10 10/0.310 20/0.3

, M20 6/1, M19 6.4/115, M16 3 10/5

3 20/55/55 16/5mirror transistors at the tail of the differential ampli-4, M11M12, M15M16 are designed with maximumm) to provide high output resistance, provide betterroring and reduce random mismatch between transis-

reduces with increased area. With increased length, the have to be correspondingly increased so that over-drivee not increased too much and maintain all transistorsn. Note the choice of maximum length transistors forrors is just an example and reduced length and width(e.g. both scaled down by factor of 2) can also be usedent biasing.ice of passive components is important from both cir-nality and area. It is desirable to keep reduced capacitorrrent CMOS technologies capacitance/unit area for lin-insulatormetal (MIM) capacitors is not very large (2]). However, the minimum capacitor size is limited notmatch, but also transistor parasitic start to play domi-the external capacitor is small and hence, FO is not wellNot keeping very small valued capacitors, i.e. using large

A. Lahiri, N. Herencsar / Int. J. Electron. Commun. (AE) 66 (2012) 1032 1037 1035

se qua

Table 3Component va

R1, R2, R3R4C1, C2IoTotal curren

valued capaintegrator (range as theleading to b

For the (2.5 fF/m2

were chose(Table 3). Thconsumes 8cuit is 82 Wsinusoidal othat R4 valdesign, gm9needs to beand temperdesigns whbias circuitof the diffetance valueshown hereand T = 27 Cvalue of R4respondingbe useful inrequired, buto generateautomatic gthe oscillatiing a peak the differen

The osciputs with Fare shown than 2.5% anFig. 2. Oscillation waveforms for the four-pha

lues for FO = 160.2 kHz.

50 k58 k20 pF1 A

t consumption 82 A

citors, is also benecial for simulating pseudo-losslesswith xed biasing current) in the operating frequency

pole frequency (1/ro||C) is pushed to lower frequencies,etter realization of lossless integrator.passives p+poly-silicon resistors and MIM capacitors) are employed. The values of the passive elements 110

120

130

140

150

160

170

180

190

200

FO

(kH

z)n as: R1 = R2 = R3 = 50 k, R4 = 58 k, and C1 = C2 = 20 pFe bias current is equal to Io = 1 A and the entire circuit2 A of current. Thus, the power consumption of the cir-

and which is much lower than many recently reportedscillators based on ABB-based approach [215]. Note

ue has been chosen to satisfy CO and in the present 250 A/V. In industrial designs sufcient margin

given for oscillator start-up across different processature corners. Since gm varies with temperature, forere R2 is not much larger than 1/gm9, a constant-gm

may to be employed [20] for biasing the tail currentrential amplier, to servo the inverse of transconduc-

to a low temp-co resistor. The biasing circuit is not and simulations are performed only at typical process

for demonstration of concept. Also, note that increasedprovides higher oscillation amplitude, but with cor-

ly higher distortion. High amplitude oscillations may some applications, where low THD sinusoids are nott rather increased amplitude sine like waves are used

square wave using a comparator. In the present design,ain control (AGC) loop has not been employed to controlon amplitude, but it can be done routinely by employ-amplitude detector and controlling the bias current oftial amplier in negative feedback.llation waveforms for the four-phase quadrature out-O = 160.2 kHz, where the phase error is less than 1.5

in Fig. 2. The harmonic distortion at each output is lessd which can be high in some applications. As described

20 100

before, an atude and imof FO by simand the FOdesign, valuR1 as a serieMOSFET. Dior binary w

Anotherthe presentoscillators capacitor amuch as cal FO can vfrequency gappropriatefrequency lRC oscillato(derived frowork is notdrature oscillator.40 60 80 10 0 120 140 160 18 0 20 0

Resistor R1 (kOhms)

Fig. 3. SRC tuning of FO via R1.

uxiliary AGC circuit is required to regulate the ampli-prove THD performance. To further demonstrate tuningply changing R1 value, R1 is varied from 30 k to 200 k

varies from 198.5 kHz to 104.4 kHz, see Fig. 3. In ICe of R1 can be changed in analog fashion by makings combination of xed linear resistor and triode biasedgital tuning can be achieved by switching unit resistorseighted resistor bank by an external digital code.

aspect which needs to be addressed is the usability of oscillator as a single frequency generator. On-chip RCsuffer from process variations of both the resistor andnd thus the oscillation frequency tends to vary by as30% (example, an oscillator designed for 30 MHz typi-ary from 20 MHz to 40 MHz). Therefore, on-chip singleenerators should have mechanisms to be tuned to the

frequency. Most of the on-chip RC oscillators employ aocked loop (FLL) for process compensation wherein ther frequency is locked to an external frequency referencem crystal oscillator) or it is multiple. The aim of this

the design of an FLL for process compensation, which

1036 A. Lahiri, N. Herencsar / Int. J. Electron. Commun. (AE) 66 (2012) 1032 1037

is a standard technique of frequency locking, but rather to demon-strate the usability of the proposed oscillator to also be embeddedin an FLL. As demonstrated, the FO of the proposed oscillator canbe varied independently using resistor R1 and thus if embedded ina negative ferror betwefrequency tin analog faear resistorcode by swto create thloop alwayserence freqchanges) caalso meansfeedback elcannot provitoring of thFLL is a bettwave to be cthe input ctor, which woscillator frreference clideal countunit resistooscillator frthe resolutinegative fecan be remopower-dowout as the oin the FO. Floops can halator frequewithin the lnot availabto set the Fto servo onpassive com

4. Conclud

A compacapable of proposed. Bgrators in loand attempapproachesof practical advances inand/or new

Acknowled

This worunder no. PTechnologyanonymousthat helped

Appendix A

This sectABBs.

CCII: second-generation current conveyorFDCCII: fully-differential second-generation current conveyorCDBA: current-differencing buffered amplierICCII: inverting second-generation current conveyor

ity gity g: diff: ge

: unirogr

nces

gsriratrolleJ Electar A

circu7:21.

rng JWdratuEAS Tng CMce cont 2002gsriraillator9;63:elmars. Aniri A. Nerencgsrira. Frequer A,s usin2;10(ani Rers anta SS

educe12.encsaployinress 2encsalter0;97(encsatrollescond0;97(encsadratuani R,As: s6.elmalet. Aniri A. -inter1;20(iri A. eratiotrolle394: iri A. using1;20(ani R.0;26(ner R,ple osE Elec

veira L 3.1

TH. Tbridg

umbodings CS). 2eedback loop the value of the R1 can be adjusted so thaten the generated output frequency and the referenceends to zero. As already pointed out, R1 can be changedshion by making R1 as a series combination of xed lin-

and triode biased MOSFET and also through a digitalitching unit resistors in series or parallel combinatione effective R1. In the analog FLL, the negative feedback

needs to be there, necessitating a dedicated input ref-uency, but slow environment changes (e.g. temperaturen be tracked and compensated for by the feedback. This

that the analog FLL will always consume power in theements that are always ON. In cases where in the useride a dedicated clock source for continuous time mon-e FO but only for one time process trimming, a digitaler solution. Digital FLL would rst of all require the sinereated into square wave for frequency comparison withlock. Digital FLL would use a digital frequency detec-ould count the number of cycles of the generated RC

equency in a reference time period created by the inputock. Depending on the count and comparing it with the, an error count can be generated and through whichrs in the R1 resistor ladder can be switched. Once the RCequency is within the desired error bound decided byon of the resistor ladder digital-to-analog converter, theedback loop is disabled, the input reference frequencyved and the complete digital frequency detector can ben. Further environment changes can never be trackedscillator now is free running and can only lead to errorsurther to be noted is that both the digital and analogve smaller input reference frequency than the RC oscil-ncy and the desired scaling factor can be incorporatedoop gain. In cases where external frequency reference isle, off-chip precision passive components are requiredO. Servo biasing feedback loops can also be employed-chip component values to scaled value of the off-chipponents.

ing remarks

ct CMOS realization of active RC sinusoidal oscillatorgenerating four quadrature voltage outputs has beenased on the concept of cascade of lossless and lossy inte-op, the oscillator circuit provides SRC type tuning lawsts to reduce the transistor count as opposed to previous

of reducing ABB count. It is expected that the circuit isuse to researchers and engineers in the eld and further

creating CMOS RC oscillators with improved features techniques are reported in the near future.

gements

k was supported by Czech Science Foundation projects102/11/P489, no. P102/09/1681, and Brno University of

Fund no. FEKT-S-11-15. Authors also wish to thank the reviewers for their useful and constructive comments

to improve the paper.

.

ion provides full nomenclature of the aforementioned

VF: unCF: unDBTAGCFTAUGVFPCA: p

Refere

[1] TanconInt

[2] Kumtor200

[3] HoquaWS

[4] ChatanLet

[5] Tanosc200

[6] Abulato

[7] Lahdiff

[8] Tantor

[9] Tokgie200

[10] Senlow

[11] Gupa r507

[12] HeremExp

[13] Hersal 201

[14] Hercontran201

[15] Herqua

[16] SenCFO104

[17] Abuout

[18] Lahnon201

[19] Lahgencon274

[20] Lahter 201

[21] Sen199

[22] SotsimIEIC

[23] Olifrom

[24] LeeCam

[25] Palcee(ICEain voltage followerain current followererential-input buffered and transconductance amplierneralized current follower transconductance amplierty-gain voltage-followerammable current amplier

t W, Prasertsom D, Piyatat T, Surakampontorn W. Single-resistance-d quadrature oscillator using current differencing buffered ampliers.ron 2008;95(11):111926., Vyas A. A single resistance controlled eight possible oscilla-its for analog signal processing applications. Acad Open Internet J

, Hou CL, Chang CM, Cheng ST, Su HY. Current or/and voltage-modere oscillators with grounded capacitors and resistors using FDCCIIs.rans Circ Syst 2008;3(7):12938., Al-Hashimi BM, Chen HP, Tu SH, Wan JA. Current-mode single resis-trolled oscillators using only grounded passive components. Electron;38(19):10712.t W, Surakampontorn W. Single-resistance-controlled quadrature

and universal biquad lter using CFOAs. AEU: Int J Electron Commun10806.ati MT. Identication of a class of two CFOA-based sinusoidal RC oscil-alog Integr Circ Signal Process 2010;65:41928.ew realizations of voltage-mode quadrature oscillators using current

ing buffered ampliers. J Circ Syst Comput 2010;19(5):106976.t W, Pisitchalermpong S. CDBA-based quadrature sinusoidal oscilla-enz 2007;61(3-4):1024.

Kuntman H, Cicekoglu O, Discigil M. New oscillator topolo-g inverting second-generation current conveyors. Turk J Elec Eng1):11929., Gupta SS. Novel sinusoidal oscillators using unity-gain voltage fol-d current followers. IEICE Electron Express 2004;1(13):4049., Senani R. New single resistance controlled oscillators employingd number of unity-gain cells. IEICE Electron Express 2004;1(16):

r N, Koton J, Vrba K, Lahiri A. New voltage-mode quadrature oscillatorg single DBTA and only grounded passive elements. IEICE Electron009;6(24):170814.r N, Koton J, Vrba K, Lattenberg I. New voltage-mode univer-

and sinusoidal oscillator using only single DBTA. Int J Electron4):36579.r N, Vrba K, Koton J, Lahiri A. Realisations of single-resistance-d quadrature oscillators using generalised current followeructance amplier and unity-gain voltage-follower. Int J Electron

8):897906.r N, Lahiri A, Vrba K, Koton J. An electronically tunable current-modere oscillator using PCAs. Int J Electron 2012;99(5):60921.

Gupta SS. Synthesis of single-resistance controlled oscillators usingimple state-variable approach. IEE Proc Circ Dev Syst 1997;144:

atti MT. New two CFOA-based sinusoidal RC oscillators with bufferedalog Integr Circ Signal Process 2011;66:47582.

Deriving (MO)(I)CCCII based second-order sinusoidal oscillators withactive tuning laws using state variable method. Radioengineering1):34953.New canonic active RC sinusoidal oscillator circuits using second-n current conveyors with application as a wide-frequency digitallyd sinusoid generator. Active Passive Electron Comp 2011. Article ID1-8.New CMOS-based resistor-less current-mode rst-order all-pass l-

only ten transistors and one external capacitor. Radioengineering3):63844.

Systematic generation of OTA-C sinusoidal oscillators. Electron Lett18):14578.

Jerabek J, Petrzela J, Dostal T, Vrba K. Electronically tunable oscillatorcillator based on single-output and multiple-output transconductor.tron Express 2009;6(20):147682.B. An inductorless CMOS quadrature oscillator continuously tuneableto 10.6 GHz. Int J Circ Theory Appl 2012;40(3):20919.he design of CMOS radio-frequency integrated circuits. Cambridge:e University Press; 1998.

G, Pennisi S. A high performance CMOS voltage follower. In: Pro-of IEEE international conference on electronics, circuits and systems008. p. 214.

A. Lahiri, N. Herencsar / Int. J. Electron. Commun. (AE) 66 (2012) 1032 1037 1037

Abhirup Lahiri received Bachelor of Engineering (B.E.)degree with the highest honors from the Division ofElectronics and Communications, Netaji Subhas Instituteof Technology (erstwhile, Delhi Institute of Technol-ogy), University of Delhi, India. His past researchworks include design of compact analog circuit solu-tions using novel voltage-mode and current-modeactive elements. His current research interests includelow-power and low-voltage analog circuit design andprecision voltage and current reference generation. Hehas authored/co-authored more than thirty internationaljournal/conference papers (including fteen SCI/SCI-Epublications) and has acted as a reviewer (by editors invi-

tation) for numerous international journals and conferences of repute. He servedas a program committee member for the International Conference on Telecom-munications and Signal Processing (TSP). He is an editorial board member ofRadioengineering Journal for the years 20112012. His biography is included inMarquis Whos Who in the World 2011 (28th Edition).

Norbert Herencsar received the M.Sc. and Ph.D. degreesin Electronics & Communication and Teleinformatics fromBrno University of Technology, Czech Republic, in 2006and 2010, respectively. Currently, he is an AssistantProfessor at the Department of Telecommunications, Fac-ulty of Electrical Engineering and Communication, BrnoUniversity of Technology, Brno, Czech Republic. FromSeptember 2009 through February 2010 he was an Eras-mus Exchange Student with the Department of Electricaland Electronic Engineering, Bogazici University, Istan-bul, Turkey. His research interests include analog lters,current-mode circuits, tunable frequency lter designmethods, and oscillators. He is an author or co-author of

20 research articles published in SCI-E international journals, 20 articles published

in other journals, and 52 papers published in proceedings of international confer-ences. His paper Generalized design method for voltage-controlled current-modemultifunction lters, presented and published at the 16th TelecommunicationsForum TELFOR 2008, Belgrade, Serbia, was recommended for Blazo MircevskiAward granted for the best paper of a young TELFOR author. In 2011, he receivedRector Award in the University competition Top 10 Excelence VUT 2010 for the9th most productive scientist at the Brno University of Technology, category Pub-lications. His paper Novel resistorless dual-output VM all-pass lter employingVDIBA, presented and published at the 7th International Conference on ElectricalElectronics Engineering - ELECO 2011, Bursa, Turkey, received The best paper awardin memory of Prof. Dr. Mustafa Bayram.

Since 2008, Dr. Herencsar serves in the organizing and technical committee ofthe International Conference on Telecommunications and Signal Processing (TSP).In 2011, he is guest co-editor of TSP 2010 Special Issue on Telecommunications,published in the Telecommunication Systems journal of Springer. In 20112013, heis guest co-editor of TSP 2010, TSP 2011, and TSP 2012 Special Issues on Signal Pro-cessing, published in the Radioengineering journal. Dr. Herencsar is Senior Memberof the IACSIT and Member of the IEEE, IAENG, and ACEEE. He is also CommitteeMember of the IACSIT Electronics and Electrical Society (EES).

CMOS-based active RC sinusoidal oscillator with four-phase quadrature outputs and single-resistance-controlled (SRC) tunin...1 Introduction2 Proposed circuit3 Design strategy and simulation results4 Concluding remarksAcknowledgementsReferencesReferences