CMOS FabricationCMOS transistors are fabricated on silicon waferWafer diameter (200-300 mm)On each step, different materials are deposited, or patterned or etched A layer must be patterned before the next layer of material is applied on the chip (lithography)Easier to understand by viewing both top and cross-section of wafer in a simplified manufacturing process

CMOS Process at a GlanceOne full photolithography sequence per layer (mask)Built (roughly) from the bottom up5 metal 24 metal 12 polysilicon3 source and drain diffusions1 tubs (aka wells, active areas)

Inverter Cross-sectionTypically use p-type substrate for nMOS transistorsRequires to make an n-well for body of pMOS transistors

Well and Substrate TapsSubstrate must be tied to GND and n-well to VDDUse heavily doped well and substrate contacts/taps (or ties)

Inverter Mask SetTop viewTransistors and wires are defined by masksCross-section taken along dashed line

Detailed Mask ViewsSix masksn-wellPolysiliconn+ diffusionp+ diffusionContactMetalInIn reality >40 masks may be needed

Creating Wafers - Czochralski MethodStart with crucible of molten silicon (1425oC)Insert crystal seed in meltSlowly rotate / raise seed to form single crystal ingotAfter cooling, slice ingot into wafers & polish

Fabrication StepsStart with blank wafer (typically p-type where NMOS is created)Build inverter from the bottom upFirst step will be to form the n-well (where PMOS would reside)Cover wafer with protective layer of SiO2 (oxide)Remove oxide layer where n-well should be builtImplant or diffuse n- dopants into exposed wafer to form n-wellStrip off SiO2

OxidationGrow SiO2 on top of Si wafer900 1200 0 C with H2O or O2 in oxidation furnace

PhotoresistSpin on photoresistPhotoresist is a light-sensitive organic polymerProperty changes where exposed to light

Two types of photoresists (positive or negative)Positive resists can be removed if exposed to UV lightNegative resists cannot be removed if exposed to UV light

LithographyExpose photoresist to Ultra-violate (UV) light through the n-well maskStrip off exposed photoresist with chemicals

EtchEtch oxide with hydrofluoric acid (HF)Only attacks oxide where resist has been exposedN-well pattern is transferred from the mask to silicon-dioxide surface; creates an opening to the silicon surface

Strip PhotoresistStrip off remaining photoresistUse mixture of acids called piranah etchNecessary so resist doesnt melt in next step

n-welln-well is formed with diffusion or ion implantationDiffusionPlace wafer in furnace with arsenic-rich gasHeat until As atoms diffuse into exposed SiIon ImplanatationBlast wafer with beam of As ionsIons blocked by SiO2, only enter exposed SiSiO2 shields (or masks) areas which remain p-type

Strip OxideStrip off the remaining oxide using HFBack to bare wafer with n-wellSubsequent steps involve similar series of steps

Polysilicon (self-aligned gate technology)Deposit very thin layer of gate oxide< 20 (6-7 atomic layers)Chemical Vapor Deposition (CVD) of silicon layerPlace wafer in furnace with Silane gas (SiH4)Forms many small crystals called polysiliconHeavily doped to be good conductor

Polysilicon PatterningUse same lithography process discussed earlier to pattern polysilicon

Self-Aligned ProcessUse gate-oxide/polysilicon and masking to expose where n+ dopants should be diffused or implantedN-diffusion forms nMOS source, drain, and n-well contact

N-diffusion/implantationPattern oxide and form n+ regionsSelf-aligned process where gate blocks n-dopantsPolysilicon is better than metal for self-aligned gates because it doesnt melt during later processing

N-diffusion/implantation cont.Historically dopants were diffusedUsually high energy ion-implantation used todayBut n+ regions are still called diffusion

N-diffusion cont.Strip off oxide to complete patterning step

P-Diffusion/implantationSimilar set of steps form p+ diffusion regions for PMOS source and drain and substrate contact

ContactsNow we need to wire together the devicesCover chip with thick field oxideEtch oxide where contact cuts are needed

MetalizationSputter aluminum over whole waferCopper is used in newer technologyPattern to remove excess metal, leaving wires

Device Isolation Techniques

Isolation is required to prevent unwanted conduction paths between devices. avoid creation of inversion layers outside the channel regions of transistors reduce leakage currentsEtched Field Oxide Method( field oxide is selectively etched to expose the silicon surface for fabrication)

Thickness of field oxide leads to large oxide steps at the boundaries between active areas and field regionsPolysilicon and metal layers are deposited over such boundaries in steps.Height difference at boundary can cause cracking of deposited layersLeading to chip failure.Manufacturers prefer isolation techniques that partially recess the field oxide into the Si surface.

Local Oxidation of Si (LOCOS)

Based on the principle of selectively growing the field oxide in certain regionsInstead of selectively etching away the active areas after oxide growthA thin layer of SiO2 is grown over the active region and covered with silicon nitride

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A thin pad oxide is grown on Si Surface, followed by depostion and patterning of a silicon nitride layer to mask. introducing a channel-stop diffusion that raises the impurity concentration in the substrate in areas where transistors are not required

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The thick field oxide is then grown in the areas not covered by Silicon Nitride.The field oxide is partially recessed into the surface.Thermal oxidation process also consumes some of Si. grows in both the vertical and lateral directions

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Field oxide forms lateral extension under nitride layer, birds beak regionThis results in a active area smaller than patterned Silicon Nitride and thin pad oxide layers are etched LOCOS is more popular technique Measures are developing to take care of birds beak encroachment.

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CMOS fabrication sequenceGate oxide growthThe nitride and stress-relief oxide are removedThe devices threshold voltage is adjusted by:adding charge at the silicon/oxide interfaceThe well controlled gate oxide is grown with thickness tox

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CMOS fabrication sequencePolysilicon deposition and patterningA layer of polysilicon is deposited over the entire wafer surfaceThe polysilicon is then patterned by a lithography sequenceAll the MOSFET gates are defined in a single step

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CMOS fabrication sequenceNMOS formationPhotoresist is patterned to define the n+ regionsDonors (arsenic or phosphorous) are ion-implanted to dope the n+ source and drain regionsThe process is self-aligned

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CMOS fabrication sequence PMOS formationPhotoresist is patterned to cover all but the p+ regionsA boron ion beam creates the p+ source and drain regions

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CMOS fabrication sequence MetalizationA layer of metallization is applied to the wafer surface and selectively etched to produce the interconnects

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