cmos fet introduction

• ID - VDS Characteristics

• Physical Layout

• Circuit Models

– Large

– Small signal

CMOS FET Introduction

VGS = VDD

VGS = VT + DV1

VGS = VT + DV2

VGS = VDD

VGS = VT + DV1

VGS = VT + DV2

ID

VDS

VDS

1

http://www.pio.okstate.edu/

ID-VD Square law


VGS = VDD

VGS = VT + DV1

VGS = VT + DV2

VGS = VDD

VGS = VT + DV1

VGS = VT + DV2

ID

VDS

VDS

(1)

L

GS D

W

2


Small Signal Sq Law – gm & gds


VGS = VDD

VGS = VT + DV1

VGS = VT + DV2

VGS = VDD

VGS = VT + DV1

VGS = VT + DV2

ID

VDS

VDS

(1)

(1)

3


Physical Overview – parasitics

– Contact Rs

• Gate

• Drain & Source

– Cox

– Csurface

– Diodes

• Cdb, Csb

CMOS FET Models

L

GS D

WCox

4


ID-VD Subthreshold

CMOS FET Models

(1)

where IDO is the leakage current at VG = 0 and is

expressed as:

(1)

VGS = VT + DV1

VGS = VT + DV2

VGS = VT + DV1

VGS = VT + DV2

ID

VDS

VDS

IF and IR are called the forward current and reverse

current respectively and can be expressed as

(1)

(1) 5


ID-VD Subthreshold (Con‟t)

CMOS FET Models

VGS = VT + DV1

VGS = VT + DV2

VGS = VT + DV1

VGS = VT + DV2

ID

VDS

VDS

IF and IR are called the forward current and reverse

current respectively and can be expressed as

(1)

(1)

(1)

(1)

(1)

6


ID-VD Subthreshold Slope

CMOS FET Models

VGS = VT + DV1

VGS = VT + DV2

VGS = VT + DV1

VGS = VT + DV2

ID

VDS

VDS

(1)

(1)

(1)

The „n‟ term in equations is defined as the sub threshold slope.

(1)

7


ID-VD Subthreshold Slope „n‟

CMOS FET Models

(1)

GS D

Cox

Cs

For BULK CMOS processes, n ranges from 1.25 to 2.

8


ID-VD Subthreshold Slope „regions‟

– Weak Inversion, IC << 1

– Moderate Inversion, IC 1

– Strong Inversion, IC >> 1

– Distinction between these three regions is

done on the basis of inversion coefficient.

CMOS FET Models

(1)

9


Small Signal Subthreshold – gm & gds

– Taking the partial derivative of ID w.r.t G,S,D

CMOS FET Models

(1)

VGS = VT + DV1

VGS = VT + DV2

VGS = VT + DV1

VGS = VT + DV2

ID

VDS

VDS

(1)

(1)

10


Small Signal Subthreshold – gm & gds

– Taking the partial derivative of ID w.r.t G,S,D

– gds = ID/VA

CMOS FET Models

(1)

VGS = VT + DV1

VGS = VT + DV2

VGS = VT + DV1

VGS = VT + DV2

ID

VDS

VDS

(1)

11


Small Signal Subthreshold –gds

– gmds (Triode VDS << 4UT)

gmds = gmd – gms

“gmds is a current controlled resistor”

CMOS FET Models

(1)

12


CMOS FET Models

Subthreshold –Advantages

13


CMOS FET Models

(1)

Subthreshold –Disadvantages

14


Mismatch in CMOS Processes

Transistors – Threshold AVT dominant term

• TOX , doping

• Doping – channel profile & Gate work function

– Current term Aβ

• KPsat = unCox 100s to 10s uA/V2

• Includes DL, DW, DTOX & mobility variations

• Components

– Rs, Cs, Ls

– Diodes

CMOS FET Models

15


Mismatch in CMOS Transistors

Where

– AVT 12.0 mV-um & 7.0 mV-um NMOS and PMOS

respectively node length dependent. (120 to 500nm)

– TOX = 4.45nm & 4.6 nm range for 180nm processes

– KPsat = unCox 350 uA & 70 uA respectively @ VT

CMOS FET Models

(1)

(1)

(1)

16


CMOS Components – Resistors options

Matching – factors Ma, Mw, Ml & Ms

Tolerance – factors

CMOS FET Models

Specification N+ S/D

Resistor

(opndres)

P+ S/D

Resistor

(oppdres)

P+

Polysilicon

Resistor

(opppcres)

RR

Polysilicon

Resistor

(oprrpres)

RR_Serp

Resistor

(rr_serp.)

RP

Polysilicon

Resistor

(oprppres)

K1

BEOL

Resistor

(k1res)

Sheet R

(W/sq)

72 105 260 1600 1600 165 61

Temp Co

(ppm/C)

1900 1340 160 -1360

3.33

-1360

3.33

210 -387

0.41

Voltage Co

(%/V)

0.065 0.054 0 0 0 0 0

V Limit (V) <5.5 <5.5 <5.5 <5.5 <5.5 <5.5 <5.5

Current

(mA/um)

1 1 0.5 0.1 0.1 0.5 0.5

(1)

(1)

17


CMOS Components – Capacitor options

MIM – Metal Insulator Metal

Single, Dual, highK Single and Dual

2.05fF/um2, 4.1fF/um2, 2.7fF/um2, 5.4fF/um2,

MOM – Metal fringe - Density approximately ½.

TempCo, VoltageCo,

Tolerance

Matching – Ma, Mw, & Ml

CMOS FET Models

(1)

18


CMOS Transistor Model Parameters

“hand analysis”

Geometry W & L

Specific current

Slope – n

Cgg, Cdd, & Css – total cap seen at g, d, & s

AVT (KVT )

Early voltage – VA

TempCos –

VT - 0.5 to 2 mV/C,

KP = uoCox - mobility 1/T3/2 From Rm to 275C

CMOS FET Models

19


VT - TempCo

CMOS FET Models

Variation of VT over (27 °C to 275 °C) for PMOS and NMOS devices

of Peregrine 0.5um SOS process. 1.37mV/C

NMOS High Vt Threshold Variation with

temperature

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

27 100 150 200

Temperarture

Th

res

ho

ld V

olt

ag

e

3/0.8

3/1

3/1.3

3/1.6

3/2

PMOS High Vt Threshold Voltage Variation with

temperature

-0.8

-0.7

-0.6

-0.5

-0.4

-0.3

-0.2

-0.1

0

27 100 150 200

Temperarture

Th

resh

old

Vo

ltag

e 3/0.8

3/1

3/1.3

3/1.6

3/2

20


KP - TempCo

CMOS FET Models

Variation of KP over (27 °C to 275 °C) for PMOS and NMOS W

equals [email protected], and L equals 0.8um, and1.6um respectively.

Measured at VGS equal 1V, and VDS equal 50mV. Peregrine 0.5um

SOS process.

uo – mobility

1/T3/2 From Rm to

275C n & p

mobility reduces

by approximately

60%.

21


MOS Switch

CMOS FET Basic Ckts

Square law

R =L

KPWDV

Subthreshold

gmds= gds = 𝑊

𝐿

𝐼𝑆𝑛𝑈𝑇

𝑒𝑥𝑝 𝑉𝐺 −𝑉𝑇𝑛𝑈𝑇

𝑒𝑥𝑝 −𝑉𝐷𝑈𝑇 + 𝑒𝑥𝑝 −

𝑉𝑆𝑈𝑇 =

ID

nUT

22


• Current steering OR Differential pair –

PLLs, current DACs

CMOS FET Basic Ckts

Tail Currernt

Tail Current

22

- -

- -

+ +

+ +

113

300 0

Avoid breaking tail current (Remains in Sat.)

Avoid both switches turning OFF simultaneously

Avoid full switch turn off (No inversion charge) 23


• Current steering OR Differential pair –

PLLs, current DACs

CMOS FET Basic Ckts

Charge injection errors WILL OCCUR

•At turn on “first currents” are channel charge

(unavoidable)

•At turn off “last currents” are injection currents (dummies

can help some, matching is typically poor)

Tail Currernt

Tail Current

22

- -

- -

+ +

+ +

1

13

300 0

24


• Current steering OR Differential pair

CMOS FET Basic Ckts

Charge injection errors WILL OCCUR

•At turn on “first currents” are channel charge

(unavoidable)

•At turn off “last currents” are injection currents (dummies

can help some, matching is typically poor)

Dummy

Dummy Tail Currernt

Tail Current

2 2- -

- -

+ +

+ +

1

13

300 0 31

3

Dwn

Dwn

Up

Up

Dwn

3

1Up

25


• Basic Circuits Simple –CD, CS, CC

CMOS FET Basic Ckts

vin

vo

VD

D

vin

vo

VS

S

vin

vo

Common Drain 𝑉𝐺 − 𝑛𝑉𝑆 − 𝑉𝑇0 = 𝑛 𝑈𝑇𝐿𝑁 𝐼

𝑆 𝐽𝑠0

1

𝑉𝑜 =𝑉𝑖𝑛

𝑛−𝑉𝑇0

𝑛− 𝑈𝑇𝐿𝑁

𝐼

𝑆 𝐽𝑠0

1

26


• Current Mirror Simple

CMOS FET Basic Ckts

M1 & M2

M1 & M2

ID1 ID2

ID1 ID2

𝑉𝐺1− 𝑛𝑉𝑆1− 𝑉𝑇01 = 𝑛 𝑈𝑇𝐿𝑁 𝐼1

𝑆1 𝐽𝑠0

1

𝑉𝐺2− 𝑛𝑉𝑆2− 𝑉𝑇02 = 𝑛 𝑈𝑇𝐿𝑁 𝐼2

𝑆2 𝐽𝑠0

2

𝑛 𝑈𝑇𝐿𝑁 𝐼2

𝑆2 𝐽𝑠0

2

= 𝑛 𝑈𝑇𝐿𝑁 𝐼1

𝑆1 𝐽𝑠0

1

𝑰𝟐 =𝑺𝟐𝑰𝟏𝑺𝟏

=𝑾𝟐𝑰𝟏𝑾𝟏

27


• Current Mirror Simple

CMOS FET Basic Ckts

M1 & M2

M1 & M2

ID1 ID2

ID1 ID2

𝐼𝐷1

ID2= 𝑊𝐿

1𝐼𝐷0𝑖𝑑𝑒𝑎𝑙 1 +

VDS 1VA

𝑊𝐿

2𝐼𝐷0𝑖𝑑𝑒𝑎𝑙 1 +

VDS 2VA

= 𝑊𝐿

1 1 +

VGS 1VA

𝑊𝐿

2 1 +

VDS 2VA

OR ideally

𝐼𝐷1

ID2= 𝑊𝐿 1

1 +VGS 1

VA

𝑊𝐿 2

1 +VDS 2

VA

Err Sources

•W&L matching - Increase Area

•VT matching – Area Fix

•Beta matching (KP = uo Cox)

•VGS1 ≠ VDS2 – Easy Fix

28


• Current Mirror Stacked or Cascode

CMOS FET Basic Ckts

Stacking or cascading the mirrors

VGS1 = VGS2, VDS1 = VDS2

VB3 > VDSsat + VGS3

Sq Law

VB3 > DV1 + VTN + DV3 VTN3 + 2DV for 1 = 3

VD4 > DV2 + DV4 = 2DV for 2 = 4

VTN1 + DV > 2DV OR VTN > DV + 90 C x TempCo 200 to 300 mV

M1 & M2

M1 & M2

ID1ID2

ID1ID2

M3 & M4

VB3

VB2

ID1 ID2

M3 & M4

29



CMOS FET Basic Ckts

SubT

VB3 > DV1 + VGS3 VTN3 - DV + 4UT for 13

VD4 > VDS2 + VDS4 = 8-9 UT

VTN - DV > = 8-9 UT; VTN > 8-9 UT + n UT LN ID1/Is VTN > 300mV+

𝐼𝐷1

ID2= 𝑊𝐿

1 1 +

VGS 1VA

𝑊𝐿

2 1 +

VDS 2VA

𝑊 1

𝑊 2= 𝑛𝑊 1

𝑚𝑊 2=𝑛

𝑚

M1 & M2

M1 & M2

ID1ID2

ID1ID2

M3 & M4

VB3

VB2

ID1 ID2

M3 & M4

30



CMOS FET Basic Ckts

Current transfer or mirroring is set by the finger or multiplier ratio

Current transfer error or mismatch is dominated by VT and the geometry if

the smaller device

Current magnitude, BW, and error are controlled to a first order by the lower

devices

M3 & M4 control VDS1 and VDS2 or the effective of Early Voltage VA

𝐼𝐷1

ID2= 𝑊𝐿

1 1 +

VGS 1VA

𝑊𝐿

2 1 +

VDS 2VA

𝑊 1

𝑊 2= 𝑛𝑊 1

𝑚𝑊 2=𝑛

𝑚

M1 & M2

M1 & M2

ID1ID2

ID1ID2

M3 & M4

VB3

VB2

ID1 ID2

M3 & M4

31



CMOS FET Basic Ckts

Current transfer or mirroring is set by the finger or multiplier ratio

Current transfer error or mismatch is dominated by VT and the geometry if

the smaller device

Small signal – VSB3 = VSB4; k = m/n

gm2 = k gm1; g2 = k g1 ; Cgg2 = k Cgg1

gm4 = k gm3; g4 = k g3 ; Cgg4 = k Cgg3

𝐼𝐷1

ID2= 𝑊𝐿

1 1 +

VGS 1VA

𝑊𝐿

2 1 +

VDS 2VA

𝑊 1

𝑊 2= 𝑛𝑊 1

𝑚𝑊 2=𝑛

𝑚

M1 & M2

ID1 ID2

g1 gm1 vg1 Cgg1 Cgg2 gm2 vg1 g2

iin

VB3

g3 gm3 vg3 g4 gm4 vg4 Iout

32



CMOS FET Basic Ckts

Note for reliable matching L1 = L2 and M1 and M2 are laid out as fingers or

multiples ID2 = m/n ID1 and that mismatched is based on the smaller of m

or n. i.e. for n = 4, m = 8, L = .5um and W = .25um 3 sigma mismatch

equals approx.

𝐼𝐷1

ID2= 𝑊𝐿

1 1 +

VGS 1VA

𝑊𝐿

2 1 +

VDS 2VA

𝑊 1

𝑊 2= 𝑛𝑊 1

𝑚𝑊 2=𝑛

𝑚

∆𝑉𝑇 ≅𝐾𝑉𝑇

𝑊 − 𝐾𝑉𝑇𝑊 𝐿 − 𝐾𝑉𝑇𝑊

𝐾𝑉𝑇

𝑛𝑊 𝐿 =

12.4𝑚𝑉 − 𝑢𝑚

4𝑥0.24𝑢𝑚 . 5𝑢𝑚 = 1.4 𝑥 12.4𝑚𝑉 = 17.5𝑚𝑉

M1 & M2

M1 & M2

ID1ID2

ID1ID2

M3 & M4

VB3

VB2

ID1 ID2

M3 & M4

33


I Proportional to Absolute Temp

CMOS FET Basic Ckts

Note for reliable matching L1 = L2 and M1 and M2 and M3 = M4 are laid

out as fingers or multiples. Select L >= Lmin!.

M1 & M2

M1 & M2

ID1ID2

ID1ID2

M3 & M4

VB2

ID1 ID2

M3 & M4

Bias loop

Ideal 1:1 Mirror

Low voltage constant gm

I1 = I2=I; VGS1 = VGS2 + IR; VT1 =VT2; VS1 = VS2

VG1 – VS1 – VT1 = VG2 – VS2 – VT2+ IR

𝑛 𝑈𝑇𝐿𝑁 𝐼1

𝑆1 𝐽𝑠0

1

= 𝑛 𝑈𝑇𝐿𝑁 𝐼2

𝑆2 𝐽𝑠0

2

+ 𝐼2𝑅

𝑛 𝑈𝑇𝐿𝑁 𝐼

𝑆1 𝐽𝑠0

1

= 𝑛 𝑈𝑇𝐿𝑁 𝐼

𝑆2 𝐽𝑠0

2

+ 𝐼𝑅


𝑆1 𝐽𝑠0

1

− 𝑛 𝑈𝑇𝐿𝑁 𝐼

𝑆2 𝐽𝑠0

2

= 𝐼𝑅

𝐼𝑅 = 𝑛 𝑈𝑇𝐿𝑁𝑆2

𝑆1 = 𝑛 𝑈𝑇𝐿𝑁

𝑊2

𝑊1

𝑰 =𝒏 𝑼𝑻

𝑹 𝑳𝑵

𝑾𝟐

𝑾𝟏 I (PTAT)

34


I Proportional to Absolute Temp

CMOS FET Basic Ckts

Note for reliable matching L1 = L2 and M1 and M2 and M3 = M4 are laid

out as fingers or multiples. Select L >= Lmin!.

𝑉𝐺2− 𝑛𝑉𝑆 − 𝑉𝑇0 = 𝑛 𝑈𝑇𝐿𝑁 𝑊

𝐿

2

𝑉𝐺1− 𝑉𝑇0 = 𝑛 𝑈𝑇𝐿𝑁 𝑊

𝐿

1

M1 M2

M3 M4

Subthreshold

𝐼𝐷1 = 𝐼𝐷2 = 𝐼; 𝑉𝐺𝑆1 = 𝑉𝐺𝑆2 + 𝐼𝑅

𝑛 𝑈𝑇𝐿𝑁 𝑊

𝐿

1

𝑛 𝑈𝑇𝐿𝑁 𝑊

𝐿

2

+ 𝐼𝑅

𝑛 𝑈𝑇𝐿𝑁 𝑊2

𝑊1 = 𝑛 𝑈𝑇𝐿𝑁

𝑚

𝑛 = 𝐼𝑅

𝑹 = 𝒏 𝑼𝑻𝑳𝑵

𝑾𝟐𝑾𝟏

𝑰=𝑳𝑵

𝒎𝒏

𝒈𝒎;

𝑰𝒏 𝑼𝑻

𝑹 𝑳𝑵

𝑾𝟐

𝑾𝟏 I (PTAT)

35


VB3 & VB2

CMOS FET Basic Ckts

Note for reliable matching L1 = L2

= L3 =L4 and M1 and M2 and M3

= M4 are laid out as fingers or

multiples.

a S

S = W/L

I

a S

S = W/L

I

VGS1 –VGS2 > 4UT

VG1-nVS1 –VT1 –(VG2- nVS2 –VT2) = > 4UT

VG1-nVS1 –VT1 –(VG2- nVS2 –VT2) = VD > 4UT


𝑆1 𝐽𝑠0

1


𝑆2 𝐽𝑠0

2

> 4 𝑈𝑇

𝑛 𝑈𝑇𝐿𝑁 𝑆2

𝑆1 > 4 𝑈𝑇

𝒏 𝑳𝑵 𝑺𝟐

𝑺𝟏 > 4 ;𝐹𝑜𝑟 𝑛 = 2;

𝑺𝟐

𝑺𝟏 = 𝟖

36


Stacked Devices

CMOS FET Basic Ckts

S

S = W/L

I

8 S

S = W/L

I

W/L

I

(3W(/(3L)

VB3

VB4

VB4

VB3

VB4

Compare the merits/demerits of

all three approaches used to

stack transistors – in developing a

mirrored current.

Consider Area, Bandwidth, &

mismatch.

Cgg1 gm1 vg1 g1 CL

AC

Device small signal model –

Cgs = Cgg =WLCox/2,

g = gds = ID/VA,

gm/g = = VA/nUT, gm << g

Cd Cgs/4 & CL << Cgs OR Cdb 37


VB3 & VB2

CMOS FET Basic Ckts

M1

M3 M4

I = I

M2

S

8 S

a S

b I = b I

VT2 =VT3 & VT1 < VT4 – Simulation Check


𝑆1 𝐽𝑠0

1


𝑆2 𝐽𝑠0

2

+ 𝑛 𝑈𝑇𝐿𝑁 𝐼

𝑆3 𝐽𝑠0

3

− 𝑛 𝑈𝑇𝐿𝑁 𝑏 𝐼

𝑆4 𝐽𝑠0

4

> 5 𝑈𝑇

𝑛 𝑈𝑇𝐿𝑁 𝑆2 𝑆4

𝑏 𝑆1 𝑆3

1

> 5 𝑈𝑇

S1 = S; S2 = 8 S; S3 = a S; b =2

𝑛 𝑈𝑇𝐿𝑁 𝑆2 𝑆4

𝑏 𝑆1 𝑆3 > 5 𝑈𝑇

𝐿𝑁 8 𝑆4

𝑏 𝑆 >

5

𝑛= 2.5

𝐿𝑁 8 𝑆4

𝑏 𝑆 >

5

𝑛= 2.5

𝟖 𝑺𝟒

𝒃 𝑺 >= 12.2; 𝑆𝟒 >= 12.2

𝟐 𝑺

𝟖 = 𝟑+𝑺

38


• Current Biasing – Global & Local

CMOS FET Basic Ckts

M1 & M2

M1 & M2

ID1ID2

ID1ID2

M3 & M4

VB3

VB2

ID1 ID2

M3 & M4

Bias loopM1 & M2

M1 & M2

ID1ID2

ID1ID2

M3 & M4

VB3

VB2

ID1 ID2

M3 & M4

Bias loop

1:1 Mirror 1:1 Mirror

IRVGSVGS

IIDID

21

21

Classical constant gmLow voltage constant gm

Sq. LAW

𝑉𝑇1 + D𝑉1 = 𝑉𝑇2 + D𝑉2 + 𝐼𝑅 D𝑉1 = D𝑉2 + 𝐼𝑅

D𝑉1

D𝑉2− 1 =

2D𝑉2𝑅 =

𝑔𝑚

2𝑅

2

𝑔𝑚 D𝑉1

D𝑉2− 1 = 𝑅

2

𝑔𝑚

𝑆1

𝑆2− 1 = 𝑅; 𝑤𝑕𝑒𝑟𝑒 𝑆1 =

𝑛𝑊

𝐿

1& 𝑆2 = 𝑚

𝑊

𝐿

2

𝑹 = 𝟐

𝒈𝒎

𝒏𝑾

𝒎𝑾− 𝟏 =

𝟐

𝒈𝒎

𝒏

𝒎− 𝟏 ; 𝒘𝒉𝒆𝒓𝒆 𝑳𝟏 = 𝑳𝟐 = 𝑳

Classical VDD >| VTX| + DV1N + DV1P + DV2P where VTX the greater of |VTP|

OR VTN

Low Voltage VDD >| VTN| + DV1N + 2DVP approx. 600 or 700mV.

Typically m = 2 n to keep DV1 near DV2 and VSB small. In low voltage version R

and M2 can be interchanged. 39


• Current Biasing – Subthreshold

CMOS FET Basic Ckts

M1 & M2

M1 & M2

ID1ID2

ID1ID2

M3 & M4

VB3

VB2

ID1 ID2

M3 & M4

Bias loopM1 & M2

M1 & M2

ID1ID2

ID1ID2

M3 & M4

VB3

VB2

ID1 ID2

M3 & M4

Bias loop

1:1 Mirror 1:1 Mirror

IRVGSVGS

IIDID

21

21

Classical constant gmLow voltage constant gm

•I Portioned to Absolute Temperature IPTAP

•gm set by R and LN(m/n) ratio Typ m/n = 4 to 8

•Use sufficient Area to ensure matching M1 & M2 P & NMOS

Subthreshold

𝐼𝐷1 = 𝐼𝐷2 = 𝐼; 𝑉𝐺𝑆1 = 𝑉𝐺𝑆2 + 𝐼𝑅


𝐼𝑠1 = 𝑛 𝑈𝑇𝐿𝑁

𝐼

𝐼𝑠2 + 𝐼𝑅

𝑛 𝑈𝑇𝐿𝑁 𝑊2

𝑊1 = 𝑛 𝑈𝑇𝐿𝑁

𝑚

𝑛 = 𝐼𝑅

𝑹 = 𝒏 𝑼𝑻𝑳𝑵

𝑾𝟐𝑾𝟏

𝑰=𝑳𝑵

𝒎𝒏

𝒈𝒎; 𝑰 =

𝒏 𝑼𝑻𝑳𝑵 𝑾𝟐𝑾𝟏

𝑹

40


• Current Biasing – Subthreshold

CMOS FET Basic Ckts

•Develop a PTAT bias

generator – assume a

20nA/Leg current.

Use a MOS resistor in place

of an actual resistor!

Homework values used

Model values – Show All Work!

KP (A/V^2)

IS (A)

VT (V)

Avt (V-um)

VA Ls (V) 0.25um

VA LL (V) 0.75um

COX (fF/um^2)

NMOS 330E-6 4.5-13 .3 12 3/2 5 9

PMOS 110E-6 9.0E-13 .35 8

3 10 9 ID-VD Subthreshold

VB1

+Vin/2 -Vin/2

VCM =VDD/2

Ia Ib

M1a M1b

VB1

I I

a S S a S S

41


• Current Biasing – Global to all analog Blks

CMOS FET Basic Ckts

Global Bias Generator

Bias source for all analog blocks i.e. PLL, Amplifiers, Voltage References, ADCs,

DACs, filters etc.

MP1

MP2

MN1MN1

MP3

MN2

MN3 MN4 MN5 MN6

R1

MP5MP4

CC1

VB1 MP6 MP7 MP8 MP9MP10

MP14MP13MP12

MP11

MN14

MN15MN13

MN12

MN11

MN10

MN9

MN8

MN7

I_SOURCE

I_SINK

VDD_REGULATED

VB3VB4

VB2

Start up Bias Loop and Tailless Amplifier Cascode Bias voltages Bias legs

42


• Current Biasing – Global to all analog Blks

CMOS FET Basic Ckts

MP1

MP2

MN1MN1

MP3

MN2

MN3 MN4 MN5 MN6

R1

MP5MP4

CC1

VB1 MP6 MP7 MP8 MP9MP10

MP14MP13MP12

MP11

MN14

MN15MN13

MN12

MN11

MN10

MN9

MN8

MN7

I_SOURCE

I_SINK

VDD_REGULATED

VB3VB4

VB2

Start up Bias Loop and Tailless Amplifier Cascode Bias voltages Bias legs

Constant

gm – Sq. Law

PTAT – Subthreshold & bipolar

Constant gain or DV – Replace R with MOS R

Sq. Law

R =1

RDVDD=

2

2DV2

n

m− 1 ; where L1 = L2 = L

𝟐

𝑹= 𝑺𝟐

𝑺𝑹=𝟐D𝑽𝑫𝑫

D𝑽𝟐

𝒏

𝒎− 𝟏 ; 𝒘𝒉𝒆𝒓𝒆 𝑳𝟏 = 𝑳𝟐 = 𝑳

DV2/DVDD approx. constant

Blocks –

Bias Loop – Positive feedback is

possible

Start-up REQUIRED! Start-up matters

Latch up is possible!

Bias Legs 43


M1 & M2

M1 & M2

ID1ID2

ID1ID2

M3 & M4

VB2

ID1 ID2

M3 & M4

Bias loop

1:1 Mirror

MP1

MP2

MN1MN1 MN2

VG1 VG2

IB

• Bias Loop & Startup–

CMOS FET Basic Ckts

Blocks –

Bias Loop – Positive feedback is

possible

Start-up REQUIRED! Start-up matters

Latch up is possible!

Constant

gm – Sq. Law

PTAT – Subthreshold & bipolar

Constant gain or DV – Replace R with MOS R

Sq. Law

R =1

RDVDD=

2

2DV2

n

m− 1 ; where L1 = L2 = L

𝟐

𝑹= 𝑺𝟐

𝑺𝑹=𝟐D𝑽𝑫𝑫

D𝑽𝟐

𝒏

𝒎− 𝟏 ; 𝒘𝒉𝒆𝒓𝒆 𝑳𝟏 = 𝑳𝟐 = 𝑳

DV2/DVDD approx. constant

44


• Bias Loop & Startup–

CMOS FET Basic Ckts

Cascode Bias (optional) VB2 & VB3

VB3 > DV9 + VTN8 + DV8 VTN8 + 2DV for 1 = 3

o SubT

VB3 > DV9 + VGS8 VTN8 - nUTLN( + 4UT for 13

𝑉𝐺𝑆 = 𝑛 𝑈𝑇𝐿𝑁 𝐼𝐷𝐼𝑠

𝐿

𝑊

𝑉𝐵3 = 𝑉𝐺𝑆𝑁7 = 𝑉𝐺𝑆𝑁8 + 5 𝑈𝑇 = 𝑛 𝑈𝑇𝐿𝑁 𝐼𝐷𝐼𝑠 𝐿

𝑊

8𝑁 + 5 𝑈𝑇

𝑉𝐺𝑆𝑁7 − 𝑉𝐺𝑆𝑁8 = 5 𝑈𝑇 = 𝑛 𝑈𝑇𝐿𝑁 𝐼𝐷𝐼𝑠 𝐿

𝑊

7𝑁 − 𝑛 𝑈𝑇𝐿𝑁

𝐼𝐷𝐼𝑠 𝐿

𝑊

8𝑁

5

𝑛 = 𝐿𝑁

𝐼𝐷7

𝐼𝐷8

𝑊8𝑁

𝑊7𝑁 ≈ 2.5

VB2 is handled in a similar manner.

MP7 MP8

MP11

MN9

MN8

MN7

VB3VB4

VB2

Cascode Bias voltages

VDD

VSS

Mirroring – matching and therefor area of

rail side devices is critical

45


• Bias Generators

CMOS FET Basic Ckts

Good practices –

• All rail side devices are long to reduce mismatch, 1/f noise,

improve PSRR. Their ONLY role is to establish stable low noise

bias currents.

• All rail side devices have a finger or multiplicity common

denominator for N and PMOS devices

• Rail side devices are 2-3X longer than stacked or cascode

devices. The accuracy is necessary.

• Global bias sets gm of all analog blocks and as a result they all

track across temperature and process. The gm in bandwidth of

all analog blocks.

46


Amplifiers

CMOS FET Basic Ckts

Small signal parameters & some assumptions

• gm – I/nUT (SUbT), 2I/DV, (Sq. Law) other forms

• gds = gd = g = VA/ID Cadence simulation

• Cgg Cgs Cgg, Cadence simulation

• Cgd << Cgs, Cdb, Cgg, AND Cdd 0

47


Common Source

CMOS FET Basic Amplifers

ID1

Vo Cgg1 gm1 vg1 g1 CL

AC

Figure 1.1 Common Source

𝑔𝑚1 𝑣𝑖𝑛 + 𝑣𝑜 𝑔1 + 𝐶𝐿 = 0

𝑣𝑜

𝑣𝑖𝑛= −

𝑔𝑚

𝑔1 + 𝐶𝐿 = −

𝑔𝑚

𝑔1 + 𝑛𝐶𝑔𝑔 = −

𝐼/𝑛𝑈𝑇

𝐼𝑉𝐴+ 𝑠 𝑚𝐶𝑔𝑔

𝑣𝑜

𝑣𝑖𝑛= −

𝑉𝐴𝑛𝑈𝑇

1 + 𝑠𝑚𝐶𝑔𝑔𝑔

= −𝑉𝐴

𝑛𝑈𝑇

1 + 𝑠𝑉𝐴𝐼 𝑚𝐶𝑔𝑔

= −−

1 + 𝑠𝑉𝐴𝐼 𝑚𝐶𝑔𝑔

48


Common Source


ID1

Vo Cgg1 gm1 vg1 g1 CL

AC

CS Observations

o Self gain independent of ID

o GBP equals gm/CL = gm/mCgg – Larger loads require large

devices OR gm!

o VA increases with length increasing but decreases BW

o Increasing I decreases ro increasing f3dB and GBP.

49


Current Mirror


M1 & M2

ID1 ID2

g1 gm1 vg1 Cgg1 Cgg2 gm2 vg1 g2

iin

𝑖𝑖𝑛 = 𝑔𝑚 𝑣𝑔1 + 𝑣𝑔1 𝑠𝐶𝑔𝑔1 + 𝑠 𝐶𝑔𝑔2 + 𝑣𝑔1 𝑔1

𝑖𝑜 = 𝑔𝑚2 𝑣𝑔2 = 𝑔𝑚2 𝑣𝑔1; 𝐴𝑠𝑠𝑢𝑚𝑒 𝐿1 = 𝐿2 = 𝑙 𝑎𝑛𝑑𝑊2

𝑊1= 𝑚/𝑛

𝑖𝑜

𝑖𝑖𝑛=

𝑔𝑚2

𝑔𝑚1 + 𝑠 𝐶𝑔𝑔1 + 𝑠 𝐶𝑔𝑔2 + 𝑔1≈

𝑚/𝑛

1 + 𝑠 𝐶𝑔𝑔1 + 𝑠 𝑚 𝑛 𝐶𝑔𝑔1

𝑔𝑚1

𝑖𝑜

𝑖𝑖𝑛=

𝑚/𝑛

1 + 𝑠 𝐶𝑔𝑔1 1 +𝑚

𝑛 𝑔𝑚1

m/n should be kept small to maintain BW.

Yin(s) = gm + s(Cgg1 + Cggs 50


Common Drain – Large Signal


Vo

Cgg1 gm1 vg1 g1

AC

Vin

VB1

CL g2

CL

M1

M2

vo

𝑉𝐼𝑁 = 𝑉𝐺𝑆𝑁1 + 𝑉𝑜;𝑉𝑜 > 5 𝑈𝑇

𝑉𝐼𝑁 = 𝑉𝐺𝑆𝑁1 + 𝑉𝑜;𝑉𝑜 > 5 𝑈𝑇 = 𝑉𝑇𝑁1 − 𝑛 𝑈𝑇𝐿𝑁 𝐼𝐷2

𝐼𝑠 𝐿

𝑊

1𝑁 + 𝑉𝑜

51


Common Drain – Small Signal Rgen =0


Vo

Cgg1 gm1 vg1 g1

AC

Vin

VB1

CL g2

CL

M1

M2

vo

𝑔𝑚1 𝑣𝑖𝑛 − 𝑣𝑜 = 𝑣𝑜 − 𝑣𝑖𝑛 𝑠 𝐶𝑔𝑔1 + 𝑣𝑜 𝑔1 + 𝑔2 + 𝑠 𝐶𝐿

𝑣𝑜(𝑔𝑚1 + 𝑔1 + 𝑔2 + 𝑠 𝐶𝐿) = 𝑣𝑖𝑛 (𝑔𝑚1 + 𝑠 𝐶𝑔𝑔1

𝑣𝑜

𝑣𝑖𝑛≈

𝑔𝑚1 + 𝑠 𝐶𝑔𝑔1

𝑔𝑚1 + 𝑠 𝐶𝐿 + 𝑠 𝐶𝑔𝑔1 =

𝑔𝑚1 + 𝑠 𝐶𝑔𝑔1

𝑔𝑚1 + 𝑠( 𝑚 + 1) 𝐶𝑔𝑔1 =

1 + 𝑠 𝐶𝑔𝑔1𝑔𝑚1

1 + 𝑠 (𝑚 + 1) 𝐶𝑔𝑔1

𝑔𝑚1

52


Common Drain – Small Signal Rgen ≠0


Vo

Cgg1 gm1 vg1 g1

AC

Vin

VB1

CL g2

CL

M1

M2

vo

𝑔𝑚1 𝑣𝑔 − 𝑣𝑜 = 𝑣𝑜 − 𝑣𝑔 𝑠 𝐶𝑔𝑔1 + 𝑣𝑜 𝑔1 + 𝑔2 + 𝑠 𝐶𝐿

𝐺𝑔𝑒𝑛 𝑣𝑔 − 𝑣𝑖𝑛 = 𝑣𝑔 − 𝑣𝑜 𝑠 𝐶𝑔𝑔1

𝑣𝑜

𝑣𝑖𝑛=

𝐺𝑔𝑒𝑛 𝑔𝑚1 + 𝑠 𝐶𝑔𝑔1

− 𝑚 𝑠 𝐶𝑔𝑔1 2 + 𝑠 𝐶𝑔𝑔1(𝐺𝑔𝑒𝑛 𝑚 + 1 − 𝑔1− 𝑔2) + 𝐺𝑔𝑒𝑛 𝑔𝑚1

𝑣𝑜

𝑣𝑖𝑛≈

𝐺𝑔𝑒𝑛 𝑔𝑚1 + 𝑠 𝐶𝑔𝑔1

− 𝑚 𝑠 𝐶𝑔𝑔1 2 − 𝑠 𝐶𝑔𝑔1(2𝑔1) + 𝐺𝑔𝑒𝑛 𝑔𝑚1

Rgen adds second poles severely limits BW!!! --- Use can be quite limited!

53


Common Gate – Cascode


Vo

- gm2 vg2 g2 =g

vin

Vin OR VB1

VB2CL = nCgg2

g1 = g

Css2 = Cgg2

M1

M2

iin

Ideal current source

Vo

CL = nCgg2

M2

g1

g2

gm1 vin

𝑔𝑚1 𝑣𝑖𝑛 + 𝑣𝑠 𝑔𝑚2 + 𝑔1 + 𝑔2 + 𝑠 𝐶𝑠𝑠2 − 𝑣𝑜 𝑔2

≈ 𝑔𝑚1 𝑣𝑖𝑛 + 𝑣𝑠 𝑔𝑚2 + 𝑔 + 𝑠 𝐶𝑠𝑠2 − 𝑣𝑜 𝑔

𝑣𝑜 𝑔2 + 𝑠 𝐶𝐿 − 𝑔𝑚2 𝑣𝑠 − 𝑣𝑠 𝑔2 ≈ 𝑣𝑜 𝑔 + 𝑠 𝐶𝐿 − 𝑔𝑚2 𝑣𝑠

𝑣𝑜 = −

𝑔𝑚1 𝑔𝑚2𝑔1 𝑔2 𝑣𝑖𝑛

𝐶𝐿 𝐶𝑔𝑔2 𝑠2 + 𝑠 𝐶𝐿 𝑔𝑚2 + 1 ;𝑓𝑜𝑟 𝑔 ≪ 𝑔𝑚 & 𝐶𝑔𝑔2 < 𝐶𝐿/

54




Solving for vo/vin and sub n CL = Cgg2

𝐴 𝑠 = −

𝑔𝑚1 𝑔𝑚2𝑔1 𝑔2

𝐶𝐿 𝑟1 𝐶𝑔𝑔2 𝑟2 𝑠2 + 𝑠 𝐶𝐿 2 𝑟1 + 1≈ −

12

𝑛 𝐶𝑔𝑔2 2𝑟2 𝑠2 + 𝑠 𝑛 𝐶𝑔𝑔2 2 𝑟 + 1

Pole splitting --- dominant pole and non-dominant pole

𝐴 𝑠 = −12 𝑣𝑖𝑛

𝑑 𝑠 + 1 𝑎 𝑠 + 1 = −

12 𝑣𝑖𝑛

𝑎 𝑑 𝑠2 + 𝑠 𝑎 + 𝑑 + 1 ≈ −

12 𝑣𝑖𝑛

𝑎 𝑑 𝑠2 + 𝑠 𝑑 + 1

dom = 1/(2 r CL) = gm1/(2 1 CL) = gm1/(2 1 n Cgg2) ;

dom = gm1/(2 1 CL); GBP = gm1/CL = gm1/n Cgg2

non = ad/d = gm2/Cgg2 = TA2

non > GBP then n > 1

55




dom = 1/(2 r CL) = gm1/(2 1 CL) = gm1/(2 1 n Cgg2) ;

dom = gm1/(2 1 CL); GBP = gm1/CL = gm1/n Cgg2

non = ad/d = gm2/Cgg2 = TA2

non > GBP then n > 1

20 Log A

f3dB

GBP = gm/CL

T = gm2/Cgg

0dB

40 LOG dB

VA/nUT OR 2 VS/DV

gm = ID/nUT OR DV

56


Differential Pair Sq. Law


VB1

+Vin/2 -Vin/2

VCM =VDD/2

Ia Ib

M1a M1b

𝑉𝐼𝑁2

= 𝑉𝐺𝑁1𝑎−𝑉𝑆𝑁1𝑎 − 𝑉𝐺𝑁1𝑏−𝑉𝑆𝑁1𝑏 −𝑉𝐼𝑁2

;

𝐼 = 𝐼𝑎 + 𝐼𝑏

𝑉𝐼𝑁 = 𝑉𝐺𝑆𝑁1𝑎 − 𝑉𝐺𝑆𝑁1𝑏 ;

𝑉𝐼𝑁 = ∆𝑉𝑎 + 𝑉𝑇𝑁1𝑎 − ∆𝑉𝑏− 𝑉𝑇𝑁1𝑏 ≈ ∆𝑉𝑎 − ∆𝑉𝑏

𝑉𝐼𝑁 = 2 𝐼𝑎 − 2 𝐼𝑏

𝑖𝐷𝑎 =𝐼

2 1 +

𝑉𝑖𝑛2

𝐼−

𝑉𝑖𝑛2

2𝐼

2

𝑖𝐷𝑏 =𝐼

2 1−

𝑉𝑖𝑛2

𝐼−

𝑉𝑖𝑛2

2𝐼

2

𝑖𝐷𝑖𝑓𝑓

𝐼= 𝑖𝐷𝑎𝐼−𝑖𝐷𝑏𝐼

= 𝑉𝑖𝑛2

𝐼−

𝑉𝑖𝑛2

2𝐼

2

Taking the derivative w.r.t. Vin = Vindif gmeff = 𝐼

𝐼=

∆𝑉

𝐼

57


Differential Pair – SubT


VB1

+Vin/2 -Vin/2

VCM =VDD/2

ID1

ID2

M1 M2

ID1 + ID2 = I;

VDiff = VG1 – VG2;

𝑉𝐷𝑖𝑓𝑓 = 𝑛 𝑈𝑇𝐿𝑁 𝐼1

𝑆1 𝐽𝑠0

1

− 𝑛 𝑈𝑇𝐿𝑁 𝐼2

𝑆2 𝐽𝑠0

2

Solving for I1-I2

k/n - 1

I k/n

58




VB1

+Vin/2 -Vin/2

VCM =VDD/2

Ia Ib

M1a M1b

ID= IF-IR = IDOexp VG

nUT exp

-VS

UT -exp

-VD

UT ≈ IDOexp

VG

nUT exp

-VS

UT (1.1)

VG = 𝑛𝑈𝑇 𝐿𝑁 𝐼𝐷

IDO − 𝑛𝑈𝑇 𝐿𝑁 1− exp

-VS

UT + n VS

(1.1)

Substituting for VGNA1 & VGN1b

𝑉𝐼𝑁 = 𝑛𝑈𝑇 𝐿𝑁 𝐼𝐷𝑎IDO − 𝑛𝑈𝑇 𝐿𝑁 1 − exp

-VS

UT + n VS

− 𝑛𝑈𝑇 𝐿𝑁 𝐼𝐷𝑏IDO − 𝑛𝑈𝑇 𝐿𝑁 1 − exp

-VS

UT + n VS

𝑉𝐼𝑁 = 𝑛𝑈𝑇 𝐿𝑁 𝐼𝐷𝑎IDO − 𝑛𝑈𝑇 𝐿𝑁

𝐼𝐷𝑏IDO = 𝑛𝑈𝑇 𝐿𝑁

𝐼𝐷𝑎IDb

59




VB1

+Vin/2 -Vin/2

VCM =VDD/2

Ia Ib

M1a M1b

Substituting IDb = I - IDa & solving for IDa and likewise for IDb

𝐼𝐷𝑎 =𝐼 exp

VinnUT

exp VinnUT

+ 1 ; 𝐼𝐷𝑎 =

𝐼

exp VinnUT

+ 1

𝐼𝐷𝑎 − 𝐼𝐷𝑏 = 𝐼𝐷𝑖𝑓 = 𝐼 exp

VinnUT

exp VinnUT

+ 1−

𝐼

exp VinnUT

+ 1= 𝐼 exp

VinnUT

− 1

exp VinnUT

+ 1

𝐼𝐷𝑖𝑓

𝐼= exp

VinnUT

− 1

exp VinnUT

+ 1

𝐼𝐷𝑖𝑓

𝐼= exp

VinnUT

− 1

exp VinnUT

+ 1= 𝑇𝐴𝑁𝐻

𝑉𝑖𝑛2𝑛𝑈𝑇

60




VB1

+Vin/2 -Vin/2

VCM =VDD/2

Ia Ib

M1a M1b

Summary

gmeff =I/(2 nUT) -- 1/2 nUT verses 𝐼

𝐼=

∆𝑉

𝐼

Slew limiting +/- 5 = 𝑉𝑖𝑛

2𝑛𝑈𝑇 OR Vin > 500mV ±10𝑛𝑈𝑇 𝑂𝑅 ± 2∆𝑉

No even order harmonics

Taylor series

𝐼𝐷𝑖𝑓

𝐼=

𝑣𝑖𝑛2𝑛𝑈𝑇

1−1

3 𝑣𝑖𝑛

2𝑛𝑈𝑇

2

+2

15 𝑣𝑖𝑛

2𝑛𝑈𝑇

4

61


• Differential Amp


VB1

+Vin/2 -Vin/2

VCM =VDD/2

Ia Ib

M1a M1b

Vo

gp gmp vgp Cggp Cggp gm2 vgp gp

gmn vin/2 gn Cdb - gmn vin/2 gn

CL >> Cdbn OR Cdbp

Small signal simplifications

• CL >> Cdb & Cgg = Css

• gm >> g

• Ignore gmbs effect

• Cdb 0

Vgp node: 𝑔𝑚𝑛 𝑣𝑖𝑛

2+ 𝑣𝑔 𝑔𝑚𝑝 + 𝑔𝑛 + 𝑔𝑝 + 𝑠 2 𝐶𝑔𝑔2 + 𝑠 𝐶𝑑𝑏𝑛 + 𝑠 𝐶𝑑𝑏𝑝

Vo node: −𝑔𝑚𝑛 𝑣𝑖𝑛

2+ 𝑣𝑜 𝑔𝑛 + 𝑔𝑝 + 𝑠 𝐶𝐿 + 𝑔𝑚𝑝 𝑣𝑔

𝐴𝑣𝑜𝑙

= 𝑔𝑚𝑛 · 𝑣𝑖𝑛 · (𝐶𝑑𝑏𝑛 · 𝑠 + 𝐶𝑑𝑏𝑝 · 𝑠 + 2 · 𝐶𝑔𝑔2 · 𝑠 + 2 · 𝑔𝑚𝑝 + 𝑔𝑛 + 𝑔𝑝)

2 · (𝐶𝐿 · 𝑠 + 𝑔𝑛 + 𝑔𝑝) · (𝐶𝑑𝑏𝑛 · 𝑠 + 𝐶𝑑𝑏𝑝 · 𝑠 + 2 · 𝐶𝑔𝑔2 · 𝑠 + 𝑔𝑚𝑝 + 𝑔𝑛 + 𝑔𝑝)

62




VB1

+Vin/2 -Vin/2

VCM =VDD/2

Ia Ib

M1a M1b

Vo

gp gmp vgp Cggp Cggp gm2 vgp gp

gmn vin/2 gn Cdb - gmn vin/2 gn

CL >> Cdbn OR Cdbp

Small signal simplifications


• gm >> g


• Cdb 0

𝑨𝒗𝒐𝒍 ≈ 𝒈𝒎𝒏 · 𝒗𝒊𝒏 · ( 𝟐 · 𝒈𝒎𝒑 + 𝒔 𝑪𝒑 )

𝟐 · (𝑪𝑳 · 𝒔 + 𝒈𝒐) · ( 𝒈𝒎𝒑 + 𝒔 𝑪𝒑 )

𝑣𝑔

𝑣𝑖𝑛=

𝑔𝑚𝑛

2 · (𝐶𝑑𝑏𝑛 · 𝑠 + 𝐶𝑑𝑏𝑝 · 𝑠 + 2 · 𝐶𝑔𝑔2 · 𝑠 + 𝑔𝑚𝑝 + 𝑔𝑛 + 𝑔𝑝)

𝑨𝒗𝒐𝒍 ≈𝒈𝒎𝒏 · 𝝁𝒏 · 𝝁𝒑

𝒈𝒎𝒏 · 𝝁𝒑 + 𝒈𝒎𝒑 · 𝝁𝒏 ;

𝒗𝒈

𝒗𝒊𝒏≈ −

𝒈𝒎𝒏

𝒈𝒎𝒑

63




VB1

+Vin/2 -Vin/2

VCM =VDD/2

Ia Ib

M1a M1b

Vo

3dB =( gn + gp)/CL

GBP = gmn/CL

0dB

20 LOG( N||p ) dB

non = gmp/Cpz = 2gmp/Cp

𝑨𝒗𝒐𝒍 ≈𝒈𝒎𝒏 · 𝝁𝒏 · 𝝁𝒑

𝒈𝒎𝒏 · 𝝁𝒑 + 𝒈𝒎𝒑 · 𝝁𝒏 ;

𝒗𝒈

𝒗𝒊𝒏≈ −

𝒈𝒎𝒏

𝒈𝒎𝒑

64


• Low gain Amps


• Low gain amplifiers with

gm loading

• Small signal simplifications


• gm >> g


• Cdb 0

VCMoVCMREF

Vo

VB1

M1CMd M1CMa

ICM

tail

ICM

tail /2

ICM

tail /2

VB3

M2CMb M2CMa

Vo

gmn vo gn/n CL

(VCMREF -Vcmo) gmp/2 gp

Vo node: −𝑔𝑚𝑝 𝑣𝑖𝑛𝑑𝑖𝑓

2+ 𝑣𝑜 𝑔𝑚𝑛 + 𝑔𝑛/𝑛 + 𝑔𝑝 + 𝑠 𝐶𝐿

𝒗𝒐 =𝒈𝒎𝒑 𝒗𝒊𝒏𝒅𝒊𝒇

𝒈𝒎𝒏 · 𝟏 + 𝑪𝑳 · 𝒔𝒈𝒎𝒏

= 𝒑

𝒏

𝒗𝒊𝒏𝒅𝒊𝒇

𝟏+ 𝑪𝑳 · 𝒔𝒈𝒎𝒏

Square law adjusting geometry controls gain 65


• Low gain Amps



gm loading



• gm >> g


• Cdb 0

Subthreshold gain adjust

gmp/gmn = ICMtail/Ip = 1/a where a < 1 taking on values of ½ to 1/8.

𝒗𝒐 =𝟏

𝟐

𝒈𝒎𝒑 𝒗𝒊𝒏𝒅𝒊𝒇

𝒈𝒎𝒏 · 𝟏 + 𝑪𝑳 · 𝒔𝒈𝒎𝒏

=𝟏

𝟐𝒂

𝒗𝒊𝒏𝒅𝒊𝒇

𝟏 + 𝑪𝑳 · 𝒔𝒈𝒎𝒏

VCMoVCMREF

Vo

VB4

VB1

M1CMd M1CMc M1CMb M1CMa

ICM

tail

a IC

Mta

il /2

a IC

Mta

il /2

[1-a

] ICM

tail /2

[1-a

] ICM

tail /2

VB3

VB4

M2CMb M2CMa

Gain = A = 1/2

Vo

gmn vo gn/n CL


66


• Low gain using negative feedback



gm loading



• gm >> g


• Cdb 0

VCMoVCMREF

VB1

M1CMd M1CMa

ICM

tail

4(2

+1

/n) IS

TA

B

ICM

tail /2

ICM

tail /2

VB3

M2CMb M2CMa

2(n+1) 2(n+1)2n 2n

Gain = A = (2n+1)/2

n

(4n+2) (4n+2)

2 IS

TA

B

4(2n+1)

Vo

Vo


vo gmna - gmnb vo gn/n CL

Vo node −𝑔𝑚𝑝 𝑣𝑖𝑛𝑑𝑖𝑓

2+ 𝑣𝑜 𝑔𝑚𝑛+ − 𝑔𝑚𝑛− +

𝑔𝑛

𝑛+ 𝑔𝑝 + 𝑠 𝐶𝐿

− 𝑔𝑚𝑝 𝑣𝑖𝑛𝑑𝑖𝑓

2+ 𝑣𝑜 𝑔𝑚𝑛+ − 𝑔𝑚𝑛− + 𝑠 𝐶𝐿

𝒗𝒐 =𝒈𝒎𝒑 𝒗𝒊𝒏𝒅𝒊𝒇

𝟐D𝒈𝒎𝒏 · 𝟏+ 𝑪𝑳 · 𝒔D𝒈𝒎𝒏

D𝑔𝑚𝑛 =2𝑛 + 2− 2𝑛

4𝑛 + 2 =

1

2𝑛 + 1 ; 𝑠𝑢𝑏𝑡𝑕𝑟𝑒𝑠𝑕𝑜𝑙𝑑

67


DC Voltage Reference


R5

R4 D1

NETB

R1

D2

NETC

VREF

R5

R4

(1)

(1)

(1)

VREF=n ∙ VT ∙ ln K ∙ N.R1

R1+

N ∙ VD1

L

68




R5

R4 D1

NETB

R1

D2

NETC

VREF

R5

R4

L=

∂VD1∂T

n∙ ln K ∙∂VT∂T

=9.41

N= VREF

n VT∙ ln K +VD1

L

=3.28

69


R1+

N ∙ VD1

L




L=

∂VD1∂T


=9.41

N= VREF

n VT∙ ln K +VD1

L

=3.28

MP7

MP8

R5

R4 D1

MP9MP9

MP10

MP11

MP12

MN7

MN8

MN6

MN5

R1

D2

MP13

MP14

CC

VDDA

NETCNETB

VB

VB2

VB1

VB

c

R6

MP15

MP16

VREF

CLR5

R4

70


R1+

N ∙ VD1

L




L=

∂VD1∂T


=9.41 N=

VREF

n VT∙ ln K +VD1

L

=3.28

VDD_REGULATED

Start up Bias Loop PTAT & CTAT Legs

Voltage Reference

c

MP1

MP2

MN1MN1 MN2

MP3

MP4

MN3MN4

MP7

MP8

R5

R4 D1

MP5

MP6

MP9MP9

MP10

MP11

MP12

MN7

MN8

MN6

MN5

R1

D2

R2

R3

R6

MP13

MP14

MP15

MP16

VREF

MP17

MP18

LDO2LDO1

CC

VDDA

NETCNETB

VB

CL

VB2

MP19MP19

MP20

71


R1+

N ∙ VD1

L


Gain Boosting


Vo

- gm2 vg2 g2 =g

vin

Vin OR VB1

CL = nCgg2g1 = g

Css2 = Cgg2

M1

M2

Ideal current source

Vo

CL = nCgg2

M2

g1

gm1 vin

g1

Cd = Cdb + Csb

gmb vs gb

vo node; 𝑣𝑏𝑠𝑡 · 𝑔𝑚 − 𝑣𝑠2 · 𝑔𝑚 + 𝑣𝑜 · (𝑔 + 𝑠 · 𝐶𝐹) − 𝑠 · 𝐶𝐹 · 𝑣𝑓𝑏 − 𝑣𝑠2 · 𝑔 = 0

vs node; 𝑔𝑚𝑑𝑝 · 𝑣𝑓𝑏 + 𝑣𝑠2 · 2 · 𝑔 + 𝑔𝑚 + 𝑣𝑠2 · 𝑠 · 𝐶𝑔 · 1 + 𝑘 − 𝑣𝑏𝑠𝑡 · 𝑠 · 𝐶𝑔 −

𝑣𝑏𝑠𝑡 · 𝑔𝑚 − 𝑣𝑜 · 𝑔 = 0

vg node 𝑘 · 𝑔𝑚 · 𝑣𝑠2 + 𝑣𝑏𝑠𝑡 · 𝑘 · 𝑔 + 𝑠 · 𝐶𝑔 + 𝑠 𝐶𝑐𝑏𝑠𝑡 − 𝑣𝑠2 · 𝑠 · 𝐶𝑔 = 0;

vfb (optional Closed Loop) 𝑣𝑓𝑏 · (𝑠 · 𝐶𝐹 + 𝑠 · 𝐶𝐼𝑁) − 𝑣𝑖𝑛 · 𝑠 · 𝐶𝐼𝑁 − 𝑣𝑜 · 𝑠 · 𝐶𝐹 = 0


gm loading



• gm >> g


• Cdb 0

72


Gain Boosting


Solving for Av = vo/vin and substituting for b x gmbst = gm1 = gm2 = gm, g1 = g2 = b x gbst = g, =

gm/g and >>1.

@ DC [𝑣𝑏𝑠𝑡 = 𝐶𝐼𝑁 · 𝑣𝑖𝑛/(𝐶𝐹 · 𝜇) ∧ 𝑣𝑓𝑏 = 𝐶𝐼𝑁 · 𝑔𝑚 · 𝑣𝑖𝑛/(𝐶𝐹 · 𝑔𝑚𝑑𝑝 · 𝜇^3) ∧ 𝑣𝑜 = − 𝐶𝐼𝑁 ·

𝑣𝑖𝑛/𝐶𝐹 ∧ 𝑣𝑠2 = − 𝐶𝐼𝑁 · 𝑣𝑖𝑛/(𝐶𝐹 · 𝜇^2)]

𝑣𝑔 =𝑔𝑚𝑑𝑝 · 𝑣𝑖𝑛 · (𝐶𝐹 · 𝜇 · 𝑠 + 𝑔𝑚) · (𝑔𝑚 · 𝑘 − 𝐶𝑔 · 𝑠)

𝑘 · 𝜇 · (𝐶𝐹 · 𝐶𝑔2 · 𝑠3 + 𝐶𝐹 · 𝐶𝑔 · 𝑔𝑚 · 𝑠2 + 𝐶𝐹 · 𝑔𝑚2 · 𝑠 + 𝑔𝑚2 · 𝑔𝑚𝑑𝑝)

𝑠𝑧 = −𝑔𝑚

𝐶𝐿 · 𝜇; 𝑠𝑧 =

𝑘 𝑔𝑚

𝐶𝑔= 𝑔𝑚𝑏𝑠𝑡

𝐶𝑔

𝑨𝒗𝒖𝒏𝒊𝒕𝒚 =𝐶𝐹 · 𝐶𝑔^2 · 𝑠3 + 𝐶𝐹 · 𝐶𝑔 · 𝑔𝑚 · 𝑠2 + 𝐶𝐹 · 𝑔𝑚2 · 𝑠 − 𝑔𝑚2 · 𝑔𝑚𝑑𝑝

𝑘 · 𝜇 · (𝐶𝐹 · 𝐶𝑔2 · 𝑠3 + 𝐶𝐹 · 𝐶𝑔 · 𝑔𝑚 · 𝑠2 + 𝐶𝐹 · 𝑔𝑚2 · 𝑠 + 𝑔𝑚2 · 𝑔𝑚𝑑𝑝)

𝑧 = 𝑔𝑚𝑑𝑝

𝐶𝐹; 𝑢𝑛 = −

𝑔𝑚

𝐶𝐹;𝑝𝑙𝑢𝑠 𝑡𝑤𝑜 𝑛𝑜𝑛𝑑𝑜𝑚 𝑐𝑜𝑚𝑜𝑝𝑙𝑒𝑥 𝑝𝑜𝑙𝑒𝑠; −

𝑔𝑚

𝐶𝑔;

• GBP = gm/CL;

• Observations:

• Increased gain at no loss in GBP bandwidth

• Scale boosting by k = ¼

• gm/Cp = TA >> GBP = gm/CF

73


Noise Basics

Noise

Noise Basics

Noise is just another signal error like CMRR and PSRR

EMI – RF coupling supply & ground, crosstalk, rectification

Measurement errors – “quantization noise”

Electronic

Thermal – constant value across frequency – vn2 = 4 kTR

Temperature T in Kelvin, k Boltzmann’s constant, R in ohms

Shot – in2 = 2 q IDC (current flow across a P-N junction (charge impulse – white spectrum)

DC current flow, q charge on a carrier

Flicker or 1/f - Vnf(f) = Kv/f i.e. 10 uV/Hz

Avalanche noise – PN junction breakdown

Phase noise – alternate form of thermal, shot and1 /f etc.

Input/output referred – Cs

74


Noise Basics

Noise

Definitions – Noise related

Vnrms = [1/T vn2(t) dt]1/2 Inrms = [1/T in

2(t) dt]1/2

Pdiss = Vnrms2 / 1 “1 ohm for simplicity”

SNR = 10 Log {Signal Pwr/Noise Pwr} “even if R 1 it cancels”

SNR = 10 Log {(Vp2/2)/ Vnrms2} = SNR = 20 Log {Vp/ (2 Vnrms)}

dBm - Refencing of signals to 1 mW or 223.6 mV across a 50 resistor

Types of “noise” Thermal, 1/f, quantization, distortion, and EMI

We are concerned with only thermal and 1/f in this context. `

10^-5

10-6

10-7

10-8

102 10

410

610

8 1010

1012

V/r

t(H

z)

Hz

75


Noise Basics

Noise

Noise is random with a mean value of zero, hence we use mean square values, which are

measurements of the dissipated noise power levels. The effective noise power of a source is

measured in root mean square of rms values.

𝑣𝑛 = 𝑣𝑛2; 𝑂𝑅 𝑖𝑛 = 𝑖𝑛

2;

Noise spectrum density describes the noise power in a 1 Hz bandwidth using units of V2/Hz

and plotted as above as V/Hz.

Total or effective noise is found by integrating the spectral noise density function

𝑣𝑛 = 𝑆𝑣𝑛 𝑓 𝑓2

𝑓1

𝑑𝑓 = 𝑂𝑅 𝑖𝑛 = 𝑆𝑖𝑛 𝑓 𝑓2

𝑓1

𝑑𝑓

Uncorrelated noise - Noise sources, thermal and 1/f are for the most part considered

uncorrelated

Therefore

V2no = V2

n1 + V2n2 V

2n3 + ... + V2

nn and likewise for noise currents.

I2no = I2n1 + I2n2 i2n3 + ... + I2nn

“Square root sum of the squares” 76


Noise Basics

Noise

** ** **

**

Vn1(t)

Vn2(t)

In1(t) in2(t)Vno(t)

Summing uncorrelated noise voltages and currents, i.e. thermal noise.

EX if two noise sources have uncorrelated voltage of 5 and 10 uVs respectively the total

noise generated is

Vno = {(5E-6)2 + (10E-6)2} = 11.2uV ” This is a Stochastic problem”

77


Filtered Noise - Ideal

Noise

Filtered or band limited white or thermal noise, shot noise (P-N unction carrier flow)

V2no = | A(j)| V2

ni

where A(s) is the filter function.

EX -- V2ni is white and has a root spectral density of 20 nV/Hz. Find the total noise from DC to

100kHz. Assuming a “Brickwall filter” with a gain of 1

𝑣𝑛2 = |𝐴 𝑗 |𝑆𝑣𝑛 𝑓

𝑓2

𝑓1

𝑑𝑓 = 1 20 nV/Hz 2

105

0

𝑑𝑓 = 4x 107(nV)2

Note input noise terms from multiple sources can be combined before or after filtering.

78


Filtered Noise – 1st Order

Noise

If | A(j)| were a 1st Order filter the it would be weighted as follows;

fx = /2 fo where fo = 1/(2 R C)

Repeating the above example for a 1st Order filter

V2no = | A(j)| V2

ni = /2 {20}2 dfi = 2.0 x 107 (nV)2

79


1/f Noise –

Noise

1/f Tangent Principal

Observation - a function proportional to 1/x results in equal power over each decade. For 1/f noise the

noise total noise power doubles ever decade. BW increases by 10 and x.


𝑓2

𝑓1

𝑑𝑓 = 1 1𝑓

10𝑘𝑓

𝑓

𝑑𝑓 = 𝑘Ln f |𝑓10𝑓

= 𝑘 2.3

LN(10kf1)- LN(f) = K LN(10) = k 2.3 for k decades OR veq = (k 2.3)

Never Open the BW any wider than is essential to achieve the desire task to avoid degrading

performance by added noise. This is a matched filter problem.

80


Device Noise –

Noise

Resistors V2R(f) = 4kT R “Thermal”

1K 4.0 nV/Hz @ Rm Temp

Diodes I2d(f) = 2q ID “Shot”

rd = Vt/ nID “ No noise”

BJT I2i(f) = 2q {IB + KIB/f + IC/|(j)|}

V2i(f) = 4kT {rb + 1/gm}

MOS I2i(f) = 4kT { 2/3} gm “shot”

V2i(f) = K/ {WLCoxf} “1/f”

Active MOS device currents can be converted to a equivalent input voltage by dividing by gm2. k

= Boltzmans Constant, q charge of an electron.

V2iT(f) = K/ {WLCoxf} + {4kT (2/3)} /gm MOS example equivalent gate input V2/Hz

81


Why kT/C?

Noise

EX -- V2ni is white. Find the total noise from DC to fo. Assuming a “RC filter”

vin vout

vin vout


𝑓2

𝑓1𝑑𝑓 = 1/|1 +

jf

fo|

105

0𝑑𝑓 =

𝑘𝑇

𝐶

where A(j) = 1/(1 + jf/fo), feff = /2 fo and fo = 1/(2 R C) and k = Boltzmans Constant

𝐯𝐧𝟐 = CkTVno /

Nice toKnow- For a 1 pFd Cap the noise floor is at 64 uV

As a perspective 1V/214 = 61 uV

OBSERVATIONS

In dependent of BW a 1 pFd Cap preserves a 61 uV noise floor. To increase the BW the only

alternative is to decrease Rs, OR inc. gm , i.e. Widen MOS switch size. At the penalty of increased charge

injection error and power consumption. 82


Noise Figure/Factor

Noise

The noise factor (F) of a device specifies how much additional noise the device will contribute to the

noise already beyond that contributed by the equivalent source generator.

The total equivalent input noise voltage

𝑣𝑒𝑞2 = 𝑣𝑛𝑠2 + 𝑣𝑛2 + 𝑖𝑛2𝑅𝑠𝑒𝑞

𝐹 = 𝑣𝑛𝑠2 + 𝑣𝑛2 + 𝑖𝑛2𝑅𝑠𝑒𝑞

𝑣𝑛𝑠2= 1 +

𝑣𝑛2 + 𝑖𝑛2𝑅𝑠𝑒𝑞

𝑣𝑛𝑠2= 1 +

𝑣𝑛2 + 𝑖𝑛2𝑅𝑠𝑒𝑞

4𝑘𝑇𝑅= 𝐹

Noise figure (NF) is the Noise factor converted to dB i.e. NF = 10 log (F) Signal to Noise Ratio F vnsveqSNRSNR Thus,

𝑆𝑁𝑅𝑖 = 𝑅𝑒𝑐𝑖𝑒𝑣𝑒𝑑 𝑃𝑤𝑟

𝑅𝑒𝑐. 𝑛𝑜𝑖𝑠𝑒 𝑃𝑤𝑟=

𝑣𝑠𝑖𝑔2

𝑣𝑛𝑠2

𝑆𝑁𝑅𝑜 = 𝑂𝑢𝑡𝑝𝑢𝑡 𝑠𝑖𝑔.𝑃𝑤𝑟

𝑂𝑢𝑡𝑝𝑢𝑡 𝑛𝑜𝑖𝑠𝑒 𝑃𝑤𝑟=

𝐴2 𝑣𝑠𝑖𝑔2

𝐴2 𝑣𝑖𝑛𝑒𝑞2=

𝑣𝑠𝑖𝑔2

𝑣𝑖𝑛𝑒𝑞2

𝑆𝑁𝑅𝑜𝑆𝑁𝑅𝑖

= 𝑣𝑖𝑛𝑒𝑞2

𝑣𝑛𝑠2

83


Quantization Noise

Noise

10 bit ADC EX - Find the SNR of a sine wave which spans the full scale range of a 10 bit ADC assuming a

perfect ADC (quantization error only) and all other noise sources have been properly managed. VFS =

2.828 V

Quantization SNR = 20 Log (Pwr out)/(Quantization pwr) = 20 Log [{VFS/(22)}/(VFS/2n)]

where n is the number of bits or 10

SNR = 20 Log [{VFS/(22)}/(VFS/{2n (12) }] = 20 n Log (2) + 20 Log ((6)/2)

SNR = 6.02 n +1.76 dB = 61.9 dB

Note All electronics; Buffer amplifiers, Track and Holds, Comprators etc. must preserve this SNR by

being at least 9 to 12 dB down from the quantization noise.

84


Knee frequency fKnee

Noise

Determine fKnee For a MOSFET assuming gate current is 0

V𝑖𝑡𝑕2 =

4 𝑘 𝑇 2

3

𝑔𝑚 Thermal Noise

V𝑖1/𝑓2 =

𝐾𝑓

𝑊𝐿𝐶𝑜𝑥 𝑓 1/f Noise

Setting both noise terms equal and solving for f

·T·k 8·Cox·L

V·KP·3·K

·T·k Cgs·4

gm·K f

2

ffKnee

D

Increase L to reduce fknee!

85


OTA Example

Noise

v𝑖𝑡𝑕2 =

4 𝑘 𝑇 2

3

𝑔𝑚 Thermal Noise

v𝑖1/𝑓2 =

𝐾𝑓


i𝑖𝑡𝑕2 = 4 𝑘 𝑇

2

3 𝑔𝑚 Thermal Noise

i𝑖1/𝑓2 = gm2 𝐾𝑓


M5 a & b

M1 a & b

M3 a & b

VCM

VCM

in1a in1b

in3bin3a

in5bin5a

87


OTA Example

Noise

M5 a & b

M1 a & b

M3 a & b

VCM

VCM

in1a in1b

in3bin3a

in5bin5a

Approach – Independent of transistor mode of operation,

1. Input or Output referred

a. Noise or Current

2. Short Inputs and Output through metal amp meter

3. Transformation voltages currents or currents to voltage

a. io = gm vin

b. vin = io/gm

4. In5 is common mode

a. ss noise is common mode – contribution is operation dependent

i. ss common mode

ii. large signal error contribution

88


OTA Example

Noise

M5 a & b

M1 a & b

M3 a & b

VCM

VCM

in1a in1b

in3bin3a

in5bin5a

Amp meter output noise (Thermal)

i𝑜𝑡𝑕2 = 2in1

2 + 2in22 = 2 4 𝑘 𝑇

2

3 𝑔𝑚1 + 2 4 𝑘 𝑇

2

3 𝑔𝑚2

Input refer divide by gm12

v𝑖𝑡𝑕2 = 2

4 𝑘 𝑇 2

3 𝑔𝑚 1

𝑔𝑚 12 + 2

4 𝑘 𝑇 2

3 𝑔𝑚 3

𝑔𝑚 12 =

16 𝑘 𝑇

3𝑔𝑚 1 1 +

𝑔𝑚 3

𝑔𝑚 1 without I tail

v𝑖𝑡𝑕2 =

16 𝑘 𝑇

3𝑔𝑚 1 1 +

𝑔𝑚 3

𝑔𝑚 1+

𝑔𝑚 5

𝑔𝑚 1 with I tail Slewing

v𝑖1/𝑓2 = 2

𝐾𝑓𝑃 𝑔𝑚12

𝑊𝐿 𝑑𝑝𝐶𝑜𝑥 𝑔𝑚12

+ 2 𝐾𝑓𝑁 𝑔𝑚3

2

𝑊𝐿 3𝐶𝑜𝑥 𝑔𝑚12

+ 2 𝐾𝑓𝑃𝑔𝑚5

2


=2𝐾𝑓𝑃

𝑊𝐿 𝑑𝑝𝐶𝑜𝑥 1 +

𝐾𝑓𝑁 𝑊𝐿 𝑑𝑝

𝐾𝑓𝑃 𝑊𝐿 3 𝑔𝑚3

𝑔𝑚1

2

+ 𝐾𝑓𝑁 𝑊𝐿 𝑑𝑝


𝑔𝑚1

2

Observation

1/f increase Area as feasiable.

Increase gm1 as much as practical – little option in subthreshold gm1 = gm3 = gm5/2.

v𝑖1/𝑓2 = 2

𝐾𝑓𝑃 𝑊𝐿 𝑑𝑝𝐶𝑜𝑥

+ 2 𝐾𝑓𝑁

𝑊𝐿 3𝐶𝑜𝑥+ 2

2𝐾𝑓𝑃 𝑊𝐿 3𝐶𝑜𝑥

=2𝐾𝑓𝑃



𝐾𝑓𝑃 𝑊𝐿 3 + 4


𝐾𝑓𝑃 𝑊𝐿 5

89


OTA Example

Noise

M5 a & b

M1 a & b

M3 a & b

VCM

VCM

in1a in1b

in3bin3a

in5bin5a When does tail noise matter & how?

90


Cascode Devices

Noise

Cascode (common gate)

ALL Cascode Error currents OR gate voltage are reduced by 1/ !!!

Cascode transistors do not contribute to output or input effective noise!

In fact any noise at the gate of the cascade maybe ignored to a first order!

Decreasing PSRR & CMRR errors!

ierr2 = (verr g3)

2+ 8/3 kT gm3

inoise2 = 8/3 kTg3

2/gmcc + 8/3 kT gm3

inoise2 = 8/3 kT gm3[1 + g3/[gmcc µ3]

inoise2 8/3 kT gm3

verr

g3in3

verr2 = 8/3 kT/gmcc

Mcc

91


Fully Differential Cascode

Noise

Observe that cascading of M3 and M4 implies only M1, M3, and M4

and possible M5 contribute noise.

M5 a & b

M1 a & b

M3 a & b

VCM

VCM

in1a in1b

in5bin5a

in3ain3b

VB4

M4 a & b

in4bin4a

VB3

VB2

VB1 VB1

92


Fully Differential Cascode

Noise

Observe that

cascading of M3 and

M4 implies only M1,

M3, and M4 and

possible M5

contribute noise.

M5 a & b

M1 a & b

M3 a & b

VCM

VCM

in1a in1b

in5bin5a

in3ain3b

VB4

M4 a & b

in4bin4a

VB3

VB2

VB1 VB1

v𝑖𝑡𝑕2 = 2

4 𝑘 𝑇 2

3 𝑔𝑚 1

𝑔𝑚 12 + 2

4 𝑘 𝑇 2

3 𝑔𝑚 3

𝑔𝑚 12 + 2

4 𝑘 𝑇 2

3 𝑔𝑚 4

𝑔𝑚 12 =

16 𝑘 𝑇

3𝑔𝑚 1 1 +

𝑔𝑚 3

𝑔𝑚 1+

𝑔𝑚 4

𝑔𝑚 1

v𝑖𝑡𝑕2 =

16 𝑘 𝑇

3𝑔𝑚 1 1 +

𝑔𝑚 3

𝑔𝑚 1+

𝑔𝑚 4

𝑔𝑚 1+

𝑔𝑚 5

𝑔𝑚 1 with I tail Slewing

v𝑖1/𝑓2 = 2

𝐾𝑓𝑃 𝑔𝑚12

𝑊𝐿 𝑑𝑝𝐶𝑜𝑥 𝑔𝑚12

+ 2 𝐾𝑓𝑁 𝑔𝑚3

2


+ 2 𝐾𝑓𝑃𝑔𝑚4

2


=2𝐾𝑓𝑃




𝑔𝑚1

2

+ 𝑊𝐿 𝑑𝑝 𝑊𝐿 4

𝑔𝑚4

𝑔𝑚1

2

93


Fully Differential Cascode - Observations

Noise

1. Cascode transistors do not contribute to output or input effective noise!

2. Cascode transistors set or limit BW indirectly dictating L or LfTA L1.

3. Select ALL rail side devices (W/L)rail as large as feasible! i.e. 2 to 3X longer

than LfTA.

94



Noise

1. Increasing Lrail to 3 LfTA and Wrail to 3 WfTA or rail side area by 9 and gm1 gm4

2 gm3.

v𝑖1/𝑓2 <≈

2𝐾𝑓𝑃 𝑊𝐿 𝑑𝑝𝐶𝑜𝑥

1 +𝐾𝑓𝑁

𝐾𝑓𝑃 1

9 𝑔𝑚3

𝑔𝑚1

2

+ 1

9 𝑔𝑚

4

𝑔𝑚1

2

≈2𝐾𝑓𝑃


𝐾𝑓𝑁

𝐾𝑓𝑃 1

9 𝑔𝑚3

𝑔𝑚1

2

2. Vos is an err much very similar to 1/f & by inspection

v𝑖𝑜𝑠2 =

𝐴𝑉𝑇𝑃2

𝑊𝐿 𝑑𝑝

𝑔𝑚12

𝑔𝑚12

+𝐴𝑉𝑇𝑁

2

𝑊𝐿 3 𝑔𝑚3

2

𝑔𝑚12

+𝐴𝑉𝑇𝑃

2

𝑊𝐿 4 𝑔𝑚4

2

𝑔𝑚12

=𝐴𝑉𝑇𝑃

2

𝑊𝐿 𝑑𝑝 1 +

𝐴𝑉𝑇𝑁2 𝑊𝐿 𝑑𝑝

𝐴𝑉𝑇𝑃2 𝑊𝐿 3

𝑔𝑚3

𝑔𝑚1

2

+ 𝑊𝐿 𝑑𝑝 𝑊𝐿 4

𝑔𝑚4

𝑔𝑚1

2

95



Noise

Again observing that rail side device are increased by 9X and assuming gm1

gm4 2 gm3.

v𝑖𝑜𝑠2 <≈

𝐴𝑉𝑇𝑃2


𝐴𝑉𝑇𝑁2

𝐴𝑉𝑇𝑃2

1

9 𝑔𝑚3

𝑔𝑚1

2

+ 1

9 𝑔𝑚4

𝑔𝑚1

2

≈𝐴𝑉𝑇𝑃

2


𝐴𝑉𝑇𝑁2

𝐴𝑉𝑇𝑃2

1

9 𝑔𝑚3

𝑔𝑚1

2

Note that the fully differential OTA neglects both noise and offset errors created by the Common Mode

Feedback (CMFB) circuit.

96


Fully Differential Cascode with 2nd Stage

Opamp Compensation

VB3

VB4

VB1

VB2

VB3

VB4

VB1

VB2

VB1

VopVom

VB1

B

VCMo VCMREF

Vip Vim

VB1

Cc Cc

CcCcRz Rz

Vop Vom

VCMo

A

AB

IDP

IP

IN

Fro

m G

lob

al B

ias

VB1

VB2

VB3

VB4

VB3

WLP/LLP

WLN/LLN

WLP/LLP

WLN/LLN

WLN/LLN

VB1

M1DAb

M1DAa

ICM

tail

WLN/LLN

CM AmplifierVB3

VB3

Optional split

transistor

Interdigitated

Transistors

Cc Cc

IP

WLP/LLP

IDP

IN

M3a M3b

M4a M4b

Stage 1 – folded cascode

Avol 2 or greater when boosting is applied.

GBP = gm1/CL CL = Cin stage 2

Stage 2 – common source

Avol

GBP = gm2/CL CL = effective load with feedback.

Signal swing VDD-6UT 97


Fully Differential Cascode with 2nd Stage

Opamp Compensation

VB3

VB4

VB1

VB2

VB3

VB4

VB1

VB2

VB1

VopVom

VB1

B

VCMo VCMREF

Vip Vim

VB1

Cc Cc

CcCcRz Rz

Vop Vom

VCMo

A

AB

IDP

IP

IN

Fro

m G

lob

al B

ias

VB1

VB2

VB3

VB4

VB3

WLP/LLP

WLN/LLN

WLP/LLP

WLN/LLN

WLN/LLN

VB1

M1DAb

M1DAa

ICM

tail

WLN/LLN

CM AmplifierVB3

VB3

Optional split

transistor

Interdigitated

Transistors

Cc Cc

IP

WLP/LLP

IDP

IN

M3a M3b

M4a M4b

Compensation options

Miller

Pole-zero cancelation

Indirect

Split transistor

Differential pair

Rail side current 98


Opamp Compensation

An Introduction to Miller Compensation

g2 CL

Vout

gm1.Vin g1 C1

CC

gm2.V1

V1

For node V1:

gm1Vin + V1𝑔1+V1s C1+ 𝑉1 − 𝑉𝑂𝑈𝑇 sCC=0 (1.1)

For node VOUT:

gm2V1 + VOUT𝑔2 + V2sCL + 𝑉𝑂𝑈𝑇 − 𝑉1 sCC=0 (1.2)

The transfer function VOUT(s)

Vin(S) can be expressed as [33]:

Vout(s)

Vin(s)=gm1r1gm2r2

1-jffz

1-jff1 1-j

ff2

1

22

1-jffz

1-jff1 1-j

ff2

(1.3)

99


Opamp Compensation

An Introduction to Miller Compensation

g2 CL

Vout

gm1.Vin g1 C1

CC

gm2.V1

V1

PM=180 − ATAN𝑓𝑢𝑓𝑑𝑜𝑚

− ATAN𝑓𝑢𝑓𝑧− ATAN

𝑓𝑢𝑓𝑛𝑜𝑛𝑑𝑜𝑚

(1.1)

For fz = fnondom = 2fu

PM=180 − 90− ATAN1

2− ATAN

2

2= 47 (1.1)

Table 1.1 Pole Zero locations of a two stage miller OTA

Parameter Value

DC gain 1

22

RHP Zero gm2

CC

GBP gm1

CC

Non- dominant pole gm2CC

CCCg2+CCCL+Cg2CL

gm2

CL

Dominant Pole g1

2CC

f1

GBPf2fZ

0°

-90°

-180°

f

f

dB

Ma

gn

itu

de

Ph

ase

100


Opamp Compensation

Indirect Compensation – some possible options

VDD VDD

VDD

Vout = V2

Vbias4

Vm

M2

2CC

VP

1

MC1

M1aM1b

Vbias2

A

MC2

Mi1 Mi2

Mi3Mi4

VDD VDD

VDD

Vout = V2

Vbias4

Vm

M2

2

CC

VP

1

MC1

M1aM1b

Vbias2

A

MC2

Mi1 Mi2

Mi3Mi4

VDD

VB3

VDD

VDD

VB1

VB2

VSS

VDD

vop+

vmM2a

CC

vP

MC1

M1aM1b

Mi1Mi2

MC2CC

M2b

MC3MC4

Mi3Mi4

MiTMi5Mi6

vom

vxp

v1av1b

vxn

VDD

VB3

VDD

VDD

VB1

VB2

VSS

VDD

V2+

VmM2a

CC

VP

MC1

M1aM1b

Mi1Mi2

MC2CC

M2b

MC3MC4

Mi3Mi4

MiTMi5Mi6

V2-

Vxp

V1aV1b

Vxn

101


Cxpvxp

gi

gmdf.vin

gmpvxpgcc

v1

Cg2

gmnvxn gcc

vxn

CC

giCxn

gm2v1 g2 CL

vo

vxp

Opamp Compensation

Indirect Compensation –

The nodal equations can be written as:

Vo:

v0g2+ v0sCL+ gm2v1+ v0-vxn sCC=0 (1.1)

Vxn:

vxnsCxn+ vxngi + vxn-v0 sCC + vxn-v1 gcc+ gmnvxn = 0 (1.2)

V1:

v1-vxn gcc- gmnvxn+ v1sCg2+ v1-vxp gcc- gmpvxp = 0 (1.3)

Vxp:

vxps Cxp+ vxpgi - gmdfVin+ vxp-v1 gcc+ gmpvxp = 0 (1.4)

102


Opamp Compensation


Solving for the transfer function VOUT(s)

Vin(S) , the prominent poles and zeros are summarized below

Table 1.1 Pole and zero locations for current injected at different nodes.

Parameter Value

LHP Zero gm

CC+Cxn ≈

gm

CC

GBP 𝑔𝑚𝑑𝑓

CC

ω dominant

2gm

CCμ2μ2

ωnon near

gm2CC

Cg2 CC+CL =

𝑇𝐴2CC

CC+CL

ωnon distant CLs2

gmωTA+ CC+CL s

CCωTA+1=0

ωTA

gm

CxnKr

103


Opamp Compensation


Examining

CLs2

gmωTA+ CC+CL s

CCωTA+1=0 (1.1)

where TA = gm/Cxp. Comparing non to the greater of the residual poles there are three cases of

interest.

pole CL<<Cc CL Cc CL>> Cc 𝑇𝐴2CC

CC+CL

𝑇𝐴2 𝑇𝐴2

2

𝑇𝐴2CC

CL

CLs2

gmωTA+ CC+CL s

CCωTA+1=0

CLs2

gmωTA+

s

ωTA+1=0

CCs2

gmωTA+

2 s

ωTA+1=0

CLs2

gmωTA+ CL s

CCωTA+1=0

Pole Comment ωnon = gm/CL ωnon = 2 gm/CC ωnon = gm/CC

Summarizing

𝑛𝑜𝑛 1=ωTA2 · 𝐶𝑐

(𝐶𝐿 + 𝐶𝑐); 𝑛𝑜𝑛 2=

𝑔𝑚 · (𝐶𝐿 + 𝐶𝑐)

(𝐶𝐿 𝐶𝑐)

𝑇𝐴2≪gm·(𝐶𝐿 + 𝐶𝑐)2

(CL·𝐶𝑐2); 𝑇𝑕𝑒𝑛 𝑛𝑜𝑛 1=

𝑔𝑚 · (𝐶𝐿 + 𝐶𝑐)

(𝐶𝐿 𝐶𝑐)

PM= 180 − 90 + ATAN𝑓𝑢

𝑓𝑧− ATAN

𝑓𝑢

𝑓𝑛𝑜𝑛𝑑𝑜𝑚 ; for fz = 2 fu

PM= 180 − 63.4− ATAN𝑓𝑢

𝑓𝑛𝑜𝑛𝑑𝑜𝑚

(1.1)

104


Cxpvxp

gi

gmpvxpgcc

v1

Cg2

gmnvxn gcc

vxn

CC

gi Cxngm2v1 g2 CL

vo

gmdp.vin

CC

Opamp Compensation

Indirect Compensation – with feedback at same node as ff

Since the main small signal current flows into the node VXN, we can ignore node VXP in the nodal analysis

by assuming the P side is near idea. Note this removes an TAp pole. The nodal equations for the above

model are written as:

Vo:

v0g2+ v0sCL+ gm2v1 + v0-vxn sCC = 0 (1.1)

Vxn:

vxnsCxn+ vxngi+ vxn-v0 sCC + vxn-v1 gcc+ gmnvxn- gmdfvin = 0 (1.2)

V1:

v1-vxn gcc- gmnvxn+ v1sCg2 = 0 (1.3)

105


Opamp Compensation

Indirect Compensation – with feedback at same node as ff

Cxpvxp

gi

gmpvxpgcc

v1

Cg2

gmnvxn gcc

vxn

CC

gi Cxngm2v1 g2 CL

vo

gmdf.vin

Figure 1.1 Small signal model of OTA with compensation current injection at same node as input

transconductance.

Table 1.1 Pole and zero locations for current injected at same nodes

Parameter Value

Zeros ≈ ±

gm.gm2

CCCg2

ω dominant gm

CCμ2𝜇2

GBP 𝑔𝑚𝑑𝑓

CC

ωnon2 gm CC+CL

CcCL= 𝐺𝐵𝑃

𝑔𝑚𝑑𝑝

𝑔𝑚

CC+CL

CL

ωnon1 gm2CC

Cg2 CC+CL =

𝑇𝐴2CC

CC+CL

106


Opamp Compensation

Indirect Compensation – with feedback at opposite nodes

VB3

VB4

VB1

VB2

VB3

VB4

VB1

VB2

VB1

VopVom

VB1

B

VCMo VCMREF

Vip Vim

VB1

Cc Cc

CcCcRz Rz

Vop Vom

VCMo

A

AB

IDP

IP

IN

Fro

m G

lob

al B

ias

VB1

VB2

VB3

VB4

VB3

WLP/LLP

WLN/LLN

WLP/LLP

WLN/LLN

WLN/LLN

VB1

M1DAb

M1DAa

ICM

tail

WLN/LLN

CM AmplifierVB3

VB3

Optional split

transistor

Interdigitated

Transistors

Cc Cc

IP

WLP/LLP

IDP

IN

M3a M3b

M4a M4b

• Pole-zero

• Indirect

• Split indirect PMOS I

• Split indirect differential pair

107


Opamp Compensation

Compensation of Fully Differential

Cxpvxp

gi

gmpvxpgcc

v1

Cg2

gmnvxn gcc

vxn

CC

gi Cxngm2v1 g2 CL

vo

gmdp.vin

CC

The nodal equations for the above p-z model can be written as:

vo:

gm2·vo1 + vo·(g2 + s·CL + s·Cc) - vx·s·Cc (1.1)

vpz:

(vx - vo)·s·Cc + (vx - vo1)·Gz (1.2)

v1:

(vo1 - vs)·g - gm·vs + (vo1 - vx)·Gz + vo1·s·Cg2 (1.3)

vxn:

- gmdp·vgi + vs·(2·g + gm) + vs·s·Cg - vo1·g (1.4)

Note the vxp will be assume to be ideal. Solving for the transfer function VOUT(s)

Vin(S) ,

Parameter Value

LHP Zero Gz gm

𝐶𝑐 · (𝐺𝑧 − 𝑔𝑚2)

GBP

gmdp

CC

ω dominant

2gm

CCμ2μ2

ωnon near gm2

CL

ωnon1 distant gm

Cxn= ωTA

ωTA2 distant

gm2

Cg2= ωTA2

108


Opamp Compensation

Compensation of Fully Differential

Cxpvxp

gi

gmpvxpgcc

v1

Cg2

gmnvxn gcc

vxn

CC

gi Cxngm2v1 g2 CL

vo

gmdp.vin

CC

Parameter Value

LHP Zero

GBP

ω dominant

ωnon near

ωnon1 distant

ωTA2 distant

The drawback to p-z compensation is the

added power associated with bias circuit

for the MOS Rz that must track gm2.

109


cmos fet introduction

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