cmos integrated circuits

7/31/2019 CMOS Integrated Circuits

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CMOS Digital

Integrated Circuits

Designing

CombinationalLogic Circuits

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Contents

Combinational vs. Sequential Circuits

Static CMOS Logic

Dynamic CMOS Logic Issues in Dynamic Design

Conclusion

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Combinational vs. Sequential Circuits

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Combinational Sequential

Output = f(In) Output = f(In, Previous In)

CombinationalLogic

Circuit

OutIn

CombinationalLogic

Circuit

OutIn

State

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Designing Combinational

Logic Circuits

There are two methods to design

combinational logic circuits

Static CMOS Logic

Dynamic CMOS Logic

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Static CMOS Logic

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At every point in time (except during the switchingtransients) each gate output is connected to eitherVDDorVssvia a low-resistive path.

The outputs of the gates assumeat all timesthevalueof the Boolean function, implemented by the circuit(ignoring, once again, the transient effects duringswitching periods).

This is in contrast to the dynamic circuit class, whichrelies on temporary storage of signal values on thecapacitance of high impedance circuit nodes.

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Static CMOS Logic

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VDD

F(In1,In2,InN)

In1

In2

InN

In1

In2

InN

PUN

PDN

PMOS only

NMOS only

PUN and PDN are dual logic networks

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NMOS Transistors

in Series/Parallel Connection

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Transistors can be thought as a switch controlled by its gate signal

NMOS switch closes when switch control input is high

X Y

A B

Y = X if A and B

XY

A

B Y = X if A OR B

NMOS Transistors pass a strong 0 but a weak 1

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PMOS Transistors

in Series/Parallel Connection

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X Y

A B

Y = X if A AND B = A + B

X Y

A

B Y = X if A OR B = AB

PMOS Transistors pass a strong 1 but a weak 0

PMOS switch closes when switch control input is low

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Example Gate: NAND

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Example Gate: NOR

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Complex CMOS Gate

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OUT = D + A (B + C)

D

A

B C

D

A

B

C

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Properties of Complementary CMOS Gates

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High noise margins:VOH and VOLare at VDDand GND, respectively.

No static power consumption:There never exists a direct path between VDD andVSS(GND) in steady-state mode.

Comparable rise and fall times:(under appropriate sizing conditions)

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Dynamic CMOS Logic

In static circuits at every point in time (except whenswitching) the output is connected to either GND orVDD via a low resistance path.

fan-in ofn requires 2n (n N-type + n P-type) devices

Dynamic circuits rely on the temporary storage ofsignal values on the capacitance of high impedance

nodes. requires on n + 2 (n+1 N-type + 1 P-type) transistors

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Dynamic CMOS Logic Gate

In dynamic CMOS logic a single clock

can be used to accomplish both thepre-charge and evaluation operations

When is low, PMOS pre-charge

transistor Mp charges Vout to Vdd,

since it remains in its linear region

during final pre-charge

During this time the logic inputs A1

B2 are active; however, since Me is off,

no charge will be lost from Vout

When goes high again, Mp is turned

off and the NMOS evaluate transistor

Me is turned on, allowing for Vout to be

selectively discharged to GND

depending on the logic inputs

If A1 B2 inputs are such that a

conducting path exists between Vout

and Me, then Vout will discharge to 0

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Dynamic CMOS Logic Circuits Dynamic CMOS Logic circuits require a

clock to precharge the output node

and then to pull down the logic tree(assuming the logic inputs provide apath for current to flow) Precharge Phase: clock is down

turning on the P precharge transistor;N pull-down transistor is off. Outputcapacitance CN charges to Vdd.

Evaluation Phase: clock goes highturning on the N pull down transistorand turning off the P prechargetransistor. If logic inputs are such thatneg Z is true, then output capacitanceCN discharges to ground.

No dc current flows during either the

precharge or the evaluate phase. Power is dynamic and is given by

P = CN Vdd2 f where CN represents an

equivalent total capacitance on theoutput, f = clock frequency, =logicrepetition rate

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Cascading Problem in Dynamic CMOS Logic

If several stages of the previous CMOS dynamic logic circuit are cascaded togetherusing the same clock , a problem in evaluation involving a built-in raceconditionwill exist

Consider the two stage dynamic logic circuit below: During pre-charge, both Vout1 and Vout2 are pre-charged to Vdd

When goes high to begin evaluate, all inputs at stage 1 require some finite time to resolve, butduring this time charge may erroneously be discharged from Vout2

e.g. assume that eventually the 1st stage NMOS logic tree conducts and fully discharges Vout1,but since all the inputs to the N-tree all not immediately resolved, it takes some time for the N-tree to finally discharge Vout1 to GND.

If, during this time delay, the 2nd stage has the input condition shown with bottom NMOStransistor gate at a logic 1, then Vout2 will start to fall and discharge its load capacitance untilVout1 finally evaluates and turns off the top series NMOS transistor in stage 2

The result is an error in the output of the 2nd stage Vout2

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Cascaded Dynamic CMOS Logic Gates: Evaluate Problem

With simple cascading of dynamicCMOS logic stages, a problem arisesin the evaluate cycle:

The pre-charged high voltage onNode N2 in stage 2 may beinadvertently (partially) discharged bylogic inputs to stage 2 which have notyet reached final correct (low) values

from the stage 1 evaluationoperation.

Can not simply cascade dynamicCMOS logic gates without preventingunwanted bleeding of charge frompre-charged nodes

Possible Solutions: two phase clocks

use of inverters to create DominoLogic

NP Domino Logic

Zipper/NORA logic

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CMOS Domino Logic

The problem with faulty discharge ofprecharged nodes in CMOS dynamic

logic circuits can be solved by placingan inverter in series with the output ofeach gate

All inputs to N logic blocks (which arederived from inverted outputs ofprevious stages) therefore will be at

zero volts during precharge and willremain at zero until the evaluationstage has logic inputs to discharge theprecharged node PZ.

This circuit approach avoids the raceproblem of vanilla cascaded dynamicCMOS

However, all circuits only provide non-inverted outputs

Charge sharing between dynamic nodeand intermediate node of NMOS logicblock during the evaluation phase.

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Issues in Dynamic Design 2: Charge

Sharing

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CL

Clk

Clk

CA

CB

B=0

A

Out

Mp

Me

Charge stored originally on CL is

redistributed (shared) over CL and CA

leading to reduced robustness

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Solution to Charge Sharing

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CL

Clk

Clk

Me

Mp

A

B

Out

Mkp

solution to charge sharing is to add weak PMOS, which forces a high output level

unless there is strong pull-down path between output and ground.

Keeper

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Properties of Dynamic Gates

Logic function is implemented by the PDN only number of transistors is N + 2 (versus 2N for static complementary CMOS)

Full swing outputs (VOL = GND and VOH = VDD)

Non-ratioed - sizing of the devices does not affect thelogic levels

Faster switching speeds reduced load capacitance due to lower input capacitance (Cin)

reduced load capacitance due to smaller output loading (Cout)

no Isc, so all the current provided by PDN goes into discharging CL

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Static Vs Dynamic Logic

Parameters Static Logic Dynamic Logic

Number of components 2N N+2

Behavior of logic stable unstable

Reliability Results high less

Results No such Problems Charge Sharing, Erroneousresults

SAP Less P A reduced

S increased

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Assignment

In Dynamic CMOS logic only NMOS network

has been used and has less delay as compare

to static CMOS logic. How?

Implement function Not ((A.B)+C) in static and

dynamic logic style.

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Thank You

cmos integrated circuits

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