cmos logic circuit design - hiroshima universityh19-7-13).pdf2019/07/13 · buffer circuit (see...

Mattausch, CMOS Design, H19/7/13 1

Interconnects• Interconnects in CMOS Circuits (Effects, Length Distribution)• Capacitive Interconnect Contributions

– Wire, Diffusion and Gate Capacitance– Capacitive Switching Delay– Inter-Wire Capacitances and Cross-Talk

• Resistive Interconnect Contributions– Sheet and Contact Resistance– RC Switching Delay

• Inductive Interconnect Contributions– Types of Interconnect Inductances– Voltage-Drop Effects

CMOS Logic Circuit Designhttp://www.rcns.hiroshima-u.ac.jp

Link（リンク）: センター教官講義ノートの下 CMOS論理回路設計


Main Interconnect-Effects on CMOS Circuits

Reduced Performance

• Capacitance• Resistance• Inductance

• Capacitive and Inductive Coupling of Signal Lines

• Electromigration (Ion Transport by Currents)

Reduced Reliability

Interconnects reduce the ideal performance/reliability of CMOS circuits. Design task is to minimizes these reductions.


Local and Global Interconnects

In CMOS logic circuits 2 types of interconnects (local, global) exist. They have different properties and requirements.

Input/Output

Control

Memory

Datapath

GlobalInterconnects

Local InterconnectExample

Global InterconnectExample

VDD

VSS En

In Out

LocalInterconnect


Typical Interconnect-Length Distribution

The interconnect-length distribution in CMOS circuits has always 2 peaks resulting from local and global interconnects.

Chip Area: AC

Empirical Findings:

• Two Interconnect-LengthMaxima at

• Average Length

Clocal A0.1L ⋅=

Lglobal = 0.5 ⋅ AC

Laverage = 13 ⋅ AC


Capacitive Interconnect Contributions

- Wire, Diffusion and Gate Capacitance- Capacitive Switching Delay- Inter-Wire Capacitance and Cross-Talk


Capacitance-Types in an Interconnect

Basic interconnect capacitances consist of diffusion (sender), wire (physical connection) and gate (receivers) components.

VDD

VSS

In

VDD

VSS VDD

VSS

DiffusionCapacitance

WireCapacitance

GateCapacitance


Parallel-Plate and Fringing Capacitance of Wires

In CMOS circuits 2 wire-capacitance components, the parallel plate and the fringing capacitance, must be considered.

Cwire = ε0 ⋅ L⋅W

H+ 0.77 +1.06 ⋅

W

H

0.25

+1.06 ⋅T

H

0.5

Parallel-PlateCapacitance CPP

WireInsulator

Cpp

FringingCapacitance CF

FringingField

W

Substrate

H

T

Empirical Wire-Capacitance FormulaCPP

CFLW

TH


Effect of Scaling Down the Wire-Width

In recent CMOS technologies the fringing capacitance CF of wires becomes larger than the parallel-plate capacitance CPP.

CF

When scaling down the wire width W, the wire height T is kept

as large as possible tokeep the

wire-resistance small.

The relative magnitude of the fringing capacitance CF

becomes large.


Diffusion Capacitance in Interconnects

The diffusion-capacitance contribution in interconnects comes mainly from the drain areas of the senders.

Cjp = periphery capacitance

∼ 4 ·10-4pF/µm

Cja = junction capacitance

∼ 5 ·10-4pF/µm2

cd = c ja ⋅(a⋅ b) + Cjp⋅ (2a+ 2 b)

Diffusion capacitancesin the transistor

Components of thecapacitance of a diffusion region

Calculation of the diffusion capacitance

Voltage dependence of the diffusion capacitance

c j ≈ cj 0⋅ 1−Vj

0.6

−m


Gate Capacitance in Interconnects

Gate capacitances, given by gate area and oxide thickness, are dominant in local as well as many global interconnects.

Overview of Capacitive Components in a MOSFET

3 gate capacitancecomponents

Cg = Cgb + Cgs + Cgd

Gate-Capacitance Equation

Approximations in differentMOSFET operating regions

Cg ≈ε0 ⋅ A

tox

A = Gate- Area

off linear saturationregion

Cgb

Cgs

Cgd

0

0

ε0 ⋅A2 ⋅ t ox

ε0 ⋅A2 ⋅ t ox

2 ⋅ ε0 ⋅ A

3 ⋅ tox

0 0

~0

Cgε0 ⋅A

tox

ε0 ⋅Atox

2 ⋅ ε0 ⋅ A

3 ⋅ tox

→0.9 ⋅ε0 ⋅ A

tox

ε0 ⋅Atox

(short channel)


Capacitive Interconnect Contributions

- Wire, Diffusion and Gate Capacitance- Capacitive Switching Delay- Inter-Wire Capacitance and Cross-Talk


Capacitive Switching Delay

Capacitive switching delays are proportional to Cload. Buffer circuits achieve small td for large Cload and keep Cin small.

Single inverter or gate

Delay depends ondriving capability of inverter

Problem for large Cload:How to increase the driving

capability β without increasing thegate capacitance for Vin ?

Vin VoutCload(=Cwire+Cg+Cd)

t d,av ≈tdr+ tdf

2

≈kr + kf

4 ⋅ βr + βf( ) ⋅Cload

VDD

kf and kr depend on fabrication technology (~2-4)(See OHP 13 of lecture on “Static and Dynamic CMOS Design” !)

Buffer Circuit(See OHPs 5,6 of lecture on

“Special Purpose Digital Circuits”)

Vin

VSS

Cload

Vout

I1 I2 I2N I2N+1

A 0 Wp

Wn

A1 Wp

Wn

A 2N −1 Wp

Wn

A 2N Wp

Wn

I3

A 2 Wp

Wn

A =Cload

Cin1

1

2N +1

N = int 12 ln

Cload

Cin1

− 1

2


Inter-Wire Capacitances in Multi-Layer Systems

In recent small-size CMOS technologies the line-to-line capacitance C22 becomes increasingly important.

Wire-capacitance componentsin a multi-layer system Wire capacitance in layer 2:

C2 = C21 + C23 + C22

Wire

Layer 3

Layer 2

Layer 1

C22C23

C21 D W

H

T

T

C22 = Line-to-LineCapacitance

C21, C23 = CrossoverCapacitancesFor design rules <0.5µm the

ratio H/D becomes large.

C22 becomes large !


Size of the Line-to-Line Capacitance

Although C21 decreases with smaller design rules, the total wire capacitance increases due to the strong increase of C22.

T and H are fixed !D=W are varied !

For W < 1.75H the line-to-line capacitance C22begins to dominate over the line-to-ground capacitance C21.

W=1.75H


Resistive Interconnect Contributions

- Sheet and Contact Resistance- RC Switching Delay


Sheet Resistance of a Wire Interconnect

The sheet resistance allows wire-resistance calculation by counting the number of squares (L=W) contained in the wire.

The thickness T of a wire isnormally a confidential

fabrication-process information.

ρ = Specific ResistanceT = ThicknessL = LengthW = Width

W

LT

R =ρT

⋅L

W

Definition of T-independent parameters is necessary.

Introduction of thesheet resistance R = ρ/T.(dimension is Ω/square)


Contact Resistance, Typical Resistance Values

The decreasing contact resistance in advanced technologies can be compensated by increasing the number of contacts.

n-well

p-substrate

n+n+ p+

W

Flat Isolation Surface by CMP(CMP=chemical mechanical polishing)

Contact betweenInterconnect Layers

As technology design rules are scaled down, contact size

decreases and contact resistance (~0.25Ω) increases.

Material

SheetResistanceΩ/square

Metal ~0.07

Polysilicon ~20

SilicidedPolysilicon

~3

Diffusion ~25

n-Well ~2000

SilicidedDiffusion

~4


RC Switching Delay

The lumped RC-model gives too pessimistic results for the delay time of an interconnect wire.

r and c are resistance and capacitance per unit length.

Rwire

Cwire

Vin Vout

r

c

Vout

c

r

c

r

c

r

Vin

Lumped RC-Delay Model.

Distributed RC-Delay Model.

Comparison of lumped RC-delay model and distributed RC-delay model

tr, tf

Lumped Model Distributed Model

2.2·Rwire·Cwire 0.9·Rwire·Cwire


Inductive Interconnect Contributions

- Types of Interconnect Inductances- Voltage-Drop Effects


Inductance of an 0n-Chip Wire Interconnect

The inductance of interconnect wires on a CMOS chip can be neglected in most cases.

µ = Permeability, T = ThicknessL = Length, W = Width, H = HeightUnits = Henry per Unit Length

Lwire =µ

2π⋅ ln

8H

W+

W

4H

T is assumed to be negligibly small and L=1 is assumed to be

one length unit.

Interconnects in a CMOS chip have a typical inductance of

Lwire ~ 2·10-11 Henry/mm .

WLT

H Wire


Inductance of a Wire Interconnect to the Package

The inductance of interconnect wires to the CMOS package is the practically most important inductance in IC technology.

µ = Permeability, D = Diameter of Bond Wire, H = Height of Bond Wire

above GroundUnits = Henry per Unit Length

Lbond =µ

2π⋅ ln

4 H

D

Typical size of bond-wire inductance is ~10-8 Henry.

Bond wires to the package can induce supply-voltage drops on the chip during output-buffer switching.


Origin of Voltage Drop Effects

Inductances of buffer interconnects to power supplies (VDD, VSS) can lead to substantial voltage drops during switching.

Equation for the voltage drop.

The inductive voltage drop is proportional to the inductance and to the time-derivative of the current.

dt

di(t)LDrop(VDD) Bond⋅=


Simulation Example of Voltage Drop Effects

Simulation parameters.

• The voltage drop during switching of a single buffer can already reach 10% of the supply voltage.• The magnitude of the voltage drop can be reduced by slower switching speed.

Switching simulation of a buffer.

Cload = 20pFVDD = 5V

Lbond = 10-8 Henry.

voltage-drop at inductancewith tfall = 0.5 nsec

Vin

t (nsec)

cmos logic circuit design - hiroshima universityh19-7-13).pdf2019/07/13 · buffer circuit (see...

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