cmos logic - mayagüezmtoledo/4207/s2011/c3_4.pdf · 2011. 2. 17. · example: cmos 0.25μm process...
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CMOS LogicINEL 4207 - Digital Electronics - Spring 2011
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2011 by Oxford University Press, Inc.
Figure 14.17 The CMOS inverter.
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2011 by Oxford University Press, Inc.
Figure 14.18
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2011 by Oxford University Press, Inc.
Figure 14.19
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2011 by Oxford University Press, Inc.
Figure 14.20 The voltage-transfer characteristic of the CMOS inverter when QN and QP are matched.
Qn and Qp are matched: kn = kp
Use Vtn = −Vtp = Vt.
VIH
Qp is in saturation, Qn is in triode region.
iDp =kp
2(VDD − vi − Vt)
2
iDn =kn
22 (vi − Vt) vO − v2
O
(VDD − vi − Vt)2 = 2 (vi − Vt) vO − v2O
−2(VDD − vi − Vt) = 2vO + 2 (vi − Vt)∂vO
∂vi− 2vO
∂vO
∂vi
vO = VIH −VDD
2
(VDD − VIH − Vt)2 = 2 (VIH − Vt)
VIH −VDD
2
−
VIH −
VDD
2
2
VIH =18
(5VDD − 2Vt)
Use symmetry on VTC
VIH −VDD
2=
VDD
2− VIL
VIL =1
8(3VDD + 2Vt)
NMH =1
8(3VDD + 2Vt) = NML
If Qn and Qp are not matched: r =
kn/kp
VM
kp
2(VDD − VM + Vtp)
2 =kn
2(VM − Vtn)
2
VDD − VM + Vtp = r (VM − Vtn)
VDD + Vtp + rVtn = VM (1 + r)
VM =VDD + rVtn − |Vtp|
1 + r
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2011 by Oxford University Press, Inc.
Figure 14.21
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2011 by Oxford University Press, Inc.
Figure 14.22 Dynamic operation of a capacitively loaded CMOS inverter: (a) circuit; (b) input and output waveforms; (c) equivalent circuit during the capacitor discharge; (d) trajectory of the operating point as the input goes high and C discharges through QN.
Approach from Secs. 10.2.3/4.10 5th edition
Using piecewise integration
tPHL =1.6C
kn
W
L
nVDD
tPLH =1.6C
kp
W
L
pVDD
Equivalent to eq. 10.18 on 5th ed.
but more general
2nd approach using ave. currentDischarge
tPHL = CVDD − (VDD/2)
iav
=CVDD
2iav
iav =12
(iDN (E) + iDN (M))
iDN (E) =12k
n
W
L
n
(VDD − Vtn)2
iDN (M) =12k
n
W
L
n
(VDD − Vtn)VDD −
VDD
2
2
tPHL =αnC
kn
W
L
n
VDD
αn =2
74 −
3VtnVDD
+
VtnVDD
2
Charging
tPLH =αpC
kp
W
L
pVDD
αp =2
74 −
3|Vtp|VDD
+
Vtp
VDD
2
tp =tPHL + tPLH
2
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2011 by Oxford University Press, Inc.
Figure 14.23 Equivalent circuits for determining the propagation delays (a) tPHL and (b) tPLH of the inverter.
Another Alternative Approach
tPHL = 0.69RNC
tPLH = 0.69RPC
Empirical expressions
RN =12.5
(W/L)nkΩ
RP =30
(W/L)pkΩ
These apply for several CMOS processes
including 0.25µm, 0.18µm and 0.13µm.
3rd Alternative approach
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2011 by Oxford University Press, Inc.
Figure 14.28 Examples of pull-down networks.
Sec. 10.3 in 5th editionLogic Gates
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2011 by Oxford University Press, Inc.
Figure 14.24 Circuit for analyzing the propagation delay of the inverter formed by Q1 and Q2, which is driving a similar inverter formed by Q3 and Q4.
C = 2Cgd1 + 2Cgd2 + Cdb1 + Cdb2 + Cg3 + Cg4 + Cw
Cg3,g4 = (WL)3,4Cox + Cgsov3,gsov4 + Cgdov3,gdov4
f14.24
Sec. 10.2.3 in 5th ed.
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2011 by Oxford University Press, Inc.
Figure 14.25 The Miller multiplication of the feedback capacitance Cgd1.
Cgd1,2, Cgsov3,4 and Cgdov3,4 are overlap capacitances
Example: CMOS 0.25μm process with Cox = 6fF/μm2, μnCox = 115μA/V2, μpCox = 30μA/V2,
Vtn = - Vtp = 0.5V, and VDD = 2.5V. (W/L)n = 0.375μm/0.25μm, (W/L)p = 1.125μm/0.25μm
Cgd, Cgsov, Cgdov ⇒ 0.3fF/μm×W
Cdbn = Cdbp = 1fF , CW= 0.2fF
Find tp when the inverter is driving an identical inverter.
C = Cint + Cext
Increasing W/L by a factor S increases Cint
C = SCint0 + Cext
and decreases Req = (RN + RP )/2 by S with respect tothe original Req0.
tp = 0.69
Req0
S
(SCint0 + Cext)
= 0.69
Req0Cint0 +
1
SReq0Cext
Inverter Sizing
Example:
If the inverter in the previous example, find(a) Cint and Cext,(b) factor S to reduce extrinsic part of tp by 2,(c) resulting tp, and(d) factor by which the area is increased.
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2011 by Oxford University Press, Inc.
Figure 14.26 The current in the CMOS inverter versus the input voltage.
Ipeak =µnCox
2(W/L)n
VDD
2− Vtn
2
f14.26
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2011 by Oxford University Press, Inc.
Figure 14.27 Representation of a three-input CMOS logic gate. The PUN comprises PMOS transistors, and the PDN comprises NMOS transistors.