cmos manual 1

K.L.E. Societys

B.V. Bhoomaraddi College of Engineering & Technology, Hubli 31

DEPARTMENT OF Electronics & Communication ENGINEERING

Introduction to CADENCE design tools

The intention for this manual is to serve as an introduction to the Cadence design environment and describe the methodology used when designing integrated circuits. The Cadence tool kit consists of several programs for different applications such as schematic drawing, layout, verification, and simulation. These applications can be used on various computer platforms. The open architecture also allows for integration of tools from other vendors or of own design. The integration of all this tools is done by a program called Design Framework II (DFW). The DFW-application is the cornerstone in the Cadence environment. It provides a common user interface and a common data base to the tools used. This makes it possible to switch between different applications without having to convert the data base.

CADENCE DESIGN TOOLS

This manual will give an overview of the user interface supplied by DFW and present some of the Cadence tools that will be used. 1. Cadence User Interface: In Cadence the user interface is graphic and based on windows, forms, and menus.

The main windows of DFW are:

Command Interpreter Window (CIW) is controlling the environment. Other tools can be started from here and it also serves a log window for many applications.

Library Manager gives a view of the design libraries and the different constructions that exists therein.

Design Window (DW) shows the current design. It is possible to have several DW opened at the same time with different, or the same, tools.

Text Window (TW) show text. It can be a log or report that was asked for, or an editor.

The menus in Cadence are mostly pull-downs, i.e. the menu will appear when the title are clicked with the left button on the mouse. There are also pop-up menus that appear in the background of the design window on a middle button press. The forms are used for entering some specific information that is needed by the function called, the size of a transistor for instance.

2. The Design Process: The design tools have a common structure of the designs. It is hierarchical and consists of libraries, views, and instances.

Libraries and Views: All design data in Cadence are organized in libraries. There are Reference Libraries which contains basic building blocks usable in the construction and Design Libraries which embodies the current design.

Every library consists of cells and their different views, as in figure 1.1. A cell is a database object which forms a building block, an inverter for instance. A view represents some level of abstraction of the cell. It can be a schematic drawing, layout, or maybe some functional description.

Figure 1.1: An inverter cell with three views: layout, schematic, and symbol.3. Instances and Hierarchy

The main reason for using hierarchical designs is to save design time and minimize the size of the data base. Say that a design would need 500 gates of the same type. Then instead of building it 500 times, it is designed once and then used were it is needed. In this way one cell can be used (not copied) several times and each such use is called an instance of the cell. In order to be instantiated every cell needs a symbol view which acts as a handle to the cell it represents. Only the symbol is shown when a cell is instantiated. Thus by creating more complex structures by instantiating simple instances a hierarchical design is formed. It is possible to move up and down and work on a selected level in the hierarchy. When a design is opened, the highest level is the default one.4. The Technology File

Since there are different semiconductor processes (with different set of rules and properties), Cadence has to know the specifications for the one that is to be used. This information is stored in a set of files called Technology Files which exists on different locations on the system. When a library is created it is therefore connected to a specific technology.

The technology files contain information about:

Layer definitions: Conductors, contacts, transistors ...

Design rules: minimum size, distance to objects ...

Display: Colors and patterns to use on the screen.

Electrical properties: resistance, capacitance ...

The technology files are usually supplied by the silicon vendor that is to fabricate the design, along with some libraries of standard cells and IO pads that can be used by the designer. Such a collection is called a Design Kit.5. The Design Flow

The abbreviated flow in figure 1.2 shows some of the steps in designing integrated circuits in the Cadence environment.

Figure 1.2: The design flow.

The step Create the Design consists of drawing schematic views of all cells and blocks. The schematic view contains transistor symbols, and maybe other components such as resistors and capacitances, and wires connecting them. From the schematic view the symbol view is created (almost automatically) so that the cell can be used on a higher level in the hierarchy.

The step Analyze the design includes functional verification (simulation) of the design on a schematic level.

The third step, Create Layout, is done in a Layout Editor. Here the final semiconductor layers are represented by different colors. All the cells and blocks used have the size they will have on the final chip.

The last step is Verification of the design. The layout is examined for violations against the geometric or electrical rules, and to verify the function of the physical implementation.

6. Schematic and Symbol tools:

To create the schematic the tool Virtuoso Schematic Composer is used. This editor is an interactive system for building schematics by instantiating some basic components (transistors, capacitances, etc.) and to connect them to each other. The values (properties) of the components can be edited to suit the specifications, text and comments can also be included.

The editor will also create symbols of the cells so that they can be used in other parts of the construction.7. Simulation

The simulation tool is started directly from the schematic editor and all the necessary net-lists describing the design will be created. A simulation is usually performed in a test bench, which is also a schematic, with the actual design included as an instance. The test bench also includes signal sources and power supply. By using parameters for the properties of the components used it is possible to quickly analyze the design for a wide range of variables.

The simulator is run from within Analog Circuit Design Environment which is a tool that handles the interface between the user and the simulator. The simulator offers a wide range of analyses (DC, frequency sweep, transient, noise, etc.) and the results can be presented graphically and be saved.

The results (voltage levels, currents, noise, etc.) can be fed into a calculator which can present various parameters of the analyzed circuit - delay time, rise time, slew rate, phase margin, and many other interesting properties. It is also possible to set up algebraic expressions of in or output signal which can be plotted as a function of some other variable.

8. Layout Tool

The Virtuoso Layout Editor is used for drawing the layout. A layout consists of geometrical figures in different colors. From the size and color of these figures it is later possible to generate the final mask layers which are used in the fabrication of the design. It is possible to include other cells by instantiating their layout views. To verify that the layout fulfills all electrical and geometric rules a Design Rule Check (DRC) program is used.

7.1.1 Title of the experiment: MOSFET Device Characteristics.7.1.2 Aim or objective of the experiment: Draw the Schematic, simulate it and plot input output characteristics for nMOS and pMOS devices.7.1.3 List of equipment required to conduct the experiment with their specifications: Cadence composer-Schematic & Virtuoso for layout simulation. 7.1.4 Theoretical background for the experiment /Validation of the experiment:

The metaloxidesemiconductor field-effect transistor (MOSFET) is a transistor used for amplifying or switching electronic signals. In MOSFETs, a voltage on the oxide-insulated gate electrode can induce a conducting channel between the two other contacts called source and drain. The channel can be of n-type or p-type, and is accordingly called an nMOSFET or a pMOSFET. Figure 1 shows the schematic diagram of the structure of an nMOS device before and after channel formation.

Fig. (1a): nMOSFET before channel formation Fig. (1b): nMOSFET structure after channel formationFigure 2 shows symbols commonly used for MOSFETs where the bulk terminal is either labeled (B) or implied (not drawn). G G

S

D S

D

Fig. (2): Circuit symbols for nMOS and pMOS respectively

7.1.5 Formulae required:

7.1.6 Step by step procedure to carry out the experiment:

1. Circuit diagram to implement.

2. Schematic of the circuit diagram will drawn using Composer-Schematic of Cadence tool and simulate for DC analysis.

3. Note down the value of Vth and different region of operation for Vgs and Vds in input/ output characteristics. 4. Change W/L ratio note the change in input/ output characteristics.7.1.7 Table of observations:W/L ratioVgsVdsVthRegion

(W/L)1

(W/L)2

7.1.8 Specimen calculations: 7.1.9 Plotting of the graph: 7.1.10 Discussion of results and conclusion: 7.2.1 Title of the experiment: Static and Dynamic Characteristics of CMOS inverter.

7.2.2 Aim or objective of the experiment: Draw the Schematic; perform static and dynamic characteristics of CMOS inverter.7.2.3 List of equipment required to conduct the experiment with their specifications: Cadence composer-Schematic & Virtuoso for layout simulation. 7.2.4 Theoretical background for the experiment /Validation of the experiment:

Static Analysis: The inverter is truly the nucleus of all digital designs. Once its operation and properties are clearly understood, designing more intricate structures such as NAND gates, adders, multipliers, and microprocessors is greatly simplified. The electrical behavior of these complex circuits can be almost completely derived by extrapolating the results obtained for inverters. The analysis of inverters can be extended to explain the behavior of more complex gates such as NAND, NOR, or XOR, which in turn form the building blocks for modules such as multipliers and processors. Fig. 2.1 shows the circuit diagram of a static CMOS inverter. Its operation is readily understood with the aid of the simple switch model of the MOS transistor: the transistor is nothing more than a switch with an infinite off resistance (for |VGS| < |VT|), and a finite on resistance (for |VGS| > |VT|). This leads to the following interpretation of the inverter. When Vin is high and equal to VDD, the NMOS transistor is on, while the PMOS is off. This yields the equivalent circuit of Fig.2.2a. A direct path exists between Vout and the ground node, resulting in a steady-state value of 0V. On the other hand, when the input voltage is low (0 V), NMOS and PMOS transistors are off and on, respectively. The equivalent circuit of Figure 5.2b shows that a path exists between VDD and Vout, yielding a high output voltage. The gate clearly functions as an inverter.

Fig.2.1: CMOS Inverter

Fig.2.2: Switch models of CMOS Inverter

The nature and the form of the voltage-transfer characteristic (VTC) can be graphically deduced by superimposing the current characteristics of the NMOS and the PMOS devices. Such a graphical construction is traditionally called a load-line plot. It requires that the I-V curves of the NMOS and PMOS devices are transformed onto a common coordinate set. We have selected the input voltage Vin, the output voltage Vout and the NMOS drain current IDN as the variables of choice. The PMOS I-V relations can be translated into this variable space by the following relations (the subscripts n and p denote the NMOS and PMOS devices, respectively).Dynamic Analysis: The qualitative analysis presented earlier concluded that the propagation delay of the CMOS inverter is determined by the time it takes to charge and discharge the load capacitor CL through the PMOS and NMOS transistors, respectively. This observation suggests that getting CL as small as possible is crucial to the realization of high-performance CMOS circuits. It is hence worthwhile to first study the major components of the load capacitance before embarking onto an in-depth analysis of the propagation delay of the gate. In addition to this detailed analysis, the section also presents a summary of techniques that a designer might use to optimize the performance of the inverter.7.2.5 Formulae required: Static Analysis: Dynamic Analysis:




3. Perform DC analysis for static CMOS inverter and note down DC operating point. 4. Change W/L ratio note the change in transfer characteristics.

5. Perform transient analysis for dynamic CMOS inverter with appropriate load and calculate tpHL, tpLH and tpd.7.2.7 Table of observations:Static Analysis:W/L ratioOperating Point

(W/L)1

(W/L)2

Dynamic Analysis:

CLtpHLtpLHtp

7.2.8 Specimen calculations: 7.2.9 Plotting of the graph: 7.2.10 Discussion of results and conclusion: 7.3.1 Title of the experiment: Static and Dynamic Characteristics of CMOS NAND2 and NOR2.

7.3.2 Aim or objective of the experiment: Draw the Schematic; perform static and dynamic characteristics of CMOS NAND2 and NOR2.7.3.3 List of equipment required to conduct the experiment with their specifications: Cadence composer-Schematic & Virtuoso for layout simulation. 7.3.4 Theoretical background for the experiment /Validation of the experiment:

Static Analysis: NAND2: Complementary CMOS gates inherit all the nice properties of the basic CMOS inverter, discussed earlier. They exhibit rail to rail swing with VOH = VDD and VOL = GND. The circuits also have no static power dissipation, since the circuits are designed such that the pull-down and pull-up networks are mutually exclusive. The analysis of the DC voltage transfer characteristics and the noise margins is more complicated than for the inverter, as these parameters depend upon the data input patterns applied to gate. Consider the static two-input NAND gate shown in Fig.3.1. Three possible input combinations switch the output of the gate from high-to-low: (a) A = B = 0 to 1, (b) A= 1, B = 0 to 1, and (c) B= 1, A = 0 to 1. The resulting voltage transfer curves display significant differences. The large variation between case (a) and the others (b & c) is explained by the fact that in the former case both transistors in the pull-up network are on simultaneously for A=B=0, representing a strong pull-up. In the latter cases, only one of the pull up devices is on. The difference between (b) and (c) results mainly from the state of the internal node int between the two NMOS devices. For the NMOS devices to turn on, both gate-tosource voltages must be above VTn, with VGS2 = VA - VDS1 and VGS1 = VB. The threshold voltage of transistor M2 will be higher than transistor M1 due to the body effect. The threshold voltages of the two devices are given by:

For case (b), M3 is turned off, and the gate voltage of M2 is set to VDD. To a first order, M2 may be considered as a resistor in series with M1. Since the drive on M2 is large, this resistance is small and has only a small effect on the voltage transfer characteristics. In case (c), transistor M1 acts as a resistor, causing body effect in M2.

Fig.3.1: Schematic and VTC of NAND2 Dynamic Analysis: The computation of propagation delay proceeds in a fashion similar to the static inverter. For the purpose of delay analysis, each transistor is modeled as a resistor in series with an ideal switch. The value of the resistance is dependent on the power supply voltage and an equivalent large signal resistance, scaled by the ratio of device width over length, must be used. The logic is transformed into an equivalent RC network that includes the effect of internal node capacitances. Fig. 3.2 shows the two-input NAND gate and its equivalent RC switch level model. Note that the internal node capacitance Cint attributable to the source/drain regions and the gate overlap capacitance of M2/M1 is included. While complicating the analysis, the capacitance of the internal nodes can have quite an impact in some networks such as large fan-in gates.

Fig.3.2: Equivalent RC model for NAND2

NOR2: The CMOS implementation of a NOR gate (F = A + B) is shown in Fig.3.3. The output of this network is high, if and only if both inputs A and B are low. The worst-case pull-down transition happens when only one of the NMOS devices turns on (i.e., if either A or B is high). Assume that the goal is to size the NOR gate such that it has approximately the same delay as an inverter with the following device sizes: NMOS 0.5mm/0.25mm and PMOS 1.5mm/0.25mm. Since the pull-down path in the worst case is a single device, the NMOS devices (M1 and M2) can have the same device widths as the NMOS device in the inverter. For the output to be pulled high, both devices must be turned on. Since the resistances add, the devices must be made two times larger compared to the PMOS in the inverter (i.e., M3 and M4 must have a size of 3mm/0.25mm). Since PMOS devices have a lower mobility relative to NMOS devices, stacking devices in series must be avoided as much as possible. A NAND implementation is clearly preferred over a NOR implementation for implementing generic logic.

Fig.3.3: Equivalent RC model for NOR2

7.3.5 Formulae required: Static Analysis: Dynamic Analysis:




3. Perform DC analysis for static CMOS inverter and note down DC operating point. 4. Change W/L ratio note the change in transfer characteristics.

5. Perform transient analysis for dynamic CMOS inverter with appropriate load and calculate tpHL, tpLH and tpd.7.3.7 Table of observations:Static Analysis:GateW/L ratioOperating Point

NAND2(W/L)1

(W/L)2

NOR2(W/L)1

(W/L)2

Dynamic Analysis:

GateCLtpHLtpLHtp

NAND2

NOR2

7.3.8 Specimen calculations: 7.3.9 Plotting of the graph: 7.3.10 Discussion of results and conclusion: 7.4.1 Title of the experiment: Layout of CMOS Inverter.7.4.2 Aim or objective of the experiment: Verify the Schematic and Layout of inverter by performing DRC (Design Rule Check) and LVS (Layout versus Schematic) and also performs RC extraction.7.4.3 List of equipment required to conduct the experiment with their specifications: Cadence composer-Schematic & Virtuoso for layout simulation. 7.4.4 Theoretical background for the experiment /Validation of the experiment:

Fig.4.1: Schematic and Layout of CMOS Inverter.

7.4.5 Formulae required: NA7.4.6 Step by step procedure to carry out the experiment:



3. Draw the layout using Virtuoso Layout. 4. Perform different analysis.7.4.7 Table of observations: VinVout

01

10

7.4.8 Specimen calculations: NA

7.4.9 Plotting of the graph: NA7.4.10 Discussion of results and conclusion: 7.5.1 Title of the experiment: Layout of CMOS NAND, CMOS NOR, and CMOS XOR.

7.5.2 Aim or objective of the experiment: Verify the Schematic and Layout of inverter by performing DRC (Design Rule Check) and LVS (Layout versus Schematic).

7.5.3 List of equipment required to conduct the experiment with their specifications: Cadence composer-Schematic & Virtuoso for layout simulation. 7.5.4 Theoretical background for the experiment /Validation of the experiment:CMOS NAND:

Fig.4.1: Schematic and Layout of CMOS NAND2CMOS NOR:

Fig.4.2: Schematic and Layout of CMOS NOR2

CMOS XOR:

Fig.4.3: Schematic and Layout of CMOS XOR2

7.5.5 Formulae required: NA7.5.6 Step by step procedure to carry out the experiment:



3. Draw the layout using Virtuoso Layout.

4. Perform different analysis.7.5.7 Table of observations:

AB~(A.B)~(A+B)AB

00110

01101

10101

11000

7.5.8 Specimen calculations: NA

7.5.9 Plotting of the graph: NA

7.5.10 Discussion of results and conclusion: EMBED Unknown

_1470139970.unknown

_1470139969.unknown

cmos manual 1

Documents