CMOS Process Integration

ECE/ChE 4752: Microelectronics ECE/ChE 4752: Microelectronics Processing LaboratoryProcessing Laboratory

Gary S. May

March 25, 2004

Outline

IntroductionIntroduction MOSFET FabricationMOSFET Fabrication CMOS TechnologyCMOS Technology Well FormationWell Formation Advanced IsolationAdvanced Isolation

MOSFET MOSFET = “Metal-Oxide-Semiconductor Field-Effect

Transistor” At present, the MOSFET is the dominant device in GSI

circuits because it can be scaled to smaller dimensions than other types of devices.

The dominant technology for MOSFET is CMOS (complementary MOSFET), in which both n-channel and p-channel devices are provided on the same chip.

CMOS technology has the lowest power consumption of all IC technology.

MOSFET Scaling

In 1970s, gate length was 7.5 m and device area was ~ 6000 m2.

For present-day MOSFETs, the gate length is < 0.10 m.

Outline

IntroductionIntroduction MOSFET FabricationMOSFET Fabrication CMOS TechnologyCMOS Technology Well FormationWell Formation Advanced IsolationAdvanced Isolation

n-Channel MOSFET

Process Sequence Start w/ Start w/ pp-type, lightly doped -type, lightly doped

(~10(~101515 cm cm–3–3), <100>-oriented ), <100>-oriented Si. Si.

Form oxide isolation region (a).Form oxide isolation region (a). Define active area with Define active area with

photoresist mask and boron photoresist mask and boron chanstop layer implanted chanstop layer implanted through nitride-oxide layer (b).through nitride-oxide layer (b).

Grow gate oxide (< 10 nm) and adjust threshold voltage by implanting B ions (enhancement-mode device) (c).

Form gate by depositing doped polysilicon. Pattern gate in Pattern gate in source and drain regions (d).source and drain regions (d).

Process Sequence (cont.) Implant arsenic (~30 keV, Implant arsenic (~30 keV,

~5 × 10~5 × 101515 cm cm–2–2) to form ) to form source and drain (a).source and drain (a).

P-glass is deposited and P-glass is deposited and flowed (b). flowed (b).

Contact windows defined Contact windows defined and etched in P-glass. Al and etched in P-glass. Al is deposited and patterned is deposited and patterned (c). (c).

Top view of completed Top view of completed MOSFET (d). MOSFET (d).

Outline

IntroductionIntroduction MOSFET FabricationMOSFET Fabrication CMOS TechnologyCMOS Technology Well FormationWell Formation Advanced IsolationAdvanced Isolation

CMOS Inverter Schematic

Gate of upper PMOS device connected to the gate of lower NMOS device.

Functions as a digital switch

Low power consumption (~ nW) is most attractive feature

CMOS Inverter Layout

CMOS Processing

p-well is implanted and driven into p-well is implanted and driven into nn-substrate (-substrate (pp-type dopant -type dopant concentration must be high enough to overcompensate the concentration must be high enough to overcompensate the nn--substrate background doping). substrate background doping).

Subsequent processes for Subsequent processes for nn-channel MOSFET in -channel MOSFET in pp-well are identical -well are identical to nMOSFET.to nMOSFET.

For For pp-channel MOSFET, B ions are implanted into -channel MOSFET, B ions are implanted into nn-substrate to -substrate to form source and drainform source and drain

Because of Because of pp-well and steps needed for p-FET, the number of steps -well and steps needed for p-FET, the number of steps in CMOS fabrication is double that to make NMOS. in CMOS fabrication is double that to make NMOS.

Outline

IntroductionIntroduction MOSFET FabricationMOSFET Fabrication CMOS TechnologyCMOS Technology Well FormationWell Formation Advanced IsolationAdvanced Isolation

Well Types Single well – discussed previously Twin well

p-well and n-well side-by-side on lightly doped substrate

Disadvantage: needs high temperature processing (above 1050 oC) and a long diffusion time (>8 hours) to achieve the required well depth of 2 – 3 m

Retrograde To reduce process temperature and time, high-energy

implantation is used The profile of the well in this case can have a peak

at a certain depth in the silicon substrate.

Retrograde Wells

Advantages:Advantages: Reduced lateral Reduced lateral

diffusion and increase diffusion and increase the device density. the device density.

Lower well resistivity Lower well resistivity Chanstop can be Chanstop can be

formed at the same formed at the same time as well time as well implantationimplantation

Outline

IntroductionIntroduction MOSFET FabricationMOSFET Fabrication CMOS TechnologyCMOS Technology Well FormationWell Formation Advanced IsolationAdvanced Isolation

Conventional Isolation

Conventional MOS isolation process has disadvantages for Conventional MOS isolation process has disadvantages for deep-submicron (< 0.25 deep-submicron (< 0.25 m) fabrication:m) fabrication: High-temperature and long oxidation time result in High-temperature and long oxidation time result in

encroachment of chanstop implantation to the active encroachment of chanstop implantation to the active region, causing a threshold voltage shift. region, causing a threshold voltage shift.

Area of the active region is reduced because of lateral Area of the active region is reduced because of lateral oxidationoxidation

Field oxide thickness is significantly less than that Field oxide thickness is significantly less than that grown in wider spacingsgrown in wider spacings

Trench isolation technology can avoid these problems. Trench isolation technology can avoid these problems.

Shallow Trench Isolation

(a) Patterning (a) Patterning

(b) Trench area etched (b) Trench area etched

(c) Trench re-filled with (c) Trench re-filled with oxide oxide

(d) Chemical-mechanical (d) Chemical-mechanical polishing removes the polishing removes the oxide on the nitride to oxide on the nitride to get a flat surfaceget a flat surface