VLSI Design

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CMOS Processing Technology

CHAPTER 2

VLSI Design

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Outline 2

1. CMOS Technologies

2. Layout Design Rules

3. CMOS Process Enhancements

4. Technology-related CAD Issues

5. Manufacturing Issues

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CMOS Technologies 3

• n-well Process : p-substrate

• p-well Process : n-substrate

• Twin-well Process – Optimized for each transistor type

• Triple-well Process (deep n-well) – Good isolation between analog & digital blocks

• BiCMOS Process (SiGe)

• Silicon-on-insulator (SOI) Process

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Process Steps 4

• Wafer formation

• Photolithography

• Well and Channel formation

• Isolation

• Gate oxide

• Gate & Source/Drain formation

• Contacts & Metalization

• Passivation

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Photolithography 5

• Resolution enhancement techniques

– Optical proximity correction (OPC) : local distortion, Phase shift masks (PSM): light diffraction, Off-axis illumination (OAI): contrast enhancement of repetitive pattern.

• Greek: Photo(light)+lithos(stone)+graphe(picture) – Carving pictures in stone using light

http://nano.nchc.org.tw/dictionary/Optical_Lithography.html

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Well and Channel Formation 6

• Vary portions of donor(n) & acceptor(p)

– Epitaxy: single-crystal film growth

– Deposition: Chemical Vapor Deposition (CVD) + Drive-in

– Implantation: ion implantation + diffusion + anneal (standard well and source/drain definition)

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Schematic and Layout of CMOS Inverter 7

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Cross Section of CMOS Inverter 8

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Photomasks of n-well CMOS Inverter 9

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n-Well CMOS Process - 1 10

(a) Define n-well diffusion (mask #1)

(b) Define active regions thin oxide (mask #2)

(d) Polysilicon gate (mask #3) (c) LOCOS oxidation field oxide

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n-Well CMOS Process - 2 11

(h) Metallization (mask #7) (g) Contact holes (mask #6)

(e) n+ diffusion (mask #4) (f) p+ diffusion (mask #5)

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Cross-Sectional Diagram of MOSFET 12

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Silicon Dioxide (SiO2) 13

• Wet oxidation – Oxidizing atmosphere contains water vapor, Temp:

900~1000oC, quick for thick oxides.

• Dry oxidation – Oxidizing atmosphere is pure oxygen, Temp: ~1200oC,

highly controlled thin oxides.

• Atomic layer deposition – Thin chemical layer deposition for various requirement

(SiO2, metal, dielectrics)

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Isolation : LOCOS 14

• LOCOS : Local Oxidation of Silicon – Low density, high electrical field : bird’s beak

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Isolation : STI 15

• STI : Shallow Trench Isolation – High density & better isolation, need Chemical Mechanical

Polishing (CMP) to planarize the structure.

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Gate Oxide 16

• Shorter gate L thinner gate oxide

• EOT : Effective Oxide Thickness – Use stack gate

structure with high-K dielectric to decrease EOT.

• Dual gate oxide for core and I/O.

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Gate & Source/Drain Formation 17

• Self-aligned poly-silicon (poly) gate

• Lightly doped drain (LDD) structure

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LDD & Salicide 18

• LDD – Reduce electrical field of drain

junction & hot-electron damage

– High sheet resistance

• Salicide : self-aligned silicide – Refractory metal to reduce the

interconnection resistance of gate, source/drain.

• CMP : – Structure planarization for further

stack process.

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Chemical Mechanical Polishing (CMP) 19

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Contacts & Metallization 20

• Contact – Metal Poly, Metal Diffusion

• VIA – Metal Metal

• CMP : – Structure planarization for further stack process.

VLSI Design

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Outline 21

1. CMOS Technologies

2. Layout Design Rules

3. CMOS Process Enhancements

4. Technology-related CAD Issues

5. Manufacturing Issues

VLSI Design

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Chih-Cheng Hsieh

Layout Design Rule 22

• Design rule: geometric constraint and tolerance for high probability of correct fabrication.

– Feature size, separations and overlaps.

• Well rule : isolation

• Transistor rule : channel quality

– Poly, active region, n+/p+ implant.

• Contact : single size for precisely process control

• Metal & Via rule: productivity & conductivity

– Top metal with loser size, space and via rules.

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N-well Process Transistor 23

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Design Rule 24

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Micron Design Rule 25

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Outline 26

1. CMOS Technologies

2. Layout Design Rules

3. CMOS Process Enhancements

4. Technology-related CAD Issues

5. Manufacturing Issues

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CMOS Process Enhancement 27

• Multiple threshold voltage & oxide thickness

– Low core voltage for low power

– High I/O voltage for interface compatibility

• Silicon on Insulator : higher speed

• High-K gate dielectrics : thinner EOT

• Higher mobility : SiGe BJT, strained silicon

• Low-leakage transistor : finFET, gate-all-around (GAA) FET

• Plastic Transistors : flexible electronic paper

• High-voltage transistor : LCD driver, power electronics

• Copper interconnection : high conductivity

• Low-K dielectrics : low wire capacitance

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Silicon on Insulator 28

• Pros. – No capacitance between

source/drain and body higher speed device.

– No Latch-up.

• Cons. – Floating body history effect

– Self heating effect.

– Parasitic BJT pass-gate leakage

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High-K & Higher Mobility 29

Mark Bohr, “The New Era of Scaling in an SoC World”, Plenary session, ISSCC 2009

SiGe bipolar transistor Strained Silicon High-K + Metal Gate

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FinFET & GAA Structure 30

Mark Bohr, “The New Era of Scaling in an SoC World”, Plenary session, ISSCC 2009

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Transistor Scaling 31

http://isscc.org/media/2012/plenary/David_Perlmutter/SilverlightLoader.html

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Plastic Transistor 32

Electronic Paper

Plastic transistor structure & process flow

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Copper Interconnect 33

• Copper atoms diffuse into the silicon and dielectrics, destroying transistors

– Barrier layers are necessary

• The processing required to etch copper wires is tricky.

• Copper oxide forms readily and interferes with good contacts.

• Care has to be taken not to introduce copper into the environment as a pollutant

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Copper Damascene Process 34

• Pros. : High conductivity

• Cons. :Complex process

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Capacitors 35

MiM Capacitor Fringe Capacitor

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MIM vs. MOM 36

• Metal-Insulator-Metal

— Need extra layer

— More routing capability

• Metal-Oxide-Metal

— Free with modern process

— More layers : higher density

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Resistor & Conductor 37

Non-silicide high-resistivity Poly resistor

Planar spiral Inductor

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Memory Category 38

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Non-Volatile Memory (NVM) 39

• Mask-programmed ROM (Read-Only Memory) – NOT programmable after manufacture.

• One-Time Programmable (OTP) memory – Fuse constructed programming flow

• EPROM: Electrically Programmable ROM – Electrical Programming, UV Erase

• EEPROM: Electrically Erasable PROM – Electrical Programming & Erase, Byte-level programming.

• Flash – Block-level programming, faster & cheaper than EEPROM

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Flash Memory 40

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BJT in CMOS Process 41

• Usage : bandgap voltage reference

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MEMS 42

• Micro Electro Mechanical Systems (MEMS)

• Actuator

• Comb drive

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Carbon Nanotube (CNT) Transistor 43

• Smaller channel length

• Higher speed

• Lower power

• Better electrical performance than Si but complex process

IBM CNTFET

VLSI Design

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Outline 44

1. CMOS Technologies

2. Layout Design Rules

3. CMOS Process Enhancements

4. Technology-related CAD Issues

5. Manufacturing Issues

VLSI Design

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Design Rule Check (DRC) 45

• Tolerate nonideal effects and guarantee device successful fabrication: Mask alignment error

SiO2

SiO2

p substrate

n well

PMOS Region

SiO2

SiO2

p substrate

n well

p+ Poly

p+ p+ n+

SiO2

SiO2

p substrate

n well

PMOS Region

SiO2

SiO2

p substrate

n well

p+ Poly

p+ p+ n+

Short

Shift

Ex: alignment of N well and active region masks

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Design Rule Check (DRC) 46

• Exposure and etching variation – Ex: different contact windows different contact resistance

SiO2

SiO2

P substrate

N well

P+ P+ N+

Contact widows

Minimum

width

Minimum

spacing

Poly overlap

Poly-contact

spacing

Contact overlap Poly-diff.

spacing

Contact

overlap

Resolution Alignment

• Two types of design rules

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Design Rule Check (DRC) 47

• Minimum channel width

– CO.W.1 + 2 CO.E.1

• Minimize S/D diffusion width (xd)

– CO.W.1 + CO.E.1 + CO.C.1

xd

xd

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Layout v.s. Schematic (LVS) 48

• Guarantee the layout is the same as the simulated netlist

– Check device parameters, interconnections and i/o ports.

Model name

Channel width

Channel length

VDD

VO VI

GND

VDD

GND

VI VO

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Parasitic Extraction (PEX) 49

• Evaluate interconnection RC effects

VDD

GND

VI VO

VDD

GND

VI VO

VDD

GND

VI VO

Only C effect Only R effect

VDD

GND

VI VO

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Gate Layout Slide 50

• Layout can be very time consuming

– Design gates to fit together nicely

– Build a library of standard cells

• Standard cell design methodology

– VDD and GND should abut (standard height)

– Adjacent gates should satisfy design rules

– nMOS at bottom and pMOS at top

– All gates include well and substrate contacts

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Example: Inverter Slide 51

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Simplified λ-Based Design Rules 52

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Example: NAND3 53

• Horizontal N-diffusion and p-diffusion strips

• Vertical polysilicon gates

• Metal1 VDD rail at top

• Metal1 GND rail at bottom

• 32 l by 40 l

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Stick Diagrams 54

• Stick diagrams help plan layout quickly

– Need not be to scale

– Draw with color pencils or dry-erase markers

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Wiring Tracks 55

• A wiring track is the space required for a wire

– 4 l width, 4 l spacing from neighbor = 8 l pitch

• Transistors also consume one wiring track

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Well spacing 56

• Wells must surround transistors by 6 l

– Implies 12 l between opposite transistor flavors

– Leaves room for one wire track

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Area Estimation 57

• Estimate area by counting wiring tracks

– Multiply by 8 to express in l

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Example: O3AI 58

• Sketch a stick diagram for O3AI and estimate area

– Y A B C D

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Example: O3AI 59

• Sketch a stick diagram for O3AI and estimate area

– Y A B C D

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Outline 60

1. CMOS Technologies

2. Layout Design Rules

3. CMOS Process Enhancements

4. Technology-related CAD Issues

5. Manufacturing Issues

VLSI Design

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Chih-Cheng Hsieh

Antenna Rules 61

Maximum area of metal connected to gate without discharge element

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Layer Density Rule 62

• CMP & Uniform etch process requirement : Planarization

• Solution : Pattern Fill (by CAD)

Reference: http://www.edadesignline.com/howto/198100760;jsessionid=EWGKEU5KZKDCVQE1GHPSKH4ATMY32JVN?pgno=2