cmos vlsi design (a3425) - wordpress.com · 2019-03-30 · cmos vlsi design (a3425) unit v dynamic...

Vardhaman COllege of Engineering 3/30/2019

Department of Electronics and

Communication Engineering 1

CMOS VLSI Design (A3425)

Unit V

Dynamic Logic Concept Circuits

Contents

• Charge Leakage

• Charge Sharing

• The Dynamic RAM Cell

• Clocks and Synchronization

• Clocked-CMOS

• Clock Generation Circuits




Introduction

• In the static logic circuits discussed up to this point,the output is valid so long as the inputs are welldefined.

• A dynamic logic circuit, on the other hand, gives aresult at the output that is only valid for a shortperiod of time.

• If the result is not used immediately, the voltage maychange in time and give an incorrect output value.

Charge Sharing

• Another important problem that occurs in dynamiccircuit is that of charge sharing.

• This occurs when the charge on an isolated capacitivenode is used to drive another isolated capacitive node.

• The two capacitors C1 and C2 represent parasiticcontributions due to the physical structure of thetransistors. Suppose that initially nFET M1 is ONwhile M2 is in cutoff.

• Capacitor C1 charges to a voltage VI=Vmax giving it a total charge of




Charge Sharing

Charge Sharing

• Suppose that the FETs are switched at time t=0, sothat M1 is OFF and M2 is ON.

• Since there is a difference in voltage between theleft and right sides of the transistor, drain currentID flows in the direction shown.

• This removes charge from C1 and adds it to C2. sothat the charge is shared between the twocapacitors. Since the individual charges are given by




Charge Sharing

• We see that the current off of C1 causes V1 todecrease while V increases. Eventually, equilibrium isreached where the two capacitors have the same finalvoltage

Charge Sharing

• The total charge in the network is now distributedaccording to

• By inspection method, Vf < Vmax

• For Logic 1; C1 > C2 � Vf ≈ Vmax

• For Logic 0; C1 < C2 � Vf << Vmax

• Since the voltage difference between the two sides is zero, the current flow also goes to zero.




RC Equivalent

• It is useful to examine the charge sharing problem byusing an RC model for the MOSFET.

• For times t<0, the switch is open with a gate signalG=0 and the voltages are given by V1=Vmax and V2 =0v.

•• Closing the switch at t = 0, gives the voltage across

the resistor as

RC Equivalent




RC Equivalent

• Current I through the resistor is,

RC Equivalent

• The case where C1 > C2

• The case where C1 < C2




RC Equivalent

• The chargesharing analysiscan be extendedto the case ofdriving multiplecapacitors suchas shown in fig.

The Dynamic RAM cell

• A dynamic random-access memory (DRAM) cell is astorage circuit that consists of an access transistorMA and a storage capacitor Cs.

• The access FET is controlled by the Word line signalWL, and the bit line is the input/output path.

• The simplicity of the circuit makes it very attractivefor high-density storage.

• there are three distinct operations for a cell:– Write - A data bit is stored in the circuit;

– Hold - The value of the data bit is maintained in the cell;

– Read - The value of the data bit is transferred to anexternal circuit






Write:

• To store a logic 1 in the cell, Vin is set to the value ofVDD so that the storage cell voltage Vs increasesaccording to

• Storage of a logic 0 is accomplished by using an inputvoltage of Vin = 0v so that the capacitor is dischargedas described by





Hold:

• A DRAM cell holds the charge on the capacitor byturning off the access transistor using WL = 0.

• This creates an isolated node, and charge leakageoccurs if a logic 1 high voltage is stored on Cs.

• The maximum hold time tH for a logic 1 bit can beestimated by


Read:

• A read operation is performed When the date bit lineis connected to high gain sense amplifier.





Read:

• The data voltage is given by,

• Voltage after charge sharing is given by,

Clocks and Synchronization

• Data flow through a complex logic network is usuallycontrolled by a clock signal ϕ(t).

• A clock voltage that has a period T in seconds that defines the time for waveform to repeat itself. The frequency f of the clock is related to the period by

• is the voltage associated with ϕ(t)




Clocks and Synchronization

Shift Registers

• This network is designed to move a data bit oneposition to the right during each half-cycle of theclock

• A data bit is admitted to the first stage when ϕ=1,andis transferred to stage 2 when ϕ goes to 0.

• Each successive bit entered into the system followsthe previous bit, resulting in the movement from leftto right.

• It is clear from the operation of the circuit that theelectronic characteristics of the circuit will placesome limitation on the clock frequency




Shift Registers

Shift Registers




Shift Registers

• During the next portion of the clock cycle when ϕ andVϕ=0v, the pass transistor M1 is in cutoff.

• During this time, charge leakage will occur and thevoltage V1 across C1 will decay from its original valueof Vmax.

• The minimum value at the inverter input that will stillbe interpreted as a logic 1 value is VIH, so that themaximum hold time is estimated by

Shift Registers

• We assumed a 50% duty cycle; this means that theclock has a high value for 50% of the period. Asapplied to the circuit

• This sets the maximum clock frequency as




TGs as Control Elements

Extension to General Clocked Systems




Extension to General Clocked Systems

Clocked – CMOS

• Clocked-CMOS (C2MOS) is a logic family thatcombines static logic design with the synchronizationachieved by using clock signals.

• The inputs A, B, and C are connected tocomplementary nFET/pFET pairs as in ordinary staticdesign where they act like open or closed switches.

• The only modification is the insertion of two clockedFETs between the logic arrays and the output.




Clocked – CMOS

Clocked – CMOS




Clocked – CMOS

for a logic 0

for a logic 1

Clocked – CMOS




Clocked – CMOS

cmos vlsi design (a3425) - wordpress.com · 2019-03-30 · cmos vlsi design (a3425) unit v dynamic...

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