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Vardhaman College of Engineering 3/30/2019
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CMOS VLSI Design (A3425)
Unit III
Static Logic Gates
Introduction
• A static logic gate is one that has a well definedoutput once the inputs are stabilized and theswitching transients have decayed away.
• Static CMOS logic gates are relatively easy to designand use.
• This chapter deals with the static logic gates, fromsimple NAND and NOR operations to complexfunctions that are quite large and powerful.
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General Structure
• Static CMOS logic gates are constructed usingcompletely symmetric nMOS and pMOS transistorarrays.
• Complex logic gates are constructed using the CMOSinverter as a basis.
• In order to construct a complex logic gate, let usreplace the single inverter nFET by an array of nFETsthat are connected to operate as a large switch.
• Similarly, we will substitute an array of pFETs for thesingle pFET used in the inverter, and view the pFETarray as a “giant” switch.
Steps to Create Complex Gates
The general structure of a complex logic gate can be createdby the following steps.
• Provide a complementary pair (an nFET and a pFET with acommon gate) for each input;
• Replace the single nFET with an array of nFETs thatconnects the output to ground;
• Replace the single pFET with an array of pFETs thatconnects the output to VDD;
• Design the nFET and pFET switching network so that onlyone network acts as a closed switch for any given inputcombination.
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General Structure of a Static Logic Gate
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Transient Analysis
• When analyzing the output transients,
nFET and pFET to Logic Gate Equivalence
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Exclusive OR and Equivalence Gates
Exclusive OR and Equivalence Gates
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• The XOR operation is used extensively in severaltypes of logic networks including adder circuits andparity checkers.
• The philosophy of mirror circuits can be betterunderstood by considering a 2 variable gate.
• The possible input combinations are
• Since the XOR function has the form
Mirror Circuits
• Since the XOR function has the form
• This means that the combinations shouldprovide the connections from the output to the powersupply, while should connect the output toground.
• Similarly, the function for XNOR (Equivalence Gate)is
Mirror Circuits
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• Uses the same transistor topology for the nFET andpFET networks.
• When there are equal numbers of input combinationsproducing 0s and 1s.– XOR
– XNOR
• Advantages:– More symmetric layouts
– Shorter rise and fall times
Mirror Circuits
Mirror Circuits
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Mirror Circuits
Mirror Circuits
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Full Adder Circuits
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NOR Based SR Latch
NOR Based SR Latch
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SRAM
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SRAM
Tri-State Output Circuits
• Static logic gates provide logic 0 and logic 1 outputvalues by connecting the output node to either groundor to the power supply.
• Static Logic – Two States - 0 and 1
• A tri-state output circuit is designed to give thesetwo logic states, but also provides for a third high-impedance (Hi-Z) state in which the output node isfloating.
• Tri-State Output Logic – Three States – 0, 1 and Hi-Z
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Tri-State Output Circuits
• Figure shows tri-state circuit that uses the enable signalEn to switch between normal and Hi-Z operation.
• pFET is controlled by the function
• nFET is controlled by the function
• If En=0, then fp=1, fn=0 which
drives both FETs into cutoff, producing the Hi-Z state.
• If En=1, then fp=D’, fn=D’ which allows the input D tocontrol the transistors
Tri-State Output Circuits
• Figure below reverses the roll of the tri-state control bymoving the location of the inverter.
• The FET inputs are controlled by
• This results in the circuit that gives a Hi-Z output statewhen the control bit Hi is 1 and normal operation withHi=0.
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Tri-State Output Circuits
• Figure below shows another tri-state circuit.
• In the circuit, the Hi-Z control
variable X is applied directly
to the tri-state pFET MpX
while X’ is applied to MnX.
• If X=0, then both FETs are
active and the gate produces
an output of D’.
• A Hi-Z state is achieved with
X=1, since this turns both
tri-state FETs OFF.
Psuedo-nMOS Logic Gates
• nMOS logic family uses only nFETs
• Pseudo-nMOS logic resemble the nMOS logic with activepull-up (pFET).
• Figure shows a basic nMOS inverter
• A single nFET MD is a driver device
that controls the circuit.
• The output node is connected to the
power supply through a load resistor
RL that acts as a pull-up device
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Psuedo-nMOS Logic Gates
Operation
• For Vin<VTn, the driver MD is in cutoff giving ID=0
• Since the load current is equal to the driver current, thevoltage across the load resistor is VL=ILRL = 0V
• The output voltage is given by
Psuedo-nMOS Logic GatesOperation
• When a high input voltage Vin = VDD is applied MD conductsbut the resistor still tries to pull up the output voltage.
• This keeps Vout from ever reaching 0V so that the outputlow voltage VOL is always greater than zero: VOL > 0.
• Psuedo-nMOS logic gate replaces the resistor with abiased-on pFET as shown in figure below.
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Psuedo-nMOS Logic GatesDC Characteristics and Operation
• pFET voltages are given by
• pFET is always biased into active region and cannot beturned off.
• For Vin<VTn, nFET is cutoff and Vout = VDD = VOH
• For Vin>VTn, Mn turns into conduction, Vin = VDD = VOH
• VOL is small � Mn is non-saturated
• VOL<|VTp|,
Psuedo-nMOS Logic Gatesdriver-to-load ratio
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Complex Logic in Psuedo-nMOS
Simplified XNOR Gate
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Compact XOR and Equivalence Gates
Alternate XOR and XNOR Gates
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Alternate XOR and XNOR Gates
Schmitt Trigger Circuits• VTC exhibits hysteresis
• Forward characteristics are different from the reversecharacteristics
• When Vin = 0�VDD, the transition takes place at theforward switching voltage V+.
• When Vin = VDD�0, the transition takes place at thereverse switching voltage V-.
• The hysteresis voltage VH = V+-V-
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• A symmetrical CMOS Schmitt trigger circuit is shown infigure below.
• pFET circuit is the mirror image of the nFET circuit.
• The forward switching is controlled by the nFETs whilethe reverse switching is determined by the pFETs.
Schmitt Trigger Circuits
Forward switching voltage V+:
• Mn2 is the main switching device. Mn1 and Mn3 acts as feedbacknetwork which controls the value of V+.
• Assume that the input is set to Vin = 0 and then increased; all ofnFETs are initially in cutoff.
• Conduction depends on the gate-source voltages
• Mn1 turns ON when VGS1=VT1
• Mn2 requires an input voltage of
Schmitt Trigger Circuits
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• V+ can be estimated by ignoring body bias effects.
• To turn on Mn2 requires a drain-source voltage of
• Mn1 is in saturation with a current of
• Mn3 is also saturated (since VGS3=VDS3) with a current of
• Equating current I1=I3 and rearranging gives
• Similarly, the reverse trigger voltage V- is given by
Schmitt Trigger Circuits
Reverse switching voltage V-:
• Mp4 is in saturation with a current of
• Mp6 is also saturated with a current of
Where
• Equating I4=I6 and rearranging gives
Schmitt Trigger Circuits
( )24
4
2DD Tp
I V V Vβ −= − −
( )26
6
2Tp
I V Vγβ
= −Tp
V V Vγ−= −
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• This CMOS circuit allows for designing a symmetric triggerwhere
• Hysteresis voltage is given by
Schmitt Trigger Circuits
Alternate Schmitt Trigger